MCInstrDesc.h revision 22fee2dff4c43b551aefa44a96ca74fcade6bfac
1//===-- llvm/Mc/McInstrDesc.h - Instruction Descriptors -*- C++ -*-===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This file defines the MCOperandInfo and MCInstrDesc classes, which 11// are used to describe target instructions and their operands. 12// 13//===----------------------------------------------------------------------===// 14 15#ifndef LLVM_MC_MCINSTRDESC_H 16#define LLVM_MC_MCINSTRDESC_H 17 18#include "llvm/Support/DataTypes.h" 19 20namespace llvm { 21 22//===----------------------------------------------------------------------===// 23// Machine Operand Flags and Description 24//===----------------------------------------------------------------------===// 25 26namespace MCOI { 27 // Operand constraints 28 enum OperandConstraint { 29 TIED_TO = 0, // Must be allocated the same register as. 30 EARLY_CLOBBER // Operand is an early clobber register operand 31 }; 32 33 /// OperandFlags - These are flags set on operands, but should be considered 34 /// private, all access should go through the MCOperandInfo accessors. 35 /// See the accessors for a description of what these are. 36 enum OperandFlags { 37 LookupPtrRegClass = 0, 38 Predicate, 39 OptionalDef 40 }; 41} 42 43/// MCOperandInfo - This holds information about one operand of a machine 44/// instruction, indicating the register class for register operands, etc. 45/// 46class MCOperandInfo { 47public: 48 /// RegClass - This specifies the register class enumeration of the operand 49 /// if the operand is a register. If isLookupPtrRegClass is set, then this is 50 /// an index that is passed to TargetRegisterInfo::getPointerRegClass(x) to 51 /// get a dynamic register class. 52 short RegClass; 53 54 /// Flags - These are flags from the MCOI::OperandFlags enum. 55 unsigned short Flags; 56 57 /// Lower 16 bits are used to specify which constraints are set. The higher 16 58 /// bits are used to specify the value of constraints (4 bits each). 59 unsigned Constraints; 60 /// Currently no other information. 61 62 /// isLookupPtrRegClass - Set if this operand is a pointer value and it 63 /// requires a callback to look up its register class. 64 bool isLookupPtrRegClass() const { return Flags&(1 <<MCOI::LookupPtrRegClass);} 65 66 /// isPredicate - Set if this is one of the operands that made up of 67 /// the predicate operand that controls an isPredicable() instruction. 68 bool isPredicate() const { return Flags & (1 << MCOI::Predicate); } 69 70 /// isOptionalDef - Set if this operand is a optional def. 71 /// 72 bool isOptionalDef() const { return Flags & (1 << MCOI::OptionalDef); } 73}; 74 75 76//===----------------------------------------------------------------------===// 77// Machine Instruction Flags and Description 78//===----------------------------------------------------------------------===// 79 80/// MCInstrDesc flags - These should be considered private to the 81/// implementation of the MCInstrDesc class. Clients should use the predicate 82/// methods on MCInstrDesc, not use these directly. These all correspond to 83/// bitfields in the MCInstrDesc::Flags field. 84namespace MCID { 85 enum { 86 Variadic = 0, 87 HasOptionalDef, 88 Return, 89 Call, 90 Barrier, 91 Terminator, 92 Branch, 93 IndirectBranch, 94 Compare, 95 MoveImm, 96 Bitcast, 97 DelaySlot, 98 FoldableAsLoad, 99 MayLoad, 100 MayStore, 101 Predicable, 102 NotDuplicable, 103 UnmodeledSideEffects, 104 Commutable, 105 ConvertibleTo3Addr, 106 UsesCustomInserter, 107 Rematerializable, 108 CheapAsAMove, 109 ExtraSrcRegAllocReq, 110 ExtraDefRegAllocReq 111 }; 112} 113 114/// MCInstrDesc - Describe properties that are true of each instruction in the 115/// target description file. This captures information about side effects, 116/// register use and many other things. There is one instance of this struct 117/// for each target instruction class, and the MachineInstr class points to 118/// this struct directly to describe itself. 119class MCInstrDesc { 120public: 121 unsigned short Opcode; // The opcode number 122 unsigned short NumOperands; // Num of args (may be more if variable_ops) 123 unsigned short NumDefs; // Num of args that are definitions 124 unsigned short SchedClass; // enum identifying instr sched class 125 const char * Name; // Name of the instruction record in td file 126 unsigned Flags; // Flags identifying machine instr class 127 uint64_t TSFlags; // Target Specific Flag values 128 const unsigned *ImplicitUses; // Registers implicitly read by this instr 129 const unsigned *ImplicitDefs; // Registers implicitly defined by this instr 130 const MCOperandInfo *OpInfo; // 'NumOperands' entries about operands 131 132 /// getOperandConstraint - Returns the value of the specific constraint if 133 /// it is set. Returns -1 if it is not set. 134 int getOperandConstraint(unsigned OpNum, 135 MCOI::OperandConstraint Constraint) const { 136 if (OpNum < NumOperands && 137 (OpInfo[OpNum].Constraints & (1 << Constraint))) { 138 unsigned Pos = 16 + Constraint * 4; 139 return (int)(OpInfo[OpNum].Constraints >> Pos) & 0xf; 140 } 141 return -1; 142 } 143 144 /// getOpcode - Return the opcode number for this descriptor. 145 unsigned getOpcode() const { 146 return Opcode; 147 } 148 149 /// getName - Return the name of the record in the .td file for this 150 /// instruction, for example "ADD8ri". 151 const char *getName() const { 152 return Name; 153 } 154 155 /// getNumOperands - Return the number of declared MachineOperands for this 156 /// MachineInstruction. Note that variadic (isVariadic() returns true) 157 /// instructions may have additional operands at the end of the list, and note 158 /// that the machine instruction may include implicit register def/uses as 159 /// well. 160 unsigned getNumOperands() const { 161 return NumOperands; 162 } 163 164 /// getNumDefs - Return the number of MachineOperands that are register 165 /// definitions. Register definitions always occur at the start of the 166 /// machine operand list. This is the number of "outs" in the .td file, 167 /// and does not include implicit defs. 168 unsigned getNumDefs() const { 169 return NumDefs; 170 } 171 172 /// isVariadic - Return true if this instruction can have a variable number of 173 /// operands. In this case, the variable operands will be after the normal 174 /// operands but before the implicit definitions and uses (if any are 175 /// present). 176 bool isVariadic() const { 177 return Flags & (1 << MCID::Variadic); 178 } 179 180 /// hasOptionalDef - Set if this instruction has an optional definition, e.g. 181 /// ARM instructions which can set condition code if 's' bit is set. 182 bool hasOptionalDef() const { 183 return Flags & (1 << MCID::HasOptionalDef); 184 } 185 186 /// getImplicitUses - Return a list of registers that are potentially 187 /// read by any instance of this machine instruction. For example, on X86, 188 /// the "adc" instruction adds two register operands and adds the carry bit in 189 /// from the flags register. In this case, the instruction is marked as 190 /// implicitly reading the flags. Likewise, the variable shift instruction on 191 /// X86 is marked as implicitly reading the 'CL' register, which it always 192 /// does. 193 /// 194 /// This method returns null if the instruction has no implicit uses. 195 const unsigned *getImplicitUses() const { 196 return ImplicitUses; 197 } 198 199 /// getNumImplicitUses - Return the number of implicit uses this instruction 200 /// has. 201 unsigned getNumImplicitUses() const { 202 if (ImplicitUses == 0) return 0; 203 unsigned i = 0; 204 for (; ImplicitUses[i]; ++i) /*empty*/; 205 return i; 206 } 207 208 /// getImplicitDefs - Return a list of registers that are potentially 209 /// written by any instance of this machine instruction. For example, on X86, 210 /// many instructions implicitly set the flags register. In this case, they 211 /// are marked as setting the FLAGS. Likewise, many instructions always 212 /// deposit their result in a physical register. For example, the X86 divide 213 /// instruction always deposits the quotient and remainder in the EAX/EDX 214 /// registers. For that instruction, this will return a list containing the 215 /// EAX/EDX/EFLAGS registers. 216 /// 217 /// This method returns null if the instruction has no implicit defs. 218 const unsigned *getImplicitDefs() const { 219 return ImplicitDefs; 220 } 221 222 /// getNumImplicitDefs - Return the number of implicit defs this instruction 223 /// has. 224 unsigned getNumImplicitDefs() const { 225 if (ImplicitDefs == 0) return 0; 226 unsigned i = 0; 227 for (; ImplicitDefs[i]; ++i) /*empty*/; 228 return i; 229 } 230 231 /// hasImplicitUseOfPhysReg - Return true if this instruction implicitly 232 /// uses the specified physical register. 233 bool hasImplicitUseOfPhysReg(unsigned Reg) const { 234 if (const unsigned *ImpUses = ImplicitUses) 235 for (; *ImpUses; ++ImpUses) 236 if (*ImpUses == Reg) return true; 237 return false; 238 } 239 240 /// hasImplicitDefOfPhysReg - Return true if this instruction implicitly 241 /// defines the specified physical register. 242 bool hasImplicitDefOfPhysReg(unsigned Reg) const { 243 if (const unsigned *ImpDefs = ImplicitDefs) 244 for (; *ImpDefs; ++ImpDefs) 245 if (*ImpDefs == Reg) return true; 246 return false; 247 } 248 249 /// getSchedClass - Return the scheduling class for this instruction. The 250 /// scheduling class is an index into the InstrItineraryData table. This 251 /// returns zero if there is no known scheduling information for the 252 /// instruction. 253 /// 254 unsigned getSchedClass() const { 255 return SchedClass; 256 } 257 258 bool isReturn() const { 259 return Flags & (1 << MCID::Return); 260 } 261 262 bool isCall() const { 263 return Flags & (1 << MCID::Call); 264 } 265 266 /// isBarrier - Returns true if the specified instruction stops control flow 267 /// from executing the instruction immediately following it. Examples include 268 /// unconditional branches and return instructions. 269 bool isBarrier() const { 270 return Flags & (1 << MCID::Barrier); 271 } 272 273 /// isTerminator - Returns true if this instruction part of the terminator for 274 /// a basic block. Typically this is things like return and branch 275 /// instructions. 276 /// 277 /// Various passes use this to insert code into the bottom of a basic block, 278 /// but before control flow occurs. 279 bool isTerminator() const { 280 return Flags & (1 << MCID::Terminator); 281 } 282 283 /// isBranch - Returns true if this is a conditional, unconditional, or 284 /// indirect branch. Predicates below can be used to discriminate between 285 /// these cases, and the TargetInstrInfo::AnalyzeBranch method can be used to 286 /// get more information. 287 bool isBranch() const { 288 return Flags & (1 << MCID::Branch); 289 } 290 291 /// isIndirectBranch - Return true if this is an indirect branch, such as a 292 /// branch through a register. 293 bool isIndirectBranch() const { 294 return Flags & (1 << MCID::IndirectBranch); 295 } 296 297 /// isConditionalBranch - Return true if this is a branch which may fall 298 /// through to the next instruction or may transfer control flow to some other 299 /// block. The TargetInstrInfo::AnalyzeBranch method can be used to get more 300 /// information about this branch. 301 bool isConditionalBranch() const { 302 return isBranch() & !isBarrier() & !isIndirectBranch(); 303 } 304 305 /// isUnconditionalBranch - Return true if this is a branch which always 306 /// transfers control flow to some other block. The 307 /// TargetInstrInfo::AnalyzeBranch method can be used to get more information 308 /// about this branch. 309 bool isUnconditionalBranch() const { 310 return isBranch() & isBarrier() & !isIndirectBranch(); 311 } 312 313 // isPredicable - Return true if this instruction has a predicate operand that 314 // controls execution. It may be set to 'always', or may be set to other 315 /// values. There are various methods in TargetInstrInfo that can be used to 316 /// control and modify the predicate in this instruction. 317 bool isPredicable() const { 318 return Flags & (1 << MCID::Predicable); 319 } 320 321 /// isCompare - Return true if this instruction is a comparison. 322 bool isCompare() const { 323 return Flags & (1 << MCID::Compare); 324 } 325 326 /// isMoveImmediate - Return true if this instruction is a move immediate 327 /// (including conditional moves) instruction. 328 bool isMoveImmediate() const { 329 return Flags & (1 << MCID::MoveImm); 330 } 331 332 /// isBitcast - Return true if this instruction is a bitcast instruction. 333 /// 334 bool isBitcast() const { 335 return Flags & (1 << MCID::Bitcast); 336 } 337 338 /// isNotDuplicable - Return true if this instruction cannot be safely 339 /// duplicated. For example, if the instruction has a unique labels attached 340 /// to it, duplicating it would cause multiple definition errors. 341 bool isNotDuplicable() const { 342 return Flags & (1 << MCID::NotDuplicable); 343 } 344 345 /// hasDelaySlot - Returns true if the specified instruction has a delay slot 346 /// which must be filled by the code generator. 347 bool hasDelaySlot() const { 348 return Flags & (1 << MCID::DelaySlot); 349 } 350 351 /// canFoldAsLoad - Return true for instructions that can be folded as 352 /// memory operands in other instructions. The most common use for this 353 /// is instructions that are simple loads from memory that don't modify 354 /// the loaded value in any way, but it can also be used for instructions 355 /// that can be expressed as constant-pool loads, such as V_SETALLONES 356 /// on x86, to allow them to be folded when it is beneficial. 357 /// This should only be set on instructions that return a value in their 358 /// only virtual register definition. 359 bool canFoldAsLoad() const { 360 return Flags & (1 << MCID::FoldableAsLoad); 361 } 362 363 //===--------------------------------------------------------------------===// 364 // Side Effect Analysis 365 //===--------------------------------------------------------------------===// 366 367 /// mayLoad - Return true if this instruction could possibly read memory. 368 /// Instructions with this flag set are not necessarily simple load 369 /// instructions, they may load a value and modify it, for example. 370 bool mayLoad() const { 371 return Flags & (1 << MCID::MayLoad); 372 } 373 374 375 /// mayStore - Return true if this instruction could possibly modify memory. 376 /// Instructions with this flag set are not necessarily simple store 377 /// instructions, they may store a modified value based on their operands, or 378 /// may not actually modify anything, for example. 379 bool mayStore() const { 380 return Flags & (1 << MCID::MayStore); 381 } 382 383 /// hasUnmodeledSideEffects - Return true if this instruction has side 384 /// effects that are not modeled by other flags. This does not return true 385 /// for instructions whose effects are captured by: 386 /// 387 /// 1. Their operand list and implicit definition/use list. Register use/def 388 /// info is explicit for instructions. 389 /// 2. Memory accesses. Use mayLoad/mayStore. 390 /// 3. Calling, branching, returning: use isCall/isReturn/isBranch. 391 /// 392 /// Examples of side effects would be modifying 'invisible' machine state like 393 /// a control register, flushing a cache, modifying a register invisible to 394 /// LLVM, etc. 395 /// 396 bool hasUnmodeledSideEffects() const { 397 return Flags & (1 << MCID::UnmodeledSideEffects); 398 } 399 400 //===--------------------------------------------------------------------===// 401 // Flags that indicate whether an instruction can be modified by a method. 402 //===--------------------------------------------------------------------===// 403 404 /// isCommutable - Return true if this may be a 2- or 3-address 405 /// instruction (of the form "X = op Y, Z, ..."), which produces the same 406 /// result if Y and Z are exchanged. If this flag is set, then the 407 /// TargetInstrInfo::commuteInstruction method may be used to hack on the 408 /// instruction. 409 /// 410 /// Note that this flag may be set on instructions that are only commutable 411 /// sometimes. In these cases, the call to commuteInstruction will fail. 412 /// Also note that some instructions require non-trivial modification to 413 /// commute them. 414 bool isCommutable() const { 415 return Flags & (1 << MCID::Commutable); 416 } 417 418 /// isConvertibleTo3Addr - Return true if this is a 2-address instruction 419 /// which can be changed into a 3-address instruction if needed. Doing this 420 /// transformation can be profitable in the register allocator, because it 421 /// means that the instruction can use a 2-address form if possible, but 422 /// degrade into a less efficient form if the source and dest register cannot 423 /// be assigned to the same register. For example, this allows the x86 424 /// backend to turn a "shl reg, 3" instruction into an LEA instruction, which 425 /// is the same speed as the shift but has bigger code size. 426 /// 427 /// If this returns true, then the target must implement the 428 /// TargetInstrInfo::convertToThreeAddress method for this instruction, which 429 /// is allowed to fail if the transformation isn't valid for this specific 430 /// instruction (e.g. shl reg, 4 on x86). 431 /// 432 bool isConvertibleTo3Addr() const { 433 return Flags & (1 << MCID::ConvertibleTo3Addr); 434 } 435 436 /// usesCustomInsertionHook - Return true if this instruction requires 437 /// custom insertion support when the DAG scheduler is inserting it into a 438 /// machine basic block. If this is true for the instruction, it basically 439 /// means that it is a pseudo instruction used at SelectionDAG time that is 440 /// expanded out into magic code by the target when MachineInstrs are formed. 441 /// 442 /// If this is true, the TargetLoweringInfo::InsertAtEndOfBasicBlock method 443 /// is used to insert this into the MachineBasicBlock. 444 bool usesCustomInsertionHook() const { 445 return Flags & (1 << MCID::UsesCustomInserter); 446 } 447 448 /// isRematerializable - Returns true if this instruction is a candidate for 449 /// remat. This flag is deprecated, please don't use it anymore. If this 450 /// flag is set, the isReallyTriviallyReMaterializable() method is called to 451 /// verify the instruction is really rematable. 452 bool isRematerializable() const { 453 return Flags & (1 << MCID::Rematerializable); 454 } 455 456 /// isAsCheapAsAMove - Returns true if this instruction has the same cost (or 457 /// less) than a move instruction. This is useful during certain types of 458 /// optimizations (e.g., remat during two-address conversion or machine licm) 459 /// where we would like to remat or hoist the instruction, but not if it costs 460 /// more than moving the instruction into the appropriate register. Note, we 461 /// are not marking copies from and to the same register class with this flag. 462 bool isAsCheapAsAMove() const { 463 return Flags & (1 << MCID::CheapAsAMove); 464 } 465 466 /// hasExtraSrcRegAllocReq - Returns true if this instruction source operands 467 /// have special register allocation requirements that are not captured by the 468 /// operand register classes. e.g. ARM::STRD's two source registers must be an 469 /// even / odd pair, ARM::STM registers have to be in ascending order. 470 /// Post-register allocation passes should not attempt to change allocations 471 /// for sources of instructions with this flag. 472 bool hasExtraSrcRegAllocReq() const { 473 return Flags & (1 << MCID::ExtraSrcRegAllocReq); 474 } 475 476 /// hasExtraDefRegAllocReq - Returns true if this instruction def operands 477 /// have special register allocation requirements that are not captured by the 478 /// operand register classes. e.g. ARM::LDRD's two def registers must be an 479 /// even / odd pair, ARM::LDM registers have to be in ascending order. 480 /// Post-register allocation passes should not attempt to change allocations 481 /// for definitions of instructions with this flag. 482 bool hasExtraDefRegAllocReq() const { 483 return Flags & (1 << MCID::ExtraDefRegAllocReq); 484 } 485}; 486 487} // end namespace llvm 488 489#endif 490