MCInstrDesc.h revision 39bdc5526f9bb4985c5ea7711e603bb44707ed42
1//===-- llvm/Mc/McInstrDesc.h - Instruction Descriptors -*- C++ -*-===//
2//
3//                     The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10// This file defines the MCOperandInfo and MCInstrDesc classes, which
11// are used to describe target instructions and their operands.
12//
13//===----------------------------------------------------------------------===//
14
15#ifndef LLVM_MC_MCINSTRDESC_H
16#define LLVM_MC_MCINSTRDESC_H
17
18#include "llvm/Support/DataTypes.h"
19
20namespace llvm {
21
22//===----------------------------------------------------------------------===//
23// Machine Operand Flags and Description
24//===----------------------------------------------------------------------===//
25
26namespace MCOI {
27  // Operand constraints
28  enum OperandConstraint {
29    TIED_TO = 0,    // Must be allocated the same register as.
30    EARLY_CLOBBER   // Operand is an early clobber register operand
31  };
32
33  /// OperandFlags - These are flags set on operands, but should be considered
34  /// private, all access should go through the MCOperandInfo accessors.
35  /// See the accessors for a description of what these are.
36  enum OperandFlags {
37    LookupPtrRegClass = 0,
38    Predicate,
39    OptionalDef
40  };
41
42  /// Operand Type - Operands are tagged with one of the values of this enum.
43  enum OperandType {
44    OPERAND_UNKNOWN,
45    OPERAND_IMMEDIATE,
46    OPERAND_REGISTER,
47    OPERAND_MEMORY,
48    OPERAND_PCREL
49  };
50}
51
52/// MCOperandInfo - This holds information about one operand of a machine
53/// instruction, indicating the register class for register operands, etc.
54///
55class MCOperandInfo {
56public:
57  /// RegClass - This specifies the register class enumeration of the operand
58  /// if the operand is a register.  If isLookupPtrRegClass is set, then this is
59  /// an index that is passed to TargetRegisterInfo::getPointerRegClass(x) to
60  /// get a dynamic register class.
61  int16_t RegClass;
62
63  /// Flags - These are flags from the MCOI::OperandFlags enum.
64  uint8_t Flags;
65
66  /// OperandType - Information about the type of the operand.
67  uint8_t OperandType;
68
69  /// Lower 16 bits are used to specify which constraints are set. The higher 16
70  /// bits are used to specify the value of constraints (4 bits each).
71  uint32_t Constraints;
72  /// Currently no other information.
73
74  /// isLookupPtrRegClass - Set if this operand is a pointer value and it
75  /// requires a callback to look up its register class.
76  bool isLookupPtrRegClass() const {return Flags&(1 <<MCOI::LookupPtrRegClass);}
77
78  /// isPredicate - Set if this is one of the operands that made up of
79  /// the predicate operand that controls an isPredicable() instruction.
80  bool isPredicate() const { return Flags & (1 << MCOI::Predicate); }
81
82  /// isOptionalDef - Set if this operand is a optional def.
83  ///
84  bool isOptionalDef() const { return Flags & (1 << MCOI::OptionalDef); }
85};
86
87
88//===----------------------------------------------------------------------===//
89// Machine Instruction Flags and Description
90//===----------------------------------------------------------------------===//
91
92/// MCInstrDesc flags - These should be considered private to the
93/// implementation of the MCInstrDesc class.  Clients should use the predicate
94/// methods on MCInstrDesc, not use these directly.  These all correspond to
95/// bitfields in the MCInstrDesc::Flags field.
96namespace MCID {
97  enum {
98    Variadic = 0,
99    HasOptionalDef,
100    Pseudo,
101    Return,
102    Call,
103    Barrier,
104    Terminator,
105    Branch,
106    IndirectBranch,
107    Compare,
108    MoveImm,
109    Bitcast,
110    DelaySlot,
111    FoldableAsLoad,
112    MayLoad,
113    MayStore,
114    Predicable,
115    NotDuplicable,
116    UnmodeledSideEffects,
117    Commutable,
118    ConvertibleTo3Addr,
119    UsesCustomInserter,
120    HasPostISelHook,
121    Rematerializable,
122    CheapAsAMove,
123    ExtraSrcRegAllocReq,
124    ExtraDefRegAllocReq
125  };
126}
127
128/// MCInstrDesc - Describe properties that are true of each instruction in the
129/// target description file.  This captures information about side effects,
130/// register use and many other things.  There is one instance of this struct
131/// for each target instruction class, and the MachineInstr class points to
132/// this struct directly to describe itself.
133class MCInstrDesc {
134public:
135  unsigned short  Opcode;        // The opcode number
136  unsigned short  NumOperands;   // Num of args (may be more if variable_ops)
137  unsigned short  NumDefs;       // Num of args that are definitions
138  unsigned short  SchedClass;    // enum identifying instr sched class
139  unsigned short  Size;          // Number of bytes in encoding.
140  unsigned        Flags;         // Flags identifying machine instr class
141  uint64_t        TSFlags;       // Target Specific Flag values
142  const uint16_t *ImplicitUses;  // Registers implicitly read by this instr
143  const uint16_t *ImplicitDefs;  // Registers implicitly defined by this instr
144  const MCOperandInfo *OpInfo;   // 'NumOperands' entries about operands
145
146  /// getOperandConstraint - Returns the value of the specific constraint if
147  /// it is set. Returns -1 if it is not set.
148  int getOperandConstraint(unsigned OpNum,
149                           MCOI::OperandConstraint Constraint) const {
150    if (OpNum < NumOperands &&
151        (OpInfo[OpNum].Constraints & (1 << Constraint))) {
152      unsigned Pos = 16 + Constraint * 4;
153      return (int)(OpInfo[OpNum].Constraints >> Pos) & 0xf;
154    }
155    return -1;
156  }
157
158  /// getOpcode - Return the opcode number for this descriptor.
159  unsigned getOpcode() const {
160    return Opcode;
161  }
162
163  /// getNumOperands - Return the number of declared MachineOperands for this
164  /// MachineInstruction.  Note that variadic (isVariadic() returns true)
165  /// instructions may have additional operands at the end of the list, and note
166  /// that the machine instruction may include implicit register def/uses as
167  /// well.
168  unsigned getNumOperands() const {
169    return NumOperands;
170  }
171
172  /// getNumDefs - Return the number of MachineOperands that are register
173  /// definitions.  Register definitions always occur at the start of the
174  /// machine operand list.  This is the number of "outs" in the .td file,
175  /// and does not include implicit defs.
176  unsigned getNumDefs() const {
177    return NumDefs;
178  }
179
180  /// getFlags - Return flags of this instruction.
181  ///
182  unsigned getFlags() const { return Flags; }
183
184  /// isVariadic - Return true if this instruction can have a variable number of
185  /// operands.  In this case, the variable operands will be after the normal
186  /// operands but before the implicit definitions and uses (if any are
187  /// present).
188  bool isVariadic() const {
189    return Flags & (1 << MCID::Variadic);
190  }
191
192  /// hasOptionalDef - Set if this instruction has an optional definition, e.g.
193  /// ARM instructions which can set condition code if 's' bit is set.
194  bool hasOptionalDef() const {
195    return Flags & (1 << MCID::HasOptionalDef);
196  }
197
198  /// isPseudo - Return true if this is a pseudo instruction that doesn't
199  /// correspond to a real machine instruction.
200  ///
201  bool isPseudo() const {
202    return Flags & (1 << MCID::Pseudo);
203  }
204
205  bool isReturn() const {
206    return Flags & (1 << MCID::Return);
207  }
208
209  bool isCall() const {
210    return Flags & (1 << MCID::Call);
211  }
212
213  /// isBarrier - Returns true if the specified instruction stops control flow
214  /// from executing the instruction immediately following it.  Examples include
215  /// unconditional branches and return instructions.
216  bool isBarrier() const {
217    return Flags & (1 << MCID::Barrier);
218  }
219
220  /// isTerminator - Returns true if this instruction part of the terminator for
221  /// a basic block.  Typically this is things like return and branch
222  /// instructions.
223  ///
224  /// Various passes use this to insert code into the bottom of a basic block,
225  /// but before control flow occurs.
226  bool isTerminator() const {
227    return Flags & (1 << MCID::Terminator);
228  }
229
230  /// isBranch - Returns true if this is a conditional, unconditional, or
231  /// indirect branch.  Predicates below can be used to discriminate between
232  /// these cases, and the TargetInstrInfo::AnalyzeBranch method can be used to
233  /// get more information.
234  bool isBranch() const {
235    return Flags & (1 << MCID::Branch);
236  }
237
238  /// isIndirectBranch - Return true if this is an indirect branch, such as a
239  /// branch through a register.
240  bool isIndirectBranch() const {
241    return Flags & (1 << MCID::IndirectBranch);
242  }
243
244  /// isConditionalBranch - Return true if this is a branch which may fall
245  /// through to the next instruction or may transfer control flow to some other
246  /// block.  The TargetInstrInfo::AnalyzeBranch method can be used to get more
247  /// information about this branch.
248  bool isConditionalBranch() const {
249    return isBranch() & !isBarrier() & !isIndirectBranch();
250  }
251
252  /// isUnconditionalBranch - Return true if this is a branch which always
253  /// transfers control flow to some other block.  The
254  /// TargetInstrInfo::AnalyzeBranch method can be used to get more information
255  /// about this branch.
256  bool isUnconditionalBranch() const {
257    return isBranch() & isBarrier() & !isIndirectBranch();
258  }
259
260  // isPredicable - Return true if this instruction has a predicate operand that
261  // controls execution.  It may be set to 'always', or may be set to other
262  /// values.   There are various methods in TargetInstrInfo that can be used to
263  /// control and modify the predicate in this instruction.
264  bool isPredicable() const {
265    return Flags & (1 << MCID::Predicable);
266  }
267
268  /// isCompare - Return true if this instruction is a comparison.
269  bool isCompare() const {
270    return Flags & (1 << MCID::Compare);
271  }
272
273  /// isMoveImmediate - Return true if this instruction is a move immediate
274  /// (including conditional moves) instruction.
275  bool isMoveImmediate() const {
276    return Flags & (1 << MCID::MoveImm);
277  }
278
279  /// isBitcast - Return true if this instruction is a bitcast instruction.
280  ///
281  bool isBitcast() const {
282    return Flags & (1 << MCID::Bitcast);
283  }
284
285  /// isNotDuplicable - Return true if this instruction cannot be safely
286  /// duplicated.  For example, if the instruction has a unique labels attached
287  /// to it, duplicating it would cause multiple definition errors.
288  bool isNotDuplicable() const {
289    return Flags & (1 << MCID::NotDuplicable);
290  }
291
292  /// hasDelaySlot - Returns true if the specified instruction has a delay slot
293  /// which must be filled by the code generator.
294  bool hasDelaySlot() const {
295    return Flags & (1 << MCID::DelaySlot);
296  }
297
298  /// canFoldAsLoad - Return true for instructions that can be folded as
299  /// memory operands in other instructions. The most common use for this
300  /// is instructions that are simple loads from memory that don't modify
301  /// the loaded value in any way, but it can also be used for instructions
302  /// that can be expressed as constant-pool loads, such as V_SETALLONES
303  /// on x86, to allow them to be folded when it is beneficial.
304  /// This should only be set on instructions that return a value in their
305  /// only virtual register definition.
306  bool canFoldAsLoad() const {
307    return Flags & (1 << MCID::FoldableAsLoad);
308  }
309
310  //===--------------------------------------------------------------------===//
311  // Side Effect Analysis
312  //===--------------------------------------------------------------------===//
313
314  /// mayLoad - Return true if this instruction could possibly read memory.
315  /// Instructions with this flag set are not necessarily simple load
316  /// instructions, they may load a value and modify it, for example.
317  bool mayLoad() const {
318    return Flags & (1 << MCID::MayLoad);
319  }
320
321
322  /// mayStore - Return true if this instruction could possibly modify memory.
323  /// Instructions with this flag set are not necessarily simple store
324  /// instructions, they may store a modified value based on their operands, or
325  /// may not actually modify anything, for example.
326  bool mayStore() const {
327    return Flags & (1 << MCID::MayStore);
328  }
329
330  /// hasUnmodeledSideEffects - Return true if this instruction has side
331  /// effects that are not modeled by other flags.  This does not return true
332  /// for instructions whose effects are captured by:
333  ///
334  ///  1. Their operand list and implicit definition/use list.  Register use/def
335  ///     info is explicit for instructions.
336  ///  2. Memory accesses.  Use mayLoad/mayStore.
337  ///  3. Calling, branching, returning: use isCall/isReturn/isBranch.
338  ///
339  /// Examples of side effects would be modifying 'invisible' machine state like
340  /// a control register, flushing a cache, modifying a register invisible to
341  /// LLVM, etc.
342  ///
343  bool hasUnmodeledSideEffects() const {
344    return Flags & (1 << MCID::UnmodeledSideEffects);
345  }
346
347  //===--------------------------------------------------------------------===//
348  // Flags that indicate whether an instruction can be modified by a method.
349  //===--------------------------------------------------------------------===//
350
351  /// isCommutable - Return true if this may be a 2- or 3-address
352  /// instruction (of the form "X = op Y, Z, ..."), which produces the same
353  /// result if Y and Z are exchanged.  If this flag is set, then the
354  /// TargetInstrInfo::commuteInstruction method may be used to hack on the
355  /// instruction.
356  ///
357  /// Note that this flag may be set on instructions that are only commutable
358  /// sometimes.  In these cases, the call to commuteInstruction will fail.
359  /// Also note that some instructions require non-trivial modification to
360  /// commute them.
361  bool isCommutable() const {
362    return Flags & (1 << MCID::Commutable);
363  }
364
365  /// isConvertibleTo3Addr - Return true if this is a 2-address instruction
366  /// which can be changed into a 3-address instruction if needed.  Doing this
367  /// transformation can be profitable in the register allocator, because it
368  /// means that the instruction can use a 2-address form if possible, but
369  /// degrade into a less efficient form if the source and dest register cannot
370  /// be assigned to the same register.  For example, this allows the x86
371  /// backend to turn a "shl reg, 3" instruction into an LEA instruction, which
372  /// is the same speed as the shift but has bigger code size.
373  ///
374  /// If this returns true, then the target must implement the
375  /// TargetInstrInfo::convertToThreeAddress method for this instruction, which
376  /// is allowed to fail if the transformation isn't valid for this specific
377  /// instruction (e.g. shl reg, 4 on x86).
378  ///
379  bool isConvertibleTo3Addr() const {
380    return Flags & (1 << MCID::ConvertibleTo3Addr);
381  }
382
383  /// usesCustomInsertionHook - Return true if this instruction requires
384  /// custom insertion support when the DAG scheduler is inserting it into a
385  /// machine basic block.  If this is true for the instruction, it basically
386  /// means that it is a pseudo instruction used at SelectionDAG time that is
387  /// expanded out into magic code by the target when MachineInstrs are formed.
388  ///
389  /// If this is true, the TargetLoweringInfo::InsertAtEndOfBasicBlock method
390  /// is used to insert this into the MachineBasicBlock.
391  bool usesCustomInsertionHook() const {
392    return Flags & (1 << MCID::UsesCustomInserter);
393  }
394
395  /// hasPostISelHook - Return true if this instruction requires *adjustment*
396  /// after instruction selection by calling a target hook. For example, this
397  /// can be used to fill in ARM 's' optional operand depending on whether
398  /// the conditional flag register is used.
399  bool hasPostISelHook() const {
400    return Flags & (1 << MCID::HasPostISelHook);
401  }
402
403  /// isRematerializable - Returns true if this instruction is a candidate for
404  /// remat.  This flag is deprecated, please don't use it anymore.  If this
405  /// flag is set, the isReallyTriviallyReMaterializable() method is called to
406  /// verify the instruction is really rematable.
407  bool isRematerializable() const {
408    return Flags & (1 << MCID::Rematerializable);
409  }
410
411  /// isAsCheapAsAMove - Returns true if this instruction has the same cost (or
412  /// less) than a move instruction. This is useful during certain types of
413  /// optimizations (e.g., remat during two-address conversion or machine licm)
414  /// where we would like to remat or hoist the instruction, but not if it costs
415  /// more than moving the instruction into the appropriate register. Note, we
416  /// are not marking copies from and to the same register class with this flag.
417  bool isAsCheapAsAMove() const {
418    return Flags & (1 << MCID::CheapAsAMove);
419  }
420
421  /// hasExtraSrcRegAllocReq - Returns true if this instruction source operands
422  /// have special register allocation requirements that are not captured by the
423  /// operand register classes. e.g. ARM::STRD's two source registers must be an
424  /// even / odd pair, ARM::STM registers have to be in ascending order.
425  /// Post-register allocation passes should not attempt to change allocations
426  /// for sources of instructions with this flag.
427  bool hasExtraSrcRegAllocReq() const {
428    return Flags & (1 << MCID::ExtraSrcRegAllocReq);
429  }
430
431  /// hasExtraDefRegAllocReq - Returns true if this instruction def operands
432  /// have special register allocation requirements that are not captured by the
433  /// operand register classes. e.g. ARM::LDRD's two def registers must be an
434  /// even / odd pair, ARM::LDM registers have to be in ascending order.
435  /// Post-register allocation passes should not attempt to change allocations
436  /// for definitions of instructions with this flag.
437  bool hasExtraDefRegAllocReq() const {
438    return Flags & (1 << MCID::ExtraDefRegAllocReq);
439  }
440
441
442  /// getImplicitUses - Return a list of registers that are potentially
443  /// read by any instance of this machine instruction.  For example, on X86,
444  /// the "adc" instruction adds two register operands and adds the carry bit in
445  /// from the flags register.  In this case, the instruction is marked as
446  /// implicitly reading the flags.  Likewise, the variable shift instruction on
447  /// X86 is marked as implicitly reading the 'CL' register, which it always
448  /// does.
449  ///
450  /// This method returns null if the instruction has no implicit uses.
451  const uint16_t *getImplicitUses() const {
452    return ImplicitUses;
453  }
454
455  /// getNumImplicitUses - Return the number of implicit uses this instruction
456  /// has.
457  unsigned getNumImplicitUses() const {
458    if (ImplicitUses == 0) return 0;
459    unsigned i = 0;
460    for (; ImplicitUses[i]; ++i) /*empty*/;
461    return i;
462  }
463
464  /// getImplicitDefs - Return a list of registers that are potentially
465  /// written by any instance of this machine instruction.  For example, on X86,
466  /// many instructions implicitly set the flags register.  In this case, they
467  /// are marked as setting the FLAGS.  Likewise, many instructions always
468  /// deposit their result in a physical register.  For example, the X86 divide
469  /// instruction always deposits the quotient and remainder in the EAX/EDX
470  /// registers.  For that instruction, this will return a list containing the
471  /// EAX/EDX/EFLAGS registers.
472  ///
473  /// This method returns null if the instruction has no implicit defs.
474  const uint16_t *getImplicitDefs() const {
475    return ImplicitDefs;
476  }
477
478  /// getNumImplicitDefs - Return the number of implicit defs this instruction
479  /// has.
480  unsigned getNumImplicitDefs() const {
481    if (ImplicitDefs == 0) return 0;
482    unsigned i = 0;
483    for (; ImplicitDefs[i]; ++i) /*empty*/;
484    return i;
485  }
486
487  /// hasImplicitUseOfPhysReg - Return true if this instruction implicitly
488  /// uses the specified physical register.
489  bool hasImplicitUseOfPhysReg(unsigned Reg) const {
490    if (const uint16_t *ImpUses = ImplicitUses)
491      for (; *ImpUses; ++ImpUses)
492        if (*ImpUses == Reg) return true;
493    return false;
494  }
495
496  /// hasImplicitDefOfPhysReg - Return true if this instruction implicitly
497  /// defines the specified physical register.
498  bool hasImplicitDefOfPhysReg(unsigned Reg) const {
499    if (const uint16_t *ImpDefs = ImplicitDefs)
500      for (; *ImpDefs; ++ImpDefs)
501        if (*ImpDefs == Reg) return true;
502    return false;
503  }
504
505  /// getSchedClass - Return the scheduling class for this instruction.  The
506  /// scheduling class is an index into the InstrItineraryData table.  This
507  /// returns zero if there is no known scheduling information for the
508  /// instruction.
509  ///
510  unsigned getSchedClass() const {
511    return SchedClass;
512  }
513
514  /// getSize - Return the number of bytes in the encoding of this instruction,
515  /// or zero if the encoding size cannot be known from the opcode.
516  unsigned getSize() const {
517    return Size;
518  }
519
520  /// findFirstPredOperandIdx() - Find the index of the first operand in the
521  /// operand list that is used to represent the predicate. It returns -1 if
522  /// none is found.
523  int findFirstPredOperandIdx() const {
524    if (isPredicable()) {
525      for (unsigned i = 0, e = getNumOperands(); i != e; ++i)
526        if (OpInfo[i].isPredicate())
527          return i;
528    }
529    return -1;
530  }
531};
532
533} // end namespace llvm
534
535#endif
536