MCInstrDesc.h revision 4815d56bb2c356a610f46753c5f1cefafa113b21
1//===-- llvm/Mc/McInstrDesc.h - Instruction Descriptors -*- C++ -*-===//
2//
3//                     The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10// This file defines the MCOperandInfo and MCInstrDesc classes, which
11// are used to describe target instructions and their operands.
12//
13//===----------------------------------------------------------------------===//
14
15#ifndef LLVM_MC_MCINSTRDESC_H
16#define LLVM_MC_MCINSTRDESC_H
17
18#include "llvm/Support/DataTypes.h"
19
20namespace llvm {
21
22//===----------------------------------------------------------------------===//
23// Machine Operand Flags and Description
24//===----------------------------------------------------------------------===//
25
26namespace MCOI {
27  // Operand constraints
28  enum OperandConstraint {
29    TIED_TO = 0,    // Must be allocated the same register as.
30    EARLY_CLOBBER   // Operand is an early clobber register operand
31  };
32
33  /// OperandFlags - These are flags set on operands, but should be considered
34  /// private, all access should go through the MCOperandInfo accessors.
35  /// See the accessors for a description of what these are.
36  enum OperandFlags {
37    LookupPtrRegClass = 0,
38    Predicate,
39    OptionalDef
40  };
41
42  /// Operand Type - Operands are tagged with one of the values of this enum.
43  enum OperandType {
44    OPERAND_UNKNOWN,
45    OPERAND_IMMEDIATE,
46    OPERAND_REGISTER,
47    OPERAND_MEMORY,
48    OPERAND_PCREL
49  };
50}
51
52/// MCOperandInfo - This holds information about one operand of a machine
53/// instruction, indicating the register class for register operands, etc.
54///
55class MCOperandInfo {
56public:
57  /// RegClass - This specifies the register class enumeration of the operand
58  /// if the operand is a register.  If isLookupPtrRegClass is set, then this is
59  /// an index that is passed to TargetRegisterInfo::getPointerRegClass(x) to
60  /// get a dynamic register class.
61  short RegClass;
62
63  /// Flags - These are flags from the MCOI::OperandFlags enum.
64  unsigned short Flags;
65
66  /// Lower 16 bits are used to specify which constraints are set. The higher 16
67  /// bits are used to specify the value of constraints (4 bits each).
68  unsigned Constraints;
69
70  /// OperandType - Information about the type of the operand.
71  MCOI::OperandType OperandType;
72  /// Currently no other information.
73
74  /// isLookupPtrRegClass - Set if this operand is a pointer value and it
75  /// requires a callback to look up its register class.
76  bool isLookupPtrRegClass() const {return Flags&(1 <<MCOI::LookupPtrRegClass);}
77
78  /// isPredicate - Set if this is one of the operands that made up of
79  /// the predicate operand that controls an isPredicable() instruction.
80  bool isPredicate() const { return Flags & (1 << MCOI::Predicate); }
81
82  /// isOptionalDef - Set if this operand is a optional def.
83  ///
84  bool isOptionalDef() const { return Flags & (1 << MCOI::OptionalDef); }
85};
86
87
88//===----------------------------------------------------------------------===//
89// Machine Instruction Flags and Description
90//===----------------------------------------------------------------------===//
91
92/// MCInstrDesc flags - These should be considered private to the
93/// implementation of the MCInstrDesc class.  Clients should use the predicate
94/// methods on MCInstrDesc, not use these directly.  These all correspond to
95/// bitfields in the MCInstrDesc::Flags field.
96namespace MCID {
97  enum {
98    Variadic = 0,
99    HasOptionalDef,
100    Return,
101    Call,
102    Barrier,
103    Terminator,
104    Branch,
105    IndirectBranch,
106    Compare,
107    MoveImm,
108    Bitcast,
109    DelaySlot,
110    FoldableAsLoad,
111    MayLoad,
112    MayStore,
113    Predicable,
114    NotDuplicable,
115    UnmodeledSideEffects,
116    Commutable,
117    ConvertibleTo3Addr,
118    UsesCustomInserter,
119    HasPostISelHook,
120    Rematerializable,
121    CheapAsAMove,
122    ExtraSrcRegAllocReq,
123    ExtraDefRegAllocReq
124  };
125}
126
127/// MCInstrDesc - Describe properties that are true of each instruction in the
128/// target description file.  This captures information about side effects,
129/// register use and many other things.  There is one instance of this struct
130/// for each target instruction class, and the MachineInstr class points to
131/// this struct directly to describe itself.
132class MCInstrDesc {
133public:
134  unsigned short  Opcode;        // The opcode number
135  unsigned short  NumOperands;   // Num of args (may be more if variable_ops)
136  unsigned short  NumDefs;       // Num of args that are definitions
137  unsigned short  SchedClass;    // enum identifying instr sched class
138  unsigned short  Size;          // Number of bytes in encoding.
139  const char *    Name;          // Name of the instruction record in td file
140  unsigned        Flags;         // Flags identifying machine instr class
141  uint64_t        TSFlags;       // Target Specific Flag values
142  const unsigned *ImplicitUses;  // Registers implicitly read by this instr
143  const unsigned *ImplicitDefs;  // Registers implicitly defined by this instr
144  const MCOperandInfo *OpInfo;   // 'NumOperands' entries about operands
145
146  /// getOperandConstraint - Returns the value of the specific constraint if
147  /// it is set. Returns -1 if it is not set.
148  int getOperandConstraint(unsigned OpNum,
149                           MCOI::OperandConstraint Constraint) const {
150    if (OpNum < NumOperands &&
151        (OpInfo[OpNum].Constraints & (1 << Constraint))) {
152      unsigned Pos = 16 + Constraint * 4;
153      return (int)(OpInfo[OpNum].Constraints >> Pos) & 0xf;
154    }
155    return -1;
156  }
157
158  /// getOpcode - Return the opcode number for this descriptor.
159  unsigned getOpcode() const {
160    return Opcode;
161  }
162
163  /// getName - Return the name of the record in the .td file for this
164  /// instruction, for example "ADD8ri".
165  const char *getName() const {
166    return Name;
167  }
168
169  /// getNumOperands - Return the number of declared MachineOperands for this
170  /// MachineInstruction.  Note that variadic (isVariadic() returns true)
171  /// instructions may have additional operands at the end of the list, and note
172  /// that the machine instruction may include implicit register def/uses as
173  /// well.
174  unsigned getNumOperands() const {
175    return NumOperands;
176  }
177
178  /// getNumDefs - Return the number of MachineOperands that are register
179  /// definitions.  Register definitions always occur at the start of the
180  /// machine operand list.  This is the number of "outs" in the .td file,
181  /// and does not include implicit defs.
182  unsigned getNumDefs() const {
183    return NumDefs;
184  }
185
186  /// isVariadic - Return true if this instruction can have a variable number of
187  /// operands.  In this case, the variable operands will be after the normal
188  /// operands but before the implicit definitions and uses (if any are
189  /// present).
190  bool isVariadic() const {
191    return Flags & (1 << MCID::Variadic);
192  }
193
194  /// hasOptionalDef - Set if this instruction has an optional definition, e.g.
195  /// ARM instructions which can set condition code if 's' bit is set.
196  bool hasOptionalDef() const {
197    return Flags & (1 << MCID::HasOptionalDef);
198  }
199
200  /// getImplicitUses - Return a list of registers that are potentially
201  /// read by any instance of this machine instruction.  For example, on X86,
202  /// the "adc" instruction adds two register operands and adds the carry bit in
203  /// from the flags register.  In this case, the instruction is marked as
204  /// implicitly reading the flags.  Likewise, the variable shift instruction on
205  /// X86 is marked as implicitly reading the 'CL' register, which it always
206  /// does.
207  ///
208  /// This method returns null if the instruction has no implicit uses.
209  const unsigned *getImplicitUses() const {
210    return ImplicitUses;
211  }
212
213  /// getNumImplicitUses - Return the number of implicit uses this instruction
214  /// has.
215  unsigned getNumImplicitUses() const {
216    if (ImplicitUses == 0) return 0;
217    unsigned i = 0;
218    for (; ImplicitUses[i]; ++i) /*empty*/;
219    return i;
220  }
221
222  /// getImplicitDefs - Return a list of registers that are potentially
223  /// written by any instance of this machine instruction.  For example, on X86,
224  /// many instructions implicitly set the flags register.  In this case, they
225  /// are marked as setting the FLAGS.  Likewise, many instructions always
226  /// deposit their result in a physical register.  For example, the X86 divide
227  /// instruction always deposits the quotient and remainder in the EAX/EDX
228  /// registers.  For that instruction, this will return a list containing the
229  /// EAX/EDX/EFLAGS registers.
230  ///
231  /// This method returns null if the instruction has no implicit defs.
232  const unsigned *getImplicitDefs() const {
233    return ImplicitDefs;
234  }
235
236  /// getNumImplicitDefs - Return the number of implicit defs this instruction
237  /// has.
238  unsigned getNumImplicitDefs() const {
239    if (ImplicitDefs == 0) return 0;
240    unsigned i = 0;
241    for (; ImplicitDefs[i]; ++i) /*empty*/;
242    return i;
243  }
244
245  /// hasImplicitUseOfPhysReg - Return true if this instruction implicitly
246  /// uses the specified physical register.
247  bool hasImplicitUseOfPhysReg(unsigned Reg) const {
248    if (const unsigned *ImpUses = ImplicitUses)
249      for (; *ImpUses; ++ImpUses)
250        if (*ImpUses == Reg) return true;
251    return false;
252  }
253
254  /// hasImplicitDefOfPhysReg - Return true if this instruction implicitly
255  /// defines the specified physical register.
256  bool hasImplicitDefOfPhysReg(unsigned Reg) const {
257    if (const unsigned *ImpDefs = ImplicitDefs)
258      for (; *ImpDefs; ++ImpDefs)
259        if (*ImpDefs == Reg) return true;
260    return false;
261  }
262
263  /// getSchedClass - Return the scheduling class for this instruction.  The
264  /// scheduling class is an index into the InstrItineraryData table.  This
265  /// returns zero if there is no known scheduling information for the
266  /// instruction.
267  ///
268  unsigned getSchedClass() const {
269    return SchedClass;
270  }
271
272  /// getSize - Return the number of bytes in the encoding of this instruction,
273  /// or zero if the encoding size cannot be known from the opcode.
274  unsigned getSize() const {
275    return Size;
276  }
277
278  bool isReturn() const {
279    return Flags & (1 << MCID::Return);
280  }
281
282  bool isCall() const {
283    return Flags & (1 << MCID::Call);
284  }
285
286  /// isBarrier - Returns true if the specified instruction stops control flow
287  /// from executing the instruction immediately following it.  Examples include
288  /// unconditional branches and return instructions.
289  bool isBarrier() const {
290    return Flags & (1 << MCID::Barrier);
291  }
292
293  /// findFirstPredOperandIdx() - Find the index of the first operand in the
294  /// operand list that is used to represent the predicate. It returns -1 if
295  /// none is found.
296  int findFirstPredOperandIdx() const {
297    if (isPredicable()) {
298      for (unsigned i = 0, e = getNumOperands(); i != e; ++i)
299        if (OpInfo[i].isPredicate())
300          return i;
301    }
302    return -1;
303  }
304
305  /// isTerminator - Returns true if this instruction part of the terminator for
306  /// a basic block.  Typically this is things like return and branch
307  /// instructions.
308  ///
309  /// Various passes use this to insert code into the bottom of a basic block,
310  /// but before control flow occurs.
311  bool isTerminator() const {
312    return Flags & (1 << MCID::Terminator);
313  }
314
315  /// isBranch - Returns true if this is a conditional, unconditional, or
316  /// indirect branch.  Predicates below can be used to discriminate between
317  /// these cases, and the TargetInstrInfo::AnalyzeBranch method can be used to
318  /// get more information.
319  bool isBranch() const {
320    return Flags & (1 << MCID::Branch);
321  }
322
323  /// isIndirectBranch - Return true if this is an indirect branch, such as a
324  /// branch through a register.
325  bool isIndirectBranch() const {
326    return Flags & (1 << MCID::IndirectBranch);
327  }
328
329  /// isConditionalBranch - Return true if this is a branch which may fall
330  /// through to the next instruction or may transfer control flow to some other
331  /// block.  The TargetInstrInfo::AnalyzeBranch method can be used to get more
332  /// information about this branch.
333  bool isConditionalBranch() const {
334    return isBranch() & !isBarrier() & !isIndirectBranch();
335  }
336
337  /// isUnconditionalBranch - Return true if this is a branch which always
338  /// transfers control flow to some other block.  The
339  /// TargetInstrInfo::AnalyzeBranch method can be used to get more information
340  /// about this branch.
341  bool isUnconditionalBranch() const {
342    return isBranch() & isBarrier() & !isIndirectBranch();
343  }
344
345  // isPredicable - Return true if this instruction has a predicate operand that
346  // controls execution.  It may be set to 'always', or may be set to other
347  /// values.   There are various methods in TargetInstrInfo that can be used to
348  /// control and modify the predicate in this instruction.
349  bool isPredicable() const {
350    return Flags & (1 << MCID::Predicable);
351  }
352
353  /// isCompare - Return true if this instruction is a comparison.
354  bool isCompare() const {
355    return Flags & (1 << MCID::Compare);
356  }
357
358  /// isMoveImmediate - Return true if this instruction is a move immediate
359  /// (including conditional moves) instruction.
360  bool isMoveImmediate() const {
361    return Flags & (1 << MCID::MoveImm);
362  }
363
364  /// isBitcast - Return true if this instruction is a bitcast instruction.
365  ///
366  bool isBitcast() const {
367    return Flags & (1 << MCID::Bitcast);
368  }
369
370  /// isNotDuplicable - Return true if this instruction cannot be safely
371  /// duplicated.  For example, if the instruction has a unique labels attached
372  /// to it, duplicating it would cause multiple definition errors.
373  bool isNotDuplicable() const {
374    return Flags & (1 << MCID::NotDuplicable);
375  }
376
377  /// hasDelaySlot - Returns true if the specified instruction has a delay slot
378  /// which must be filled by the code generator.
379  bool hasDelaySlot() const {
380    return Flags & (1 << MCID::DelaySlot);
381  }
382
383  /// canFoldAsLoad - Return true for instructions that can be folded as
384  /// memory operands in other instructions. The most common use for this
385  /// is instructions that are simple loads from memory that don't modify
386  /// the loaded value in any way, but it can also be used for instructions
387  /// that can be expressed as constant-pool loads, such as V_SETALLONES
388  /// on x86, to allow them to be folded when it is beneficial.
389  /// This should only be set on instructions that return a value in their
390  /// only virtual register definition.
391  bool canFoldAsLoad() const {
392    return Flags & (1 << MCID::FoldableAsLoad);
393  }
394
395  //===--------------------------------------------------------------------===//
396  // Side Effect Analysis
397  //===--------------------------------------------------------------------===//
398
399  /// mayLoad - Return true if this instruction could possibly read memory.
400  /// Instructions with this flag set are not necessarily simple load
401  /// instructions, they may load a value and modify it, for example.
402  bool mayLoad() const {
403    return Flags & (1 << MCID::MayLoad);
404  }
405
406
407  /// mayStore - Return true if this instruction could possibly modify memory.
408  /// Instructions with this flag set are not necessarily simple store
409  /// instructions, they may store a modified value based on their operands, or
410  /// may not actually modify anything, for example.
411  bool mayStore() const {
412    return Flags & (1 << MCID::MayStore);
413  }
414
415  /// hasUnmodeledSideEffects - Return true if this instruction has side
416  /// effects that are not modeled by other flags.  This does not return true
417  /// for instructions whose effects are captured by:
418  ///
419  ///  1. Their operand list and implicit definition/use list.  Register use/def
420  ///     info is explicit for instructions.
421  ///  2. Memory accesses.  Use mayLoad/mayStore.
422  ///  3. Calling, branching, returning: use isCall/isReturn/isBranch.
423  ///
424  /// Examples of side effects would be modifying 'invisible' machine state like
425  /// a control register, flushing a cache, modifying a register invisible to
426  /// LLVM, etc.
427  ///
428  bool hasUnmodeledSideEffects() const {
429    return Flags & (1 << MCID::UnmodeledSideEffects);
430  }
431
432  //===--------------------------------------------------------------------===//
433  // Flags that indicate whether an instruction can be modified by a method.
434  //===--------------------------------------------------------------------===//
435
436  /// isCommutable - Return true if this may be a 2- or 3-address
437  /// instruction (of the form "X = op Y, Z, ..."), which produces the same
438  /// result if Y and Z are exchanged.  If this flag is set, then the
439  /// TargetInstrInfo::commuteInstruction method may be used to hack on the
440  /// instruction.
441  ///
442  /// Note that this flag may be set on instructions that are only commutable
443  /// sometimes.  In these cases, the call to commuteInstruction will fail.
444  /// Also note that some instructions require non-trivial modification to
445  /// commute them.
446  bool isCommutable() const {
447    return Flags & (1 << MCID::Commutable);
448  }
449
450  /// isConvertibleTo3Addr - Return true if this is a 2-address instruction
451  /// which can be changed into a 3-address instruction if needed.  Doing this
452  /// transformation can be profitable in the register allocator, because it
453  /// means that the instruction can use a 2-address form if possible, but
454  /// degrade into a less efficient form if the source and dest register cannot
455  /// be assigned to the same register.  For example, this allows the x86
456  /// backend to turn a "shl reg, 3" instruction into an LEA instruction, which
457  /// is the same speed as the shift but has bigger code size.
458  ///
459  /// If this returns true, then the target must implement the
460  /// TargetInstrInfo::convertToThreeAddress method for this instruction, which
461  /// is allowed to fail if the transformation isn't valid for this specific
462  /// instruction (e.g. shl reg, 4 on x86).
463  ///
464  bool isConvertibleTo3Addr() const {
465    return Flags & (1 << MCID::ConvertibleTo3Addr);
466  }
467
468  /// usesCustomInsertionHook - Return true if this instruction requires
469  /// custom insertion support when the DAG scheduler is inserting it into a
470  /// machine basic block.  If this is true for the instruction, it basically
471  /// means that it is a pseudo instruction used at SelectionDAG time that is
472  /// expanded out into magic code by the target when MachineInstrs are formed.
473  ///
474  /// If this is true, the TargetLoweringInfo::InsertAtEndOfBasicBlock method
475  /// is used to insert this into the MachineBasicBlock.
476  bool usesCustomInsertionHook() const {
477    return Flags & (1 << MCID::UsesCustomInserter);
478  }
479
480  /// isRematerializable - Returns true if this instruction is a candidate for
481  /// remat.  This flag is deprecated, please don't use it anymore.  If this
482  /// flag is set, the isReallyTriviallyReMaterializable() method is called to
483  /// verify the instruction is really rematable.
484  bool isRematerializable() const {
485    return Flags & (1 << MCID::Rematerializable);
486  }
487
488  /// isAsCheapAsAMove - Returns true if this instruction has the same cost (or
489  /// less) than a move instruction. This is useful during certain types of
490  /// optimizations (e.g., remat during two-address conversion or machine licm)
491  /// where we would like to remat or hoist the instruction, but not if it costs
492  /// more than moving the instruction into the appropriate register. Note, we
493  /// are not marking copies from and to the same register class with this flag.
494  bool isAsCheapAsAMove() const {
495    return Flags & (1 << MCID::CheapAsAMove);
496  }
497
498  /// hasExtraSrcRegAllocReq - Returns true if this instruction source operands
499  /// have special register allocation requirements that are not captured by the
500  /// operand register classes. e.g. ARM::STRD's two source registers must be an
501  /// even / odd pair, ARM::STM registers have to be in ascending order.
502  /// Post-register allocation passes should not attempt to change allocations
503  /// for sources of instructions with this flag.
504  bool hasExtraSrcRegAllocReq() const {
505    return Flags & (1 << MCID::ExtraSrcRegAllocReq);
506  }
507
508  /// hasExtraDefRegAllocReq - Returns true if this instruction def operands
509  /// have special register allocation requirements that are not captured by the
510  /// operand register classes. e.g. ARM::LDRD's two def registers must be an
511  /// even / odd pair, ARM::LDM registers have to be in ascending order.
512  /// Post-register allocation passes should not attempt to change allocations
513  /// for definitions of instructions with this flag.
514  bool hasExtraDefRegAllocReq() const {
515    return Flags & (1 << MCID::ExtraDefRegAllocReq);
516  }
517};
518
519} // end namespace llvm
520
521#endif
522