MCInstrDesc.h revision f8e1e3e729473b8b2b7ee6134b6417976af84d05
1//===-- llvm/Mc/McInstrDesc.h - Instruction Descriptors -*- C++ -*-===//
2//
3//                     The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10// This file defines the MCOperandInfo and MCInstrDesc classes, which
11// are used to describe target instructions and their operands.
12//
13//===----------------------------------------------------------------------===//
14
15#ifndef LLVM_MC_MCINSTRDESC_H
16#define LLVM_MC_MCINSTRDESC_H
17
18#include "llvm/Support/DataTypes.h"
19
20namespace llvm {
21
22//===----------------------------------------------------------------------===//
23// Machine Operand Flags and Description
24//===----------------------------------------------------------------------===//
25
26namespace MCOI {
27  // Operand constraints
28  enum OperandConstraint {
29    TIED_TO = 0,    // Must be allocated the same register as.
30    EARLY_CLOBBER   // Operand is an early clobber register operand
31  };
32
33  /// OperandFlags - These are flags set on operands, but should be considered
34  /// private, all access should go through the MCOperandInfo accessors.
35  /// See the accessors for a description of what these are.
36  enum OperandFlags {
37    LookupPtrRegClass = 0,
38    Predicate,
39    OptionalDef
40  };
41
42  /// Operand Type - Operands are tagged with one of the values of this enum.
43  enum OperandType {
44    OPERAND_UNKNOWN,
45    OPERAND_IMMEDIATE,
46    OPERAND_REGISTER,
47    OPERAND_MEMORY,
48    OPERAND_PCREL
49  };
50}
51
52/// MCOperandInfo - This holds information about one operand of a machine
53/// instruction, indicating the register class for register operands, etc.
54///
55class MCOperandInfo {
56public:
57  /// RegClass - This specifies the register class enumeration of the operand
58  /// if the operand is a register.  If isLookupPtrRegClass is set, then this is
59  /// an index that is passed to TargetRegisterInfo::getPointerRegClass(x) to
60  /// get a dynamic register class.
61  short RegClass;
62
63  /// Flags - These are flags from the MCOI::OperandFlags enum.
64  unsigned short Flags;
65
66  /// Lower 16 bits are used to specify which constraints are set. The higher 16
67  /// bits are used to specify the value of constraints (4 bits each).
68  unsigned Constraints;
69
70  /// OperandType - Information about the type of the operand.
71  MCOI::OperandType OperandType;
72  /// Currently no other information.
73
74  /// isLookupPtrRegClass - Set if this operand is a pointer value and it
75  /// requires a callback to look up its register class.
76  bool isLookupPtrRegClass() const {return Flags&(1 <<MCOI::LookupPtrRegClass);}
77
78  /// isPredicate - Set if this is one of the operands that made up of
79  /// the predicate operand that controls an isPredicable() instruction.
80  bool isPredicate() const { return Flags & (1 << MCOI::Predicate); }
81
82  /// isOptionalDef - Set if this operand is a optional def.
83  ///
84  bool isOptionalDef() const { return Flags & (1 << MCOI::OptionalDef); }
85};
86
87
88//===----------------------------------------------------------------------===//
89// Machine Instruction Flags and Description
90//===----------------------------------------------------------------------===//
91
92/// MCInstrDesc flags - These should be considered private to the
93/// implementation of the MCInstrDesc class.  Clients should use the predicate
94/// methods on MCInstrDesc, not use these directly.  These all correspond to
95/// bitfields in the MCInstrDesc::Flags field.
96namespace MCID {
97  enum {
98    Variadic = 0,
99    HasOptionalDef,
100    Return,
101    Call,
102    Barrier,
103    Terminator,
104    Branch,
105    IndirectBranch,
106    Compare,
107    MoveImm,
108    Bitcast,
109    DelaySlot,
110    FoldableAsLoad,
111    MayLoad,
112    MayStore,
113    Predicable,
114    NotDuplicable,
115    UnmodeledSideEffects,
116    Commutable,
117    ConvertibleTo3Addr,
118    UsesCustomInserter,
119    Rematerializable,
120    CheapAsAMove,
121    ExtraSrcRegAllocReq,
122    ExtraDefRegAllocReq
123  };
124}
125
126/// MCInstrDesc - Describe properties that are true of each instruction in the
127/// target description file.  This captures information about side effects,
128/// register use and many other things.  There is one instance of this struct
129/// for each target instruction class, and the MachineInstr class points to
130/// this struct directly to describe itself.
131class MCInstrDesc {
132public:
133  unsigned short  Opcode;        // The opcode number
134  unsigned short  NumOperands;   // Num of args (may be more if variable_ops)
135  unsigned short  NumDefs;       // Num of args that are definitions
136  unsigned short  SchedClass;    // enum identifying instr sched class
137  unsigned short  Size;          // Number of bytes in encoding.
138  const char *    Name;          // Name of the instruction record in td file
139  unsigned        Flags;         // Flags identifying machine instr class
140  uint64_t        TSFlags;       // Target Specific Flag values
141  const unsigned *ImplicitUses;  // Registers implicitly read by this instr
142  const unsigned *ImplicitDefs;  // Registers implicitly defined by this instr
143  const MCOperandInfo *OpInfo;   // 'NumOperands' entries about operands
144
145  /// getOperandConstraint - Returns the value of the specific constraint if
146  /// it is set. Returns -1 if it is not set.
147  int getOperandConstraint(unsigned OpNum,
148                           MCOI::OperandConstraint Constraint) const {
149    if (OpNum < NumOperands &&
150        (OpInfo[OpNum].Constraints & (1 << Constraint))) {
151      unsigned Pos = 16 + Constraint * 4;
152      return (int)(OpInfo[OpNum].Constraints >> Pos) & 0xf;
153    }
154    return -1;
155  }
156
157  /// getOpcode - Return the opcode number for this descriptor.
158  unsigned getOpcode() const {
159    return Opcode;
160  }
161
162  /// getName - Return the name of the record in the .td file for this
163  /// instruction, for example "ADD8ri".
164  const char *getName() const {
165    return Name;
166  }
167
168  /// getNumOperands - Return the number of declared MachineOperands for this
169  /// MachineInstruction.  Note that variadic (isVariadic() returns true)
170  /// instructions may have additional operands at the end of the list, and note
171  /// that the machine instruction may include implicit register def/uses as
172  /// well.
173  unsigned getNumOperands() const {
174    return NumOperands;
175  }
176
177  /// getNumDefs - Return the number of MachineOperands that are register
178  /// definitions.  Register definitions always occur at the start of the
179  /// machine operand list.  This is the number of "outs" in the .td file,
180  /// and does not include implicit defs.
181  unsigned getNumDefs() const {
182    return NumDefs;
183  }
184
185  /// isVariadic - Return true if this instruction can have a variable number of
186  /// operands.  In this case, the variable operands will be after the normal
187  /// operands but before the implicit definitions and uses (if any are
188  /// present).
189  bool isVariadic() const {
190    return Flags & (1 << MCID::Variadic);
191  }
192
193  /// hasOptionalDef - Set if this instruction has an optional definition, e.g.
194  /// ARM instructions which can set condition code if 's' bit is set.
195  bool hasOptionalDef() const {
196    return Flags & (1 << MCID::HasOptionalDef);
197  }
198
199  /// getImplicitUses - Return a list of registers that are potentially
200  /// read by any instance of this machine instruction.  For example, on X86,
201  /// the "adc" instruction adds two register operands and adds the carry bit in
202  /// from the flags register.  In this case, the instruction is marked as
203  /// implicitly reading the flags.  Likewise, the variable shift instruction on
204  /// X86 is marked as implicitly reading the 'CL' register, which it always
205  /// does.
206  ///
207  /// This method returns null if the instruction has no implicit uses.
208  const unsigned *getImplicitUses() const {
209    return ImplicitUses;
210  }
211
212  /// getNumImplicitUses - Return the number of implicit uses this instruction
213  /// has.
214  unsigned getNumImplicitUses() const {
215    if (ImplicitUses == 0) return 0;
216    unsigned i = 0;
217    for (; ImplicitUses[i]; ++i) /*empty*/;
218    return i;
219  }
220
221  /// getImplicitDefs - Return a list of registers that are potentially
222  /// written by any instance of this machine instruction.  For example, on X86,
223  /// many instructions implicitly set the flags register.  In this case, they
224  /// are marked as setting the FLAGS.  Likewise, many instructions always
225  /// deposit their result in a physical register.  For example, the X86 divide
226  /// instruction always deposits the quotient and remainder in the EAX/EDX
227  /// registers.  For that instruction, this will return a list containing the
228  /// EAX/EDX/EFLAGS registers.
229  ///
230  /// This method returns null if the instruction has no implicit defs.
231  const unsigned *getImplicitDefs() const {
232    return ImplicitDefs;
233  }
234
235  /// getNumImplicitDefs - Return the number of implicit defs this instruction
236  /// has.
237  unsigned getNumImplicitDefs() const {
238    if (ImplicitDefs == 0) return 0;
239    unsigned i = 0;
240    for (; ImplicitDefs[i]; ++i) /*empty*/;
241    return i;
242  }
243
244  /// hasImplicitUseOfPhysReg - Return true if this instruction implicitly
245  /// uses the specified physical register.
246  bool hasImplicitUseOfPhysReg(unsigned Reg) const {
247    if (const unsigned *ImpUses = ImplicitUses)
248      for (; *ImpUses; ++ImpUses)
249        if (*ImpUses == Reg) return true;
250    return false;
251  }
252
253  /// hasImplicitDefOfPhysReg - Return true if this instruction implicitly
254  /// defines the specified physical register.
255  bool hasImplicitDefOfPhysReg(unsigned Reg) const {
256    if (const unsigned *ImpDefs = ImplicitDefs)
257      for (; *ImpDefs; ++ImpDefs)
258        if (*ImpDefs == Reg) return true;
259    return false;
260  }
261
262  /// getSchedClass - Return the scheduling class for this instruction.  The
263  /// scheduling class is an index into the InstrItineraryData table.  This
264  /// returns zero if there is no known scheduling information for the
265  /// instruction.
266  ///
267  unsigned getSchedClass() const {
268    return SchedClass;
269  }
270
271  /// getSize - Return the number of bytes in the encoding of this instruction,
272  /// or zero if the encoding size cannot be known from the opcode.
273  unsigned getSize() const {
274    return Size;
275  }
276
277  bool isReturn() const {
278    return Flags & (1 << MCID::Return);
279  }
280
281  bool isCall() const {
282    return Flags & (1 << MCID::Call);
283  }
284
285  /// isBarrier - Returns true if the specified instruction stops control flow
286  /// from executing the instruction immediately following it.  Examples include
287  /// unconditional branches and return instructions.
288  bool isBarrier() const {
289    return Flags & (1 << MCID::Barrier);
290  }
291
292  /// findFirstPredOperandIdx() - Find the index of the first operand in the
293  /// operand list that is used to represent the predicate. It returns -1 if
294  /// none is found.
295  int findFirstPredOperandIdx() const {
296    if (isPredicable()) {
297      for (unsigned i = 0, e = getNumOperands(); i != e; ++i)
298        if (OpInfo[i].isPredicate())
299          return i;
300    }
301    return -1;
302  }
303
304  /// isTerminator - Returns true if this instruction part of the terminator for
305  /// a basic block.  Typically this is things like return and branch
306  /// instructions.
307  ///
308  /// Various passes use this to insert code into the bottom of a basic block,
309  /// but before control flow occurs.
310  bool isTerminator() const {
311    return Flags & (1 << MCID::Terminator);
312  }
313
314  /// isBranch - Returns true if this is a conditional, unconditional, or
315  /// indirect branch.  Predicates below can be used to discriminate between
316  /// these cases, and the TargetInstrInfo::AnalyzeBranch method can be used to
317  /// get more information.
318  bool isBranch() const {
319    return Flags & (1 << MCID::Branch);
320  }
321
322  /// isIndirectBranch - Return true if this is an indirect branch, such as a
323  /// branch through a register.
324  bool isIndirectBranch() const {
325    return Flags & (1 << MCID::IndirectBranch);
326  }
327
328  /// isConditionalBranch - Return true if this is a branch which may fall
329  /// through to the next instruction or may transfer control flow to some other
330  /// block.  The TargetInstrInfo::AnalyzeBranch method can be used to get more
331  /// information about this branch.
332  bool isConditionalBranch() const {
333    return isBranch() & !isBarrier() & !isIndirectBranch();
334  }
335
336  /// isUnconditionalBranch - Return true if this is a branch which always
337  /// transfers control flow to some other block.  The
338  /// TargetInstrInfo::AnalyzeBranch method can be used to get more information
339  /// about this branch.
340  bool isUnconditionalBranch() const {
341    return isBranch() & isBarrier() & !isIndirectBranch();
342  }
343
344  // isPredicable - Return true if this instruction has a predicate operand that
345  // controls execution.  It may be set to 'always', or may be set to other
346  /// values.   There are various methods in TargetInstrInfo that can be used to
347  /// control and modify the predicate in this instruction.
348  bool isPredicable() const {
349    return Flags & (1 << MCID::Predicable);
350  }
351
352  /// isCompare - Return true if this instruction is a comparison.
353  bool isCompare() const {
354    return Flags & (1 << MCID::Compare);
355  }
356
357  /// isMoveImmediate - Return true if this instruction is a move immediate
358  /// (including conditional moves) instruction.
359  bool isMoveImmediate() const {
360    return Flags & (1 << MCID::MoveImm);
361  }
362
363  /// isBitcast - Return true if this instruction is a bitcast instruction.
364  ///
365  bool isBitcast() const {
366    return Flags & (1 << MCID::Bitcast);
367  }
368
369  /// isNotDuplicable - Return true if this instruction cannot be safely
370  /// duplicated.  For example, if the instruction has a unique labels attached
371  /// to it, duplicating it would cause multiple definition errors.
372  bool isNotDuplicable() const {
373    return Flags & (1 << MCID::NotDuplicable);
374  }
375
376  /// hasDelaySlot - Returns true if the specified instruction has a delay slot
377  /// which must be filled by the code generator.
378  bool hasDelaySlot() const {
379    return Flags & (1 << MCID::DelaySlot);
380  }
381
382  /// canFoldAsLoad - Return true for instructions that can be folded as
383  /// memory operands in other instructions. The most common use for this
384  /// is instructions that are simple loads from memory that don't modify
385  /// the loaded value in any way, but it can also be used for instructions
386  /// that can be expressed as constant-pool loads, such as V_SETALLONES
387  /// on x86, to allow them to be folded when it is beneficial.
388  /// This should only be set on instructions that return a value in their
389  /// only virtual register definition.
390  bool canFoldAsLoad() const {
391    return Flags & (1 << MCID::FoldableAsLoad);
392  }
393
394  //===--------------------------------------------------------------------===//
395  // Side Effect Analysis
396  //===--------------------------------------------------------------------===//
397
398  /// mayLoad - Return true if this instruction could possibly read memory.
399  /// Instructions with this flag set are not necessarily simple load
400  /// instructions, they may load a value and modify it, for example.
401  bool mayLoad() const {
402    return Flags & (1 << MCID::MayLoad);
403  }
404
405
406  /// mayStore - Return true if this instruction could possibly modify memory.
407  /// Instructions with this flag set are not necessarily simple store
408  /// instructions, they may store a modified value based on their operands, or
409  /// may not actually modify anything, for example.
410  bool mayStore() const {
411    return Flags & (1 << MCID::MayStore);
412  }
413
414  /// hasUnmodeledSideEffects - Return true if this instruction has side
415  /// effects that are not modeled by other flags.  This does not return true
416  /// for instructions whose effects are captured by:
417  ///
418  ///  1. Their operand list and implicit definition/use list.  Register use/def
419  ///     info is explicit for instructions.
420  ///  2. Memory accesses.  Use mayLoad/mayStore.
421  ///  3. Calling, branching, returning: use isCall/isReturn/isBranch.
422  ///
423  /// Examples of side effects would be modifying 'invisible' machine state like
424  /// a control register, flushing a cache, modifying a register invisible to
425  /// LLVM, etc.
426  ///
427  bool hasUnmodeledSideEffects() const {
428    return Flags & (1 << MCID::UnmodeledSideEffects);
429  }
430
431  //===--------------------------------------------------------------------===//
432  // Flags that indicate whether an instruction can be modified by a method.
433  //===--------------------------------------------------------------------===//
434
435  /// isCommutable - Return true if this may be a 2- or 3-address
436  /// instruction (of the form "X = op Y, Z, ..."), which produces the same
437  /// result if Y and Z are exchanged.  If this flag is set, then the
438  /// TargetInstrInfo::commuteInstruction method may be used to hack on the
439  /// instruction.
440  ///
441  /// Note that this flag may be set on instructions that are only commutable
442  /// sometimes.  In these cases, the call to commuteInstruction will fail.
443  /// Also note that some instructions require non-trivial modification to
444  /// commute them.
445  bool isCommutable() const {
446    return Flags & (1 << MCID::Commutable);
447  }
448
449  /// isConvertibleTo3Addr - Return true if this is a 2-address instruction
450  /// which can be changed into a 3-address instruction if needed.  Doing this
451  /// transformation can be profitable in the register allocator, because it
452  /// means that the instruction can use a 2-address form if possible, but
453  /// degrade into a less efficient form if the source and dest register cannot
454  /// be assigned to the same register.  For example, this allows the x86
455  /// backend to turn a "shl reg, 3" instruction into an LEA instruction, which
456  /// is the same speed as the shift but has bigger code size.
457  ///
458  /// If this returns true, then the target must implement the
459  /// TargetInstrInfo::convertToThreeAddress method for this instruction, which
460  /// is allowed to fail if the transformation isn't valid for this specific
461  /// instruction (e.g. shl reg, 4 on x86).
462  ///
463  bool isConvertibleTo3Addr() const {
464    return Flags & (1 << MCID::ConvertibleTo3Addr);
465  }
466
467  /// usesCustomInsertionHook - Return true if this instruction requires
468  /// custom insertion support when the DAG scheduler is inserting it into a
469  /// machine basic block.  If this is true for the instruction, it basically
470  /// means that it is a pseudo instruction used at SelectionDAG time that is
471  /// expanded out into magic code by the target when MachineInstrs are formed.
472  ///
473  /// If this is true, the TargetLoweringInfo::InsertAtEndOfBasicBlock method
474  /// is used to insert this into the MachineBasicBlock.
475  bool usesCustomInsertionHook() const {
476    return Flags & (1 << MCID::UsesCustomInserter);
477  }
478
479  /// isRematerializable - Returns true if this instruction is a candidate for
480  /// remat.  This flag is deprecated, please don't use it anymore.  If this
481  /// flag is set, the isReallyTriviallyReMaterializable() method is called to
482  /// verify the instruction is really rematable.
483  bool isRematerializable() const {
484    return Flags & (1 << MCID::Rematerializable);
485  }
486
487  /// isAsCheapAsAMove - Returns true if this instruction has the same cost (or
488  /// less) than a move instruction. This is useful during certain types of
489  /// optimizations (e.g., remat during two-address conversion or machine licm)
490  /// where we would like to remat or hoist the instruction, but not if it costs
491  /// more than moving the instruction into the appropriate register. Note, we
492  /// are not marking copies from and to the same register class with this flag.
493  bool isAsCheapAsAMove() const {
494    return Flags & (1 << MCID::CheapAsAMove);
495  }
496
497  /// hasExtraSrcRegAllocReq - Returns true if this instruction source operands
498  /// have special register allocation requirements that are not captured by the
499  /// operand register classes. e.g. ARM::STRD's two source registers must be an
500  /// even / odd pair, ARM::STM registers have to be in ascending order.
501  /// Post-register allocation passes should not attempt to change allocations
502  /// for sources of instructions with this flag.
503  bool hasExtraSrcRegAllocReq() const {
504    return Flags & (1 << MCID::ExtraSrcRegAllocReq);
505  }
506
507  /// hasExtraDefRegAllocReq - Returns true if this instruction def operands
508  /// have special register allocation requirements that are not captured by the
509  /// operand register classes. e.g. ARM::LDRD's two def registers must be an
510  /// even / odd pair, ARM::LDM registers have to be in ascending order.
511  /// Post-register allocation passes should not attempt to change allocations
512  /// for definitions of instructions with this flag.
513  bool hasExtraDefRegAllocReq() const {
514    return Flags & (1 << MCID::ExtraDefRegAllocReq);
515  }
516};
517
518} // end namespace llvm
519
520#endif
521