MCInstrDesc.h revision fbf3b4a07690751f72302757058ab0298dfb832e
1//===-- llvm/MC/MCInstrDesc.h - Instruction Descriptors -*- C++ -*-===//
2//
3//                     The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10// This file defines the MCOperandInfo and MCInstrDesc classes, which
11// are used to describe target instructions and their operands.
12//
13//===----------------------------------------------------------------------===//
14
15#ifndef LLVM_MC_MCINSTRDESC_H
16#define LLVM_MC_MCINSTRDESC_H
17
18#include "llvm/Support/DataTypes.h"
19#include "llvm/MC/MCRegisterInfo.h"
20#include "llvm/MC/MCInst.h"
21
22namespace llvm {
23
24//===----------------------------------------------------------------------===//
25// Machine Operand Flags and Description
26//===----------------------------------------------------------------------===//
27
28namespace MCOI {
29  // Operand constraints
30  enum OperandConstraint {
31    TIED_TO = 0,    // Must be allocated the same register as.
32    EARLY_CLOBBER   // Operand is an early clobber register operand
33  };
34
35  /// OperandFlags - These are flags set on operands, but should be considered
36  /// private, all access should go through the MCOperandInfo accessors.
37  /// See the accessors for a description of what these are.
38  enum OperandFlags {
39    LookupPtrRegClass = 0,
40    Predicate,
41    OptionalDef
42  };
43
44  /// Operand Type - Operands are tagged with one of the values of this enum.
45  enum OperandType {
46    OPERAND_UNKNOWN,
47    OPERAND_IMMEDIATE,
48    OPERAND_REGISTER,
49    OPERAND_MEMORY,
50    OPERAND_PCREL
51  };
52}
53
54/// MCOperandInfo - This holds information about one operand of a machine
55/// instruction, indicating the register class for register operands, etc.
56///
57class MCOperandInfo {
58public:
59  /// RegClass - This specifies the register class enumeration of the operand
60  /// if the operand is a register.  If isLookupPtrRegClass is set, then this is
61  /// an index that is passed to TargetRegisterInfo::getPointerRegClass(x) to
62  /// get a dynamic register class.
63  int16_t RegClass;
64
65  /// Flags - These are flags from the MCOI::OperandFlags enum.
66  uint8_t Flags;
67
68  /// OperandType - Information about the type of the operand.
69  uint8_t OperandType;
70
71  /// Lower 16 bits are used to specify which constraints are set. The higher 16
72  /// bits are used to specify the value of constraints (4 bits each).
73  uint32_t Constraints;
74  /// Currently no other information.
75
76  /// isLookupPtrRegClass - Set if this operand is a pointer value and it
77  /// requires a callback to look up its register class.
78  bool isLookupPtrRegClass() const {return Flags&(1 <<MCOI::LookupPtrRegClass);}
79
80  /// isPredicate - Set if this is one of the operands that made up of
81  /// the predicate operand that controls an isPredicable() instruction.
82  bool isPredicate() const { return Flags & (1 << MCOI::Predicate); }
83
84  /// isOptionalDef - Set if this operand is a optional def.
85  ///
86  bool isOptionalDef() const { return Flags & (1 << MCOI::OptionalDef); }
87};
88
89
90//===----------------------------------------------------------------------===//
91// Machine Instruction Flags and Description
92//===----------------------------------------------------------------------===//
93
94/// MCInstrDesc flags - These should be considered private to the
95/// implementation of the MCInstrDesc class.  Clients should use the predicate
96/// methods on MCInstrDesc, not use these directly.  These all correspond to
97/// bitfields in the MCInstrDesc::Flags field.
98namespace MCID {
99  enum {
100    Variadic = 0,
101    HasOptionalDef,
102    Pseudo,
103    Return,
104    Call,
105    Barrier,
106    Terminator,
107    Branch,
108    IndirectBranch,
109    Compare,
110    MoveImm,
111    Bitcast,
112    Select,
113    DelaySlot,
114    FoldableAsLoad,
115    MayLoad,
116    MayStore,
117    Predicable,
118    NotDuplicable,
119    UnmodeledSideEffects,
120    Commutable,
121    ConvertibleTo3Addr,
122    UsesCustomInserter,
123    HasPostISelHook,
124    Rematerializable,
125    CheapAsAMove,
126    ExtraSrcRegAllocReq,
127    ExtraDefRegAllocReq
128  };
129}
130
131/// MCInstrDesc - Describe properties that are true of each instruction in the
132/// target description file.  This captures information about side effects,
133/// register use and many other things.  There is one instance of this struct
134/// for each target instruction class, and the MachineInstr class points to
135/// this struct directly to describe itself.
136class MCInstrDesc {
137public:
138  unsigned short  Opcode;        // The opcode number
139  unsigned short  NumOperands;   // Num of args (may be more if variable_ops)
140  unsigned short  NumDefs;       // Num of args that are definitions
141  unsigned short  SchedClass;    // enum identifying instr sched class
142  unsigned short  Size;          // Number of bytes in encoding.
143  unsigned        Flags;         // Flags identifying machine instr class
144  uint64_t        TSFlags;       // Target Specific Flag values
145  const uint16_t *ImplicitUses;  // Registers implicitly read by this instr
146  const uint16_t *ImplicitDefs;  // Registers implicitly defined by this instr
147  const MCOperandInfo *OpInfo;   // 'NumOperands' entries about operands
148
149  /// getOperandConstraint - Returns the value of the specific constraint if
150  /// it is set. Returns -1 if it is not set.
151  int getOperandConstraint(unsigned OpNum,
152                           MCOI::OperandConstraint Constraint) const {
153    if (OpNum < NumOperands &&
154        (OpInfo[OpNum].Constraints & (1 << Constraint))) {
155      unsigned Pos = 16 + Constraint * 4;
156      return (int)(OpInfo[OpNum].Constraints >> Pos) & 0xf;
157    }
158    return -1;
159  }
160
161  /// getOpcode - Return the opcode number for this descriptor.
162  unsigned getOpcode() const {
163    return Opcode;
164  }
165
166  /// getNumOperands - Return the number of declared MachineOperands for this
167  /// MachineInstruction.  Note that variadic (isVariadic() returns true)
168  /// instructions may have additional operands at the end of the list, and note
169  /// that the machine instruction may include implicit register def/uses as
170  /// well.
171  unsigned getNumOperands() const {
172    return NumOperands;
173  }
174
175  /// getNumDefs - Return the number of MachineOperands that are register
176  /// definitions.  Register definitions always occur at the start of the
177  /// machine operand list.  This is the number of "outs" in the .td file,
178  /// and does not include implicit defs.
179  unsigned getNumDefs() const {
180    return NumDefs;
181  }
182
183  /// getFlags - Return flags of this instruction.
184  ///
185  unsigned getFlags() const { return Flags; }
186
187  /// isVariadic - Return true if this instruction can have a variable number of
188  /// operands.  In this case, the variable operands will be after the normal
189  /// operands but before the implicit definitions and uses (if any are
190  /// present).
191  bool isVariadic() const {
192    return Flags & (1 << MCID::Variadic);
193  }
194
195  /// hasOptionalDef - Set if this instruction has an optional definition, e.g.
196  /// ARM instructions which can set condition code if 's' bit is set.
197  bool hasOptionalDef() const {
198    return Flags & (1 << MCID::HasOptionalDef);
199  }
200
201  /// isPseudo - Return true if this is a pseudo instruction that doesn't
202  /// correspond to a real machine instruction.
203  ///
204  bool isPseudo() const {
205    return Flags & (1 << MCID::Pseudo);
206  }
207
208  bool isReturn() const {
209    return Flags & (1 << MCID::Return);
210  }
211
212  bool isCall() const {
213    return Flags & (1 << MCID::Call);
214  }
215
216  /// isBarrier - Returns true if the specified instruction stops control flow
217  /// from executing the instruction immediately following it.  Examples include
218  /// unconditional branches and return instructions.
219  bool isBarrier() const {
220    return Flags & (1 << MCID::Barrier);
221  }
222
223  /// isTerminator - Returns true if this instruction part of the terminator for
224  /// a basic block.  Typically this is things like return and branch
225  /// instructions.
226  ///
227  /// Various passes use this to insert code into the bottom of a basic block,
228  /// but before control flow occurs.
229  bool isTerminator() const {
230    return Flags & (1 << MCID::Terminator);
231  }
232
233  /// isBranch - Returns true if this is a conditional, unconditional, or
234  /// indirect branch.  Predicates below can be used to discriminate between
235  /// these cases, and the TargetInstrInfo::AnalyzeBranch method can be used to
236  /// get more information.
237  bool isBranch() const {
238    return Flags & (1 << MCID::Branch);
239  }
240
241  /// isIndirectBranch - Return true if this is an indirect branch, such as a
242  /// branch through a register.
243  bool isIndirectBranch() const {
244    return Flags & (1 << MCID::IndirectBranch);
245  }
246
247  /// isConditionalBranch - Return true if this is a branch which may fall
248  /// through to the next instruction or may transfer control flow to some other
249  /// block.  The TargetInstrInfo::AnalyzeBranch method can be used to get more
250  /// information about this branch.
251  bool isConditionalBranch() const {
252    return isBranch() & !isBarrier() & !isIndirectBranch();
253  }
254
255  /// isUnconditionalBranch - Return true if this is a branch which always
256  /// transfers control flow to some other block.  The
257  /// TargetInstrInfo::AnalyzeBranch method can be used to get more information
258  /// about this branch.
259  bool isUnconditionalBranch() const {
260    return isBranch() & isBarrier() & !isIndirectBranch();
261  }
262
263  /// Return true if this is a branch or an instruction which directly
264  /// writes to the program counter. Considered 'may' affect rather than
265  /// 'does' affect as things like predication are not taken into account.
266  bool mayAffectControlFlow(const MCInst &MI, const MCRegisterInfo &RI) const {
267    if (isBranch() || isCall() || isReturn() || isIndirectBranch())
268      return true;
269    unsigned PC = RI.getProgramCounter();
270    if (PC == 0) return false;
271    return hasDefOfPhysReg(MI, PC, RI);
272  }
273
274  /// isPredicable - Return true if this instruction has a predicate operand
275  /// that controls execution. It may be set to 'always', or may be set to other
276  /// values. There are various methods in TargetInstrInfo that can be used to
277  /// control and modify the predicate in this instruction.
278  bool isPredicable() const {
279    return Flags & (1 << MCID::Predicable);
280  }
281
282  /// isCompare - Return true if this instruction is a comparison.
283  bool isCompare() const {
284    return Flags & (1 << MCID::Compare);
285  }
286
287  /// isMoveImmediate - Return true if this instruction is a move immediate
288  /// (including conditional moves) instruction.
289  bool isMoveImmediate() const {
290    return Flags & (1 << MCID::MoveImm);
291  }
292
293  /// isBitcast - Return true if this instruction is a bitcast instruction.
294  ///
295  bool isBitcast() const {
296    return Flags & (1 << MCID::Bitcast);
297  }
298
299  /// isSelect - Return true if this is a select instruction.
300  ///
301  bool isSelect() const {
302    return Flags & (1 << MCID::Select);
303  }
304
305  /// isNotDuplicable - Return true if this instruction cannot be safely
306  /// duplicated.  For example, if the instruction has a unique labels attached
307  /// to it, duplicating it would cause multiple definition errors.
308  bool isNotDuplicable() const {
309    return Flags & (1 << MCID::NotDuplicable);
310  }
311
312  /// hasDelaySlot - Returns true if the specified instruction has a delay slot
313  /// which must be filled by the code generator.
314  bool hasDelaySlot() const {
315    return Flags & (1 << MCID::DelaySlot);
316  }
317
318  /// canFoldAsLoad - Return true for instructions that can be folded as
319  /// memory operands in other instructions. The most common use for this
320  /// is instructions that are simple loads from memory that don't modify
321  /// the loaded value in any way, but it can also be used for instructions
322  /// that can be expressed as constant-pool loads, such as V_SETALLONES
323  /// on x86, to allow them to be folded when it is beneficial.
324  /// This should only be set on instructions that return a value in their
325  /// only virtual register definition.
326  bool canFoldAsLoad() const {
327    return Flags & (1 << MCID::FoldableAsLoad);
328  }
329
330  //===--------------------------------------------------------------------===//
331  // Side Effect Analysis
332  //===--------------------------------------------------------------------===//
333
334  /// mayLoad - Return true if this instruction could possibly read memory.
335  /// Instructions with this flag set are not necessarily simple load
336  /// instructions, they may load a value and modify it, for example.
337  bool mayLoad() const {
338    return Flags & (1 << MCID::MayLoad);
339  }
340
341
342  /// mayStore - Return true if this instruction could possibly modify memory.
343  /// Instructions with this flag set are not necessarily simple store
344  /// instructions, they may store a modified value based on their operands, or
345  /// may not actually modify anything, for example.
346  bool mayStore() const {
347    return Flags & (1 << MCID::MayStore);
348  }
349
350  /// hasUnmodeledSideEffects - Return true if this instruction has side
351  /// effects that are not modeled by other flags.  This does not return true
352  /// for instructions whose effects are captured by:
353  ///
354  ///  1. Their operand list and implicit definition/use list.  Register use/def
355  ///     info is explicit for instructions.
356  ///  2. Memory accesses.  Use mayLoad/mayStore.
357  ///  3. Calling, branching, returning: use isCall/isReturn/isBranch.
358  ///
359  /// Examples of side effects would be modifying 'invisible' machine state like
360  /// a control register, flushing a cache, modifying a register invisible to
361  /// LLVM, etc.
362  ///
363  bool hasUnmodeledSideEffects() const {
364    return Flags & (1 << MCID::UnmodeledSideEffects);
365  }
366
367  //===--------------------------------------------------------------------===//
368  // Flags that indicate whether an instruction can be modified by a method.
369  //===--------------------------------------------------------------------===//
370
371  /// isCommutable - Return true if this may be a 2- or 3-address
372  /// instruction (of the form "X = op Y, Z, ..."), which produces the same
373  /// result if Y and Z are exchanged.  If this flag is set, then the
374  /// TargetInstrInfo::commuteInstruction method may be used to hack on the
375  /// instruction.
376  ///
377  /// Note that this flag may be set on instructions that are only commutable
378  /// sometimes.  In these cases, the call to commuteInstruction will fail.
379  /// Also note that some instructions require non-trivial modification to
380  /// commute them.
381  bool isCommutable() const {
382    return Flags & (1 << MCID::Commutable);
383  }
384
385  /// isConvertibleTo3Addr - Return true if this is a 2-address instruction
386  /// which can be changed into a 3-address instruction if needed.  Doing this
387  /// transformation can be profitable in the register allocator, because it
388  /// means that the instruction can use a 2-address form if possible, but
389  /// degrade into a less efficient form if the source and dest register cannot
390  /// be assigned to the same register.  For example, this allows the x86
391  /// backend to turn a "shl reg, 3" instruction into an LEA instruction, which
392  /// is the same speed as the shift but has bigger code size.
393  ///
394  /// If this returns true, then the target must implement the
395  /// TargetInstrInfo::convertToThreeAddress method for this instruction, which
396  /// is allowed to fail if the transformation isn't valid for this specific
397  /// instruction (e.g. shl reg, 4 on x86).
398  ///
399  bool isConvertibleTo3Addr() const {
400    return Flags & (1 << MCID::ConvertibleTo3Addr);
401  }
402
403  /// usesCustomInsertionHook - Return true if this instruction requires
404  /// custom insertion support when the DAG scheduler is inserting it into a
405  /// machine basic block.  If this is true for the instruction, it basically
406  /// means that it is a pseudo instruction used at SelectionDAG time that is
407  /// expanded out into magic code by the target when MachineInstrs are formed.
408  ///
409  /// If this is true, the TargetLoweringInfo::InsertAtEndOfBasicBlock method
410  /// is used to insert this into the MachineBasicBlock.
411  bool usesCustomInsertionHook() const {
412    return Flags & (1 << MCID::UsesCustomInserter);
413  }
414
415  /// hasPostISelHook - Return true if this instruction requires *adjustment*
416  /// after instruction selection by calling a target hook. For example, this
417  /// can be used to fill in ARM 's' optional operand depending on whether
418  /// the conditional flag register is used.
419  bool hasPostISelHook() const {
420    return Flags & (1 << MCID::HasPostISelHook);
421  }
422
423  /// isRematerializable - Returns true if this instruction is a candidate for
424  /// remat.  This flag is deprecated, please don't use it anymore.  If this
425  /// flag is set, the isReallyTriviallyReMaterializable() method is called to
426  /// verify the instruction is really rematable.
427  bool isRematerializable() const {
428    return Flags & (1 << MCID::Rematerializable);
429  }
430
431  /// isAsCheapAsAMove - Returns true if this instruction has the same cost (or
432  /// less) than a move instruction. This is useful during certain types of
433  /// optimizations (e.g., remat during two-address conversion or machine licm)
434  /// where we would like to remat or hoist the instruction, but not if it costs
435  /// more than moving the instruction into the appropriate register. Note, we
436  /// are not marking copies from and to the same register class with this flag.
437  bool isAsCheapAsAMove() const {
438    return Flags & (1 << MCID::CheapAsAMove);
439  }
440
441  /// hasExtraSrcRegAllocReq - Returns true if this instruction source operands
442  /// have special register allocation requirements that are not captured by the
443  /// operand register classes. e.g. ARM::STRD's two source registers must be an
444  /// even / odd pair, ARM::STM registers have to be in ascending order.
445  /// Post-register allocation passes should not attempt to change allocations
446  /// for sources of instructions with this flag.
447  bool hasExtraSrcRegAllocReq() const {
448    return Flags & (1 << MCID::ExtraSrcRegAllocReq);
449  }
450
451  /// hasExtraDefRegAllocReq - Returns true if this instruction def operands
452  /// have special register allocation requirements that are not captured by the
453  /// operand register classes. e.g. ARM::LDRD's two def registers must be an
454  /// even / odd pair, ARM::LDM registers have to be in ascending order.
455  /// Post-register allocation passes should not attempt to change allocations
456  /// for definitions of instructions with this flag.
457  bool hasExtraDefRegAllocReq() const {
458    return Flags & (1 << MCID::ExtraDefRegAllocReq);
459  }
460
461
462  /// getImplicitUses - Return a list of registers that are potentially
463  /// read by any instance of this machine instruction.  For example, on X86,
464  /// the "adc" instruction adds two register operands and adds the carry bit in
465  /// from the flags register.  In this case, the instruction is marked as
466  /// implicitly reading the flags.  Likewise, the variable shift instruction on
467  /// X86 is marked as implicitly reading the 'CL' register, which it always
468  /// does.
469  ///
470  /// This method returns null if the instruction has no implicit uses.
471  const uint16_t *getImplicitUses() const {
472    return ImplicitUses;
473  }
474
475  /// getNumImplicitUses - Return the number of implicit uses this instruction
476  /// has.
477  unsigned getNumImplicitUses() const {
478    if (ImplicitUses == 0) return 0;
479    unsigned i = 0;
480    for (; ImplicitUses[i]; ++i) /*empty*/;
481    return i;
482  }
483
484  /// getImplicitDefs - Return a list of registers that are potentially
485  /// written by any instance of this machine instruction.  For example, on X86,
486  /// many instructions implicitly set the flags register.  In this case, they
487  /// are marked as setting the FLAGS.  Likewise, many instructions always
488  /// deposit their result in a physical register.  For example, the X86 divide
489  /// instruction always deposits the quotient and remainder in the EAX/EDX
490  /// registers.  For that instruction, this will return a list containing the
491  /// EAX/EDX/EFLAGS registers.
492  ///
493  /// This method returns null if the instruction has no implicit defs.
494  const uint16_t *getImplicitDefs() const {
495    return ImplicitDefs;
496  }
497
498  /// getNumImplicitDefs - Return the number of implicit defs this instruction
499  /// has.
500  unsigned getNumImplicitDefs() const {
501    if (ImplicitDefs == 0) return 0;
502    unsigned i = 0;
503    for (; ImplicitDefs[i]; ++i) /*empty*/;
504    return i;
505  }
506
507  /// hasImplicitUseOfPhysReg - Return true if this instruction implicitly
508  /// uses the specified physical register.
509  bool hasImplicitUseOfPhysReg(unsigned Reg) const {
510    if (const uint16_t *ImpUses = ImplicitUses)
511      for (; *ImpUses; ++ImpUses)
512        if (*ImpUses == Reg) return true;
513    return false;
514  }
515
516  /// hasImplicitDefOfPhysReg - Return true if this instruction implicitly
517  /// defines the specified physical register.
518  bool hasImplicitDefOfPhysReg(unsigned Reg,
519                               const MCRegisterInfo *MRI = 0) const {
520    if (const uint16_t *ImpDefs = ImplicitDefs)
521      for (; *ImpDefs; ++ImpDefs)
522        if (*ImpDefs == Reg || (MRI && MRI->isSubRegister(Reg, *ImpDefs)))
523            return true;
524    return false;
525  }
526
527  /// Return true if this instruction defines the specified physical
528  /// register, either explicitly or implicitly.
529  bool hasDefOfPhysReg(const MCInst &MI, unsigned Reg,
530                       const MCRegisterInfo &RI) const {
531    for (int i = 0, e = NumDefs; i != e; ++i)
532      if (MI.getOperand(i).isReg() &&
533          RI.isSubRegisterEq(Reg, MI.getOperand(i).getReg()))
534        return true;
535    return hasImplicitDefOfPhysReg(Reg, &RI);
536  }
537
538  /// getSchedClass - Return the scheduling class for this instruction.  The
539  /// scheduling class is an index into the InstrItineraryData table.  This
540  /// returns zero if there is no known scheduling information for the
541  /// instruction.
542  ///
543  unsigned getSchedClass() const {
544    return SchedClass;
545  }
546
547  /// getSize - Return the number of bytes in the encoding of this instruction,
548  /// or zero if the encoding size cannot be known from the opcode.
549  unsigned getSize() const {
550    return Size;
551  }
552
553  /// findFirstPredOperandIdx() - Find the index of the first operand in the
554  /// operand list that is used to represent the predicate. It returns -1 if
555  /// none is found.
556  int findFirstPredOperandIdx() const {
557    if (isPredicable()) {
558      for (unsigned i = 0, e = getNumOperands(); i != e; ++i)
559        if (OpInfo[i].isPredicate())
560          return i;
561    }
562    return -1;
563  }
564};
565
566} // end namespace llvm
567
568#endif
569