MCRegisterInfo.h revision 209cdc2999208e9783349e970bd96fc37557fd97
1//=== MC/MCRegisterInfo.h - Target Register Description ---------*- C++ -*-===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This file describes an abstract interface used to get information about a 11// target machines register file. This information is used for a variety of 12// purposed, especially register allocation. 13// 14//===----------------------------------------------------------------------===// 15 16#ifndef LLVM_MC_MCREGISTERINFO_H 17#define LLVM_MC_MCREGISTERINFO_H 18 19#include "llvm/ADT/DenseMap.h" 20#include "llvm/Support/ErrorHandling.h" 21#include <cassert> 22 23namespace llvm { 24 25/// MCRegisterClass - Base class of TargetRegisterClass. 26class MCRegisterClass { 27public: 28 typedef const uint16_t* iterator; 29 typedef const uint16_t* const_iterator; 30 31 const char *Name; 32 const iterator RegsBegin; 33 const uint8_t *const RegSet; 34 const uint16_t RegsSize; 35 const uint16_t RegSetSize; 36 const uint16_t ID; 37 const uint16_t RegSize, Alignment; // Size & Alignment of register in bytes 38 const int8_t CopyCost; 39 const bool Allocatable; 40 41 /// getID() - Return the register class ID number. 42 /// 43 unsigned getID() const { return ID; } 44 45 /// getName() - Return the register class name for debugging. 46 /// 47 const char *getName() const { return Name; } 48 49 /// begin/end - Return all of the registers in this class. 50 /// 51 iterator begin() const { return RegsBegin; } 52 iterator end() const { return RegsBegin + RegsSize; } 53 54 /// getNumRegs - Return the number of registers in this class. 55 /// 56 unsigned getNumRegs() const { return RegsSize; } 57 58 /// getRegister - Return the specified register in the class. 59 /// 60 unsigned getRegister(unsigned i) const { 61 assert(i < getNumRegs() && "Register number out of range!"); 62 return RegsBegin[i]; 63 } 64 65 /// contains - Return true if the specified register is included in this 66 /// register class. This does not include virtual registers. 67 bool contains(unsigned Reg) const { 68 unsigned InByte = Reg % 8; 69 unsigned Byte = Reg / 8; 70 if (Byte >= RegSetSize) 71 return false; 72 return (RegSet[Byte] & (1 << InByte)) != 0; 73 } 74 75 /// contains - Return true if both registers are in this class. 76 bool contains(unsigned Reg1, unsigned Reg2) const { 77 return contains(Reg1) && contains(Reg2); 78 } 79 80 /// getSize - Return the size of the register in bytes, which is also the size 81 /// of a stack slot allocated to hold a spilled copy of this register. 82 unsigned getSize() const { return RegSize; } 83 84 /// getAlignment - Return the minimum required alignment for a register of 85 /// this class. 86 unsigned getAlignment() const { return Alignment; } 87 88 /// getCopyCost - Return the cost of copying a value between two registers in 89 /// this class. A negative number means the register class is very expensive 90 /// to copy e.g. status flag register classes. 91 int getCopyCost() const { return CopyCost; } 92 93 /// isAllocatable - Return true if this register class may be used to create 94 /// virtual registers. 95 bool isAllocatable() const { return Allocatable; } 96}; 97 98/// MCRegisterDesc - This record contains all of the information known about 99/// a particular register. The Overlaps field contains a pointer to a zero 100/// terminated array of registers that this register aliases, starting with 101/// itself. This is needed for architectures like X86 which have AL alias AX 102/// alias EAX. The SubRegs field is a zero terminated array of registers that 103/// are sub-registers of the specific register, e.g. AL, AH are sub-registers of 104/// AX. The SuperRegs field is a zero terminated array of registers that are 105/// super-registers of the specific register, e.g. RAX, EAX, are super-registers 106/// of AX. 107/// 108struct MCRegisterDesc { 109 uint32_t Name; // Printable name for the reg (for debugging) 110 uint32_t Overlaps; // Overlapping registers, described above 111 uint32_t SubRegs; // Sub-register set, described above 112 uint32_t SuperRegs; // Super-register set, described above 113 114 // RegUnits - Points to the list of register units. The low 4 bits holds the 115 // Scale, the high bits hold an offset into DiffLists. See MCRegUnitIterator. 116 uint32_t RegUnits; 117}; 118 119/// MCRegisterInfo base class - We assume that the target defines a static 120/// array of MCRegisterDesc objects that represent all of the machine 121/// registers that the target has. As such, we simply have to track a pointer 122/// to this array so that we can turn register number into a register 123/// descriptor. 124/// 125/// Note this class is designed to be a base class of TargetRegisterInfo, which 126/// is the interface used by codegen. However, specific targets *should never* 127/// specialize this class. MCRegisterInfo should only contain getters to access 128/// TableGen generated physical register data. It must not be extended with 129/// virtual methods. 130/// 131class MCRegisterInfo { 132public: 133 typedef const MCRegisterClass *regclass_iterator; 134 135 /// DwarfLLVMRegPair - Emitted by tablegen so Dwarf<->LLVM reg mappings can be 136 /// performed with a binary search. 137 struct DwarfLLVMRegPair { 138 unsigned FromReg; 139 unsigned ToReg; 140 141 bool operator<(DwarfLLVMRegPair RHS) const { return FromReg < RHS.FromReg; } 142 }; 143private: 144 const MCRegisterDesc *Desc; // Pointer to the descriptor array 145 unsigned NumRegs; // Number of entries in the array 146 unsigned RAReg; // Return address register 147 const MCRegisterClass *Classes; // Pointer to the regclass array 148 unsigned NumClasses; // Number of entries in the array 149 unsigned NumRegUnits; // Number of regunits. 150 const uint16_t *RegLists; // Pointer to the reglists array 151 const uint16_t *DiffLists; // Pointer to the difflists array 152 const char *RegStrings; // Pointer to the string table. 153 const uint16_t *SubRegIndices; // Pointer to the subreg lookup 154 // array. 155 unsigned NumSubRegIndices; // Number of subreg indices. 156 const uint16_t *RegEncodingTable; // Pointer to array of register 157 // encodings. 158 159 unsigned L2DwarfRegsSize; 160 unsigned EHL2DwarfRegsSize; 161 unsigned Dwarf2LRegsSize; 162 unsigned EHDwarf2LRegsSize; 163 const DwarfLLVMRegPair *L2DwarfRegs; // LLVM to Dwarf regs mapping 164 const DwarfLLVMRegPair *EHL2DwarfRegs; // LLVM to Dwarf regs mapping EH 165 const DwarfLLVMRegPair *Dwarf2LRegs; // Dwarf to LLVM regs mapping 166 const DwarfLLVMRegPair *EHDwarf2LRegs; // Dwarf to LLVM regs mapping EH 167 DenseMap<unsigned, int> L2SEHRegs; // LLVM to SEH regs mapping 168 169public: 170 /// DiffListIterator - Base iterator class that can traverse the 171 /// differentially encoded register and regunit lists in DiffLists. 172 /// Don't use this class directly, use one of the specialized sub-classes 173 /// defined below. 174 class DiffListIterator { 175 uint16_t Val; 176 const uint16_t *List; 177 178 protected: 179 /// Create an invalid iterator. Call init() to point to something useful. 180 DiffListIterator() : Val(0), List(0) {} 181 182 /// init - Point the iterator to InitVal, decoding subsequent values from 183 /// DiffList. The iterator will initially point to InitVal, sub-classes are 184 /// responsible for skipping the seed value if it is not part of the list. 185 void init(uint16_t InitVal, const uint16_t *DiffList) { 186 Val = InitVal; 187 List = DiffList; 188 } 189 190 /// advance - Move to the next list position, return the applied 191 /// differential. This function does not detect the end of the list, that 192 /// is the caller's responsibility (by checking for a 0 return value). 193 unsigned advance() { 194 assert(isValid() && "Cannot move off the end of the list."); 195 uint16_t D = *List++; 196 Val += D; 197 return D; 198 } 199 200 public: 201 202 /// isValid - returns true if this iterator is not yet at the end. 203 bool isValid() const { return List; } 204 205 /// Dereference the iterator to get the value at the current position. 206 unsigned operator*() const { return Val; } 207 208 /// Pre-increment to move to the next position. 209 void operator++() { 210 // The end of the list is encoded as a 0 differential. 211 if (!advance()) 212 List = 0; 213 } 214 }; 215 216 // These iterators are allowed to sub-class DiffListIterator and access 217 // internal list pointers. 218 friend class MCRegUnitIterator; 219 220 /// InitMCRegisterInfo - Initialize MCRegisterInfo, called by TableGen 221 /// auto-generated routines. *DO NOT USE*. 222 void InitMCRegisterInfo(const MCRegisterDesc *D, unsigned NR, unsigned RA, 223 const MCRegisterClass *C, unsigned NC, unsigned NRU, 224 const uint16_t *RL, 225 const uint16_t *DL, 226 const char *Strings, 227 const uint16_t *SubIndices, 228 unsigned NumIndices, 229 const uint16_t *RET) { 230 Desc = D; 231 NumRegs = NR; 232 RAReg = RA; 233 Classes = C; 234 RegLists = RL; 235 DiffLists = DL; 236 RegStrings = Strings; 237 NumClasses = NC; 238 NumRegUnits = NRU; 239 SubRegIndices = SubIndices; 240 NumSubRegIndices = NumIndices; 241 RegEncodingTable = RET; 242 } 243 244 /// mapLLVMRegsToDwarfRegs - Used to initialize LLVM register to Dwarf 245 /// register number mapping. Called by TableGen auto-generated routines. 246 /// *DO NOT USE*. 247 void mapLLVMRegsToDwarfRegs(const DwarfLLVMRegPair *Map, unsigned Size, 248 bool isEH) { 249 if (isEH) { 250 EHL2DwarfRegs = Map; 251 EHL2DwarfRegsSize = Size; 252 } else { 253 L2DwarfRegs = Map; 254 L2DwarfRegsSize = Size; 255 } 256 } 257 258 /// mapDwarfRegsToLLVMRegs - Used to initialize Dwarf register to LLVM 259 /// register number mapping. Called by TableGen auto-generated routines. 260 /// *DO NOT USE*. 261 void mapDwarfRegsToLLVMRegs(const DwarfLLVMRegPair *Map, unsigned Size, 262 bool isEH) { 263 if (isEH) { 264 EHDwarf2LRegs = Map; 265 EHDwarf2LRegsSize = Size; 266 } else { 267 Dwarf2LRegs = Map; 268 Dwarf2LRegsSize = Size; 269 } 270 } 271 272 /// mapLLVMRegToSEHReg - Used to initialize LLVM register to SEH register 273 /// number mapping. By default the SEH register number is just the same 274 /// as the LLVM register number. 275 /// FIXME: TableGen these numbers. Currently this requires target specific 276 /// initialization code. 277 void mapLLVMRegToSEHReg(unsigned LLVMReg, int SEHReg) { 278 L2SEHRegs[LLVMReg] = SEHReg; 279 } 280 281 /// getRARegister - This method should return the register where the return 282 /// address can be found. 283 unsigned getRARegister() const { 284 return RAReg; 285 } 286 287 const MCRegisterDesc &operator[](unsigned RegNo) const { 288 assert(RegNo < NumRegs && 289 "Attempting to access record for invalid register number!"); 290 return Desc[RegNo]; 291 } 292 293 /// Provide a get method, equivalent to [], but more useful if we have a 294 /// pointer to this object. 295 /// 296 const MCRegisterDesc &get(unsigned RegNo) const { 297 return operator[](RegNo); 298 } 299 300 /// getAliasSet - Return the set of registers aliased by the specified 301 /// register, or a null list of there are none. The list returned is zero 302 /// terminated. 303 /// 304 const uint16_t *getAliasSet(unsigned RegNo) const { 305 // The Overlaps set always begins with Reg itself. 306 return RegLists + get(RegNo).Overlaps + 1; 307 } 308 309 /// getOverlaps - Return a list of registers that overlap Reg, including 310 /// itself. This is the same as the alias set except Reg is included in the 311 /// list. 312 /// These are exactly the registers in { x | regsOverlap(x, Reg) }. 313 /// 314 const uint16_t *getOverlaps(unsigned RegNo) const { 315 return RegLists + get(RegNo).Overlaps; 316 } 317 318 /// getSubRegisters - Return the list of registers that are sub-registers of 319 /// the specified register, or a null list of there are none. The list 320 /// returned is zero terminated and sorted according to super-sub register 321 /// relations. e.g. X86::RAX's sub-register list is EAX, AX, AL, AH. 322 /// 323 const uint16_t *getSubRegisters(unsigned RegNo) const { 324 return RegLists + get(RegNo).SubRegs; 325 } 326 327 /// getSubReg - Returns the physical register number of sub-register "Index" 328 /// for physical register RegNo. Return zero if the sub-register does not 329 /// exist. 330 unsigned getSubReg(unsigned Reg, unsigned Idx) const { 331 return *(SubRegIndices + (Reg - 1) * NumSubRegIndices + Idx - 1); 332 } 333 334 /// getMatchingSuperReg - Return a super-register of the specified register 335 /// Reg so its sub-register of index SubIdx is Reg. 336 unsigned getMatchingSuperReg(unsigned Reg, unsigned SubIdx, 337 const MCRegisterClass *RC) const { 338 for (const uint16_t *SRs = getSuperRegisters(Reg); unsigned SR = *SRs;++SRs) 339 if (Reg == getSubReg(SR, SubIdx) && RC->contains(SR)) 340 return SR; 341 return 0; 342 } 343 344 /// getSubRegIndex - For a given register pair, return the sub-register index 345 /// if the second register is a sub-register of the first. Return zero 346 /// otherwise. 347 unsigned getSubRegIndex(unsigned RegNo, unsigned SubRegNo) const { 348 for (unsigned I = 1; I <= NumSubRegIndices; ++I) 349 if (getSubReg(RegNo, I) == SubRegNo) 350 return I; 351 return 0; 352 } 353 354 /// getSuperRegisters - Return the list of registers that are super-registers 355 /// of the specified register, or a null list of there are none. The list 356 /// returned is zero terminated and sorted according to super-sub register 357 /// relations. e.g. X86::AL's super-register list is AX, EAX, RAX. 358 /// 359 const uint16_t *getSuperRegisters(unsigned RegNo) const { 360 return RegLists + get(RegNo).SuperRegs; 361 } 362 363 /// getName - Return the human-readable symbolic target-specific name for the 364 /// specified physical register. 365 const char *getName(unsigned RegNo) const { 366 return RegStrings + get(RegNo).Name; 367 } 368 369 /// getNumRegs - Return the number of registers this target has (useful for 370 /// sizing arrays holding per register information) 371 unsigned getNumRegs() const { 372 return NumRegs; 373 } 374 375 /// getNumRegUnits - Return the number of (native) register units in the 376 /// target. Register units are numbered from 0 to getNumRegUnits() - 1. They 377 /// can be accessed through MCRegUnitIterator defined below. 378 unsigned getNumRegUnits() const { 379 return NumRegUnits; 380 } 381 382 /// getDwarfRegNum - Map a target register to an equivalent dwarf register 383 /// number. Returns -1 if there is no equivalent value. The second 384 /// parameter allows targets to use different numberings for EH info and 385 /// debugging info. 386 int getDwarfRegNum(unsigned RegNum, bool isEH) const { 387 const DwarfLLVMRegPair *M = isEH ? EHL2DwarfRegs : L2DwarfRegs; 388 unsigned Size = isEH ? EHL2DwarfRegsSize : L2DwarfRegsSize; 389 390 DwarfLLVMRegPair Key = { RegNum, 0 }; 391 const DwarfLLVMRegPair *I = std::lower_bound(M, M+Size, Key); 392 if (I == M+Size || I->FromReg != RegNum) 393 return -1; 394 return I->ToReg; 395 } 396 397 /// getLLVMRegNum - Map a dwarf register back to a target register. 398 /// 399 int getLLVMRegNum(unsigned RegNum, bool isEH) const { 400 const DwarfLLVMRegPair *M = isEH ? EHDwarf2LRegs : Dwarf2LRegs; 401 unsigned Size = isEH ? EHDwarf2LRegsSize : Dwarf2LRegsSize; 402 403 DwarfLLVMRegPair Key = { RegNum, 0 }; 404 const DwarfLLVMRegPair *I = std::lower_bound(M, M+Size, Key); 405 assert(I != M+Size && I->FromReg == RegNum && "Invalid RegNum"); 406 return I->ToReg; 407 } 408 409 /// getSEHRegNum - Map a target register to an equivalent SEH register 410 /// number. Returns LLVM register number if there is no equivalent value. 411 int getSEHRegNum(unsigned RegNum) const { 412 const DenseMap<unsigned, int>::const_iterator I = L2SEHRegs.find(RegNum); 413 if (I == L2SEHRegs.end()) return (int)RegNum; 414 return I->second; 415 } 416 417 regclass_iterator regclass_begin() const { return Classes; } 418 regclass_iterator regclass_end() const { return Classes+NumClasses; } 419 420 unsigned getNumRegClasses() const { 421 return (unsigned)(regclass_end()-regclass_begin()); 422 } 423 424 /// getRegClass - Returns the register class associated with the enumeration 425 /// value. See class MCOperandInfo. 426 const MCRegisterClass getRegClass(unsigned i) const { 427 assert(i < getNumRegClasses() && "Register Class ID out of range"); 428 return Classes[i]; 429 } 430 431 /// getEncodingValue - Returns the encoding for RegNo 432 uint16_t getEncodingValue(unsigned RegNo) const { 433 assert(RegNo < NumRegs && 434 "Attempting to get encoding for invalid register number!"); 435 return RegEncodingTable[RegNo]; 436 } 437 438}; 439 440//===----------------------------------------------------------------------===// 441// Register Units 442//===----------------------------------------------------------------------===// 443 444// Register units are used to compute register aliasing. Every register has at 445// least one register unit, but it can have more. Two registers overlap if and 446// only if they have a common register unit. 447// 448// A target with a complicated sub-register structure will typically have many 449// fewer register units than actual registers. MCRI::getNumRegUnits() returns 450// the number of register units in the target. 451 452// MCRegUnitIterator enumerates a list of register units for Reg. The list is 453// in ascending numerical order. 454class MCRegUnitIterator : public MCRegisterInfo::DiffListIterator { 455public: 456 /// MCRegUnitIterator - Create an iterator that traverses the register units 457 /// in Reg. 458 MCRegUnitIterator(unsigned Reg, const MCRegisterInfo *MCRI) { 459 // Decode the RegUnits MCRegisterDesc field. 460 unsigned RU = MCRI->get(Reg).RegUnits; 461 unsigned Scale = RU & 15; 462 unsigned Offset = RU >> 4; 463 464 // Initialize the iterator to Reg * Scale, and the List pointer to 465 // DiffLists + Offset. 466 init(Reg * Scale, MCRI->DiffLists + Offset); 467 468 // That may not be a valid unit, we need to advance by one to get the real 469 // unit number. The first differential can be 0 which would normally 470 // terminate the list, but since we know every register has at least one 471 // unit, we can allow a 0 differential here. 472 advance(); 473 } 474}; 475 476} // End llvm namespace 477 478#endif 479