MCRegisterInfo.h revision 22de91aec556d44ee580c2e42f45c7675da98349
1//=== MC/MCRegisterInfo.h - Target Register Description ---------*- C++ -*-===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This file describes an abstract interface used to get information about a 11// target machines register file. This information is used for a variety of 12// purposed, especially register allocation. 13// 14//===----------------------------------------------------------------------===// 15 16#ifndef LLVM_MC_MCREGISTERINFO_H 17#define LLVM_MC_MCREGISTERINFO_H 18 19#include "llvm/ADT/DenseMap.h" 20#include "llvm/Support/ErrorHandling.h" 21#include <cassert> 22 23namespace llvm { 24 25/// MCRegisterClass - Base class of TargetRegisterClass. 26class MCRegisterClass { 27public: 28 typedef const uint16_t* iterator; 29 typedef const uint16_t* const_iterator; 30 31 const char *Name; 32 const iterator RegsBegin; 33 const uint8_t *const RegSet; 34 const uint16_t RegsSize; 35 const uint16_t RegSetSize; 36 const uint16_t ID; 37 const uint16_t RegSize, Alignment; // Size & Alignment of register in bytes 38 const int8_t CopyCost; 39 const bool Allocatable; 40 41 /// getID() - Return the register class ID number. 42 /// 43 unsigned getID() const { return ID; } 44 45 /// getName() - Return the register class name for debugging. 46 /// 47 const char *getName() const { return Name; } 48 49 /// begin/end - Return all of the registers in this class. 50 /// 51 iterator begin() const { return RegsBegin; } 52 iterator end() const { return RegsBegin + RegsSize; } 53 54 /// getNumRegs - Return the number of registers in this class. 55 /// 56 unsigned getNumRegs() const { return RegsSize; } 57 58 /// getRegister - Return the specified register in the class. 59 /// 60 unsigned getRegister(unsigned i) const { 61 assert(i < getNumRegs() && "Register number out of range!"); 62 return RegsBegin[i]; 63 } 64 65 /// contains - Return true if the specified register is included in this 66 /// register class. This does not include virtual registers. 67 bool contains(unsigned Reg) const { 68 unsigned InByte = Reg % 8; 69 unsigned Byte = Reg / 8; 70 if (Byte >= RegSetSize) 71 return false; 72 return (RegSet[Byte] & (1 << InByte)) != 0; 73 } 74 75 /// contains - Return true if both registers are in this class. 76 bool contains(unsigned Reg1, unsigned Reg2) const { 77 return contains(Reg1) && contains(Reg2); 78 } 79 80 /// getSize - Return the size of the register in bytes, which is also the size 81 /// of a stack slot allocated to hold a spilled copy of this register. 82 unsigned getSize() const { return RegSize; } 83 84 /// getAlignment - Return the minimum required alignment for a register of 85 /// this class. 86 unsigned getAlignment() const { return Alignment; } 87 88 /// getCopyCost - Return the cost of copying a value between two registers in 89 /// this class. A negative number means the register class is very expensive 90 /// to copy e.g. status flag register classes. 91 int getCopyCost() const { return CopyCost; } 92 93 /// isAllocatable - Return true if this register class may be used to create 94 /// virtual registers. 95 bool isAllocatable() const { return Allocatable; } 96}; 97 98/// MCRegisterDesc - This record contains all of the information known about 99/// a particular register. The Overlaps field contains a pointer to a zero 100/// terminated array of registers that this register aliases, starting with 101/// itself. This is needed for architectures like X86 which have AL alias AX 102/// alias EAX. The SubRegs field is a zero terminated array of registers that 103/// are sub-registers of the specific register, e.g. AL, AH are sub-registers of 104/// AX. The SuperRegs field is a zero terminated array of registers that are 105/// super-registers of the specific register, e.g. RAX, EAX, are super-registers 106/// of AX. 107/// 108struct MCRegisterDesc { 109 uint32_t Name; // Printable name for the reg (for debugging) 110 uint32_t Overlaps; // Overlapping registers, described above 111 uint32_t SubRegs; // Sub-register set, described above 112 uint32_t SuperRegs; // Super-register set, described above 113 114 // RegUnits - Points to the list of register units. The low 4 bits holds the 115 // Scale, the high bits hold an offset into DiffLists. See MCRegUnitIterator. 116 uint32_t RegUnits; 117}; 118 119/// MCRegisterInfo base class - We assume that the target defines a static 120/// array of MCRegisterDesc objects that represent all of the machine 121/// registers that the target has. As such, we simply have to track a pointer 122/// to this array so that we can turn register number into a register 123/// descriptor. 124/// 125/// Note this class is designed to be a base class of TargetRegisterInfo, which 126/// is the interface used by codegen. However, specific targets *should never* 127/// specialize this class. MCRegisterInfo should only contain getters to access 128/// TableGen generated physical register data. It must not be extended with 129/// virtual methods. 130/// 131class MCRegisterInfo { 132public: 133 typedef const MCRegisterClass *regclass_iterator; 134 135 /// DwarfLLVMRegPair - Emitted by tablegen so Dwarf<->LLVM reg mappings can be 136 /// performed with a binary search. 137 struct DwarfLLVMRegPair { 138 unsigned FromReg; 139 unsigned ToReg; 140 141 bool operator<(DwarfLLVMRegPair RHS) const { return FromReg < RHS.FromReg; } 142 }; 143private: 144 const MCRegisterDesc *Desc; // Pointer to the descriptor array 145 unsigned NumRegs; // Number of entries in the array 146 unsigned RAReg; // Return address register 147 const MCRegisterClass *Classes; // Pointer to the regclass array 148 unsigned NumClasses; // Number of entries in the array 149 unsigned NumRegUnits; // Number of regunits. 150 const uint16_t (*RegUnitRoots)[2]; // Pointer to regunit root table. 151 const uint16_t *RegLists; // Pointer to the reglists array 152 const uint16_t *DiffLists; // Pointer to the difflists array 153 const char *RegStrings; // Pointer to the string table. 154 const uint16_t *SubRegIndices; // Pointer to the subreg lookup 155 // array. 156 unsigned NumSubRegIndices; // Number of subreg indices. 157 const uint16_t *RegEncodingTable; // Pointer to array of register 158 // encodings. 159 160 unsigned L2DwarfRegsSize; 161 unsigned EHL2DwarfRegsSize; 162 unsigned Dwarf2LRegsSize; 163 unsigned EHDwarf2LRegsSize; 164 const DwarfLLVMRegPair *L2DwarfRegs; // LLVM to Dwarf regs mapping 165 const DwarfLLVMRegPair *EHL2DwarfRegs; // LLVM to Dwarf regs mapping EH 166 const DwarfLLVMRegPair *Dwarf2LRegs; // Dwarf to LLVM regs mapping 167 const DwarfLLVMRegPair *EHDwarf2LRegs; // Dwarf to LLVM regs mapping EH 168 DenseMap<unsigned, int> L2SEHRegs; // LLVM to SEH regs mapping 169 170public: 171 /// RegListIterator. This iterator class is used to traverse lists of 172 /// super-registers, sub-registers, and overlapping registers. Don't use it 173 /// directly, use one of the sub-classes defined below. 174 class RegListIterator { 175 const uint16_t *Pos; 176 public: 177 explicit RegListIterator(const uint16_t *Table) 178 : Pos(Table) {} 179 180 /// isValid - Return false when the end of the list is reached. 181 bool isValid() const { return *Pos; } 182 183 /// Dereference the iterator to get the current register. 184 unsigned operator*() const { return *Pos; } 185 186 /// Pre-increment. Move to the next register. 187 void operator++() { ++Pos; } 188 }; 189 190 /// DiffListIterator - Base iterator class that can traverse the 191 /// differentially encoded register and regunit lists in DiffLists. 192 /// Don't use this class directly, use one of the specialized sub-classes 193 /// defined below. 194 class DiffListIterator { 195 uint16_t Val; 196 const uint16_t *List; 197 198 protected: 199 /// Create an invalid iterator. Call init() to point to something useful. 200 DiffListIterator() : Val(0), List(0) {} 201 202 /// init - Point the iterator to InitVal, decoding subsequent values from 203 /// DiffList. The iterator will initially point to InitVal, sub-classes are 204 /// responsible for skipping the seed value if it is not part of the list. 205 void init(uint16_t InitVal, const uint16_t *DiffList) { 206 Val = InitVal; 207 List = DiffList; 208 } 209 210 /// advance - Move to the next list position, return the applied 211 /// differential. This function does not detect the end of the list, that 212 /// is the caller's responsibility (by checking for a 0 return value). 213 unsigned advance() { 214 assert(isValid() && "Cannot move off the end of the list."); 215 uint16_t D = *List++; 216 Val += D; 217 return D; 218 } 219 220 public: 221 222 /// isValid - returns true if this iterator is not yet at the end. 223 bool isValid() const { return List; } 224 225 /// Dereference the iterator to get the value at the current position. 226 unsigned operator*() const { return Val; } 227 228 /// Pre-increment to move to the next position. 229 void operator++() { 230 // The end of the list is encoded as a 0 differential. 231 if (!advance()) 232 List = 0; 233 } 234 }; 235 236 // These iterators are allowed to sub-class RegListIterator and 237 // DiffListIterator and access internal list pointers. 238 friend class MCSubRegIterator; 239 friend class MCSuperRegIterator; 240 friend class MCRegAliasIterator; 241 friend class MCRegUnitIterator; 242 friend class MCRegUnitRootIterator; 243 244 /// InitMCRegisterInfo - Initialize MCRegisterInfo, called by TableGen 245 /// auto-generated routines. *DO NOT USE*. 246 void InitMCRegisterInfo(const MCRegisterDesc *D, unsigned NR, unsigned RA, 247 const MCRegisterClass *C, unsigned NC, 248 const uint16_t (*RURoots)[2], 249 unsigned NRU, 250 const uint16_t *RL, 251 const uint16_t *DL, 252 const char *Strings, 253 const uint16_t *SubIndices, 254 unsigned NumIndices, 255 const uint16_t *RET) { 256 Desc = D; 257 NumRegs = NR; 258 RAReg = RA; 259 Classes = C; 260 RegLists = RL; 261 DiffLists = DL; 262 RegStrings = Strings; 263 NumClasses = NC; 264 RegUnitRoots = RURoots; 265 NumRegUnits = NRU; 266 SubRegIndices = SubIndices; 267 NumSubRegIndices = NumIndices; 268 RegEncodingTable = RET; 269 } 270 271 /// mapLLVMRegsToDwarfRegs - Used to initialize LLVM register to Dwarf 272 /// register number mapping. Called by TableGen auto-generated routines. 273 /// *DO NOT USE*. 274 void mapLLVMRegsToDwarfRegs(const DwarfLLVMRegPair *Map, unsigned Size, 275 bool isEH) { 276 if (isEH) { 277 EHL2DwarfRegs = Map; 278 EHL2DwarfRegsSize = Size; 279 } else { 280 L2DwarfRegs = Map; 281 L2DwarfRegsSize = Size; 282 } 283 } 284 285 /// mapDwarfRegsToLLVMRegs - Used to initialize Dwarf register to LLVM 286 /// register number mapping. Called by TableGen auto-generated routines. 287 /// *DO NOT USE*. 288 void mapDwarfRegsToLLVMRegs(const DwarfLLVMRegPair *Map, unsigned Size, 289 bool isEH) { 290 if (isEH) { 291 EHDwarf2LRegs = Map; 292 EHDwarf2LRegsSize = Size; 293 } else { 294 Dwarf2LRegs = Map; 295 Dwarf2LRegsSize = Size; 296 } 297 } 298 299 /// mapLLVMRegToSEHReg - Used to initialize LLVM register to SEH register 300 /// number mapping. By default the SEH register number is just the same 301 /// as the LLVM register number. 302 /// FIXME: TableGen these numbers. Currently this requires target specific 303 /// initialization code. 304 void mapLLVMRegToSEHReg(unsigned LLVMReg, int SEHReg) { 305 L2SEHRegs[LLVMReg] = SEHReg; 306 } 307 308 /// getRARegister - This method should return the register where the return 309 /// address can be found. 310 unsigned getRARegister() const { 311 return RAReg; 312 } 313 314 const MCRegisterDesc &operator[](unsigned RegNo) const { 315 assert(RegNo < NumRegs && 316 "Attempting to access record for invalid register number!"); 317 return Desc[RegNo]; 318 } 319 320 /// Provide a get method, equivalent to [], but more useful if we have a 321 /// pointer to this object. 322 /// 323 const MCRegisterDesc &get(unsigned RegNo) const { 324 return operator[](RegNo); 325 } 326 327 /// getSubReg - Returns the physical register number of sub-register "Index" 328 /// for physical register RegNo. Return zero if the sub-register does not 329 /// exist. 330 unsigned getSubReg(unsigned Reg, unsigned Idx) const { 331 return *(SubRegIndices + (Reg - 1) * NumSubRegIndices + Idx - 1); 332 } 333 334 /// getMatchingSuperReg - Return a super-register of the specified register 335 /// Reg so its sub-register of index SubIdx is Reg. 336 unsigned getMatchingSuperReg(unsigned Reg, unsigned SubIdx, 337 const MCRegisterClass *RC) const; 338 339 /// getSubRegIndex - For a given register pair, return the sub-register index 340 /// if the second register is a sub-register of the first. Return zero 341 /// otherwise. 342 unsigned getSubRegIndex(unsigned RegNo, unsigned SubRegNo) const { 343 for (unsigned I = 1; I <= NumSubRegIndices; ++I) 344 if (getSubReg(RegNo, I) == SubRegNo) 345 return I; 346 return 0; 347 } 348 349 /// getName - Return the human-readable symbolic target-specific name for the 350 /// specified physical register. 351 const char *getName(unsigned RegNo) const { 352 return RegStrings + get(RegNo).Name; 353 } 354 355 /// getNumRegs - Return the number of registers this target has (useful for 356 /// sizing arrays holding per register information) 357 unsigned getNumRegs() const { 358 return NumRegs; 359 } 360 361 /// getNumRegUnits - Return the number of (native) register units in the 362 /// target. Register units are numbered from 0 to getNumRegUnits() - 1. They 363 /// can be accessed through MCRegUnitIterator defined below. 364 unsigned getNumRegUnits() const { 365 return NumRegUnits; 366 } 367 368 /// getDwarfRegNum - Map a target register to an equivalent dwarf register 369 /// number. Returns -1 if there is no equivalent value. The second 370 /// parameter allows targets to use different numberings for EH info and 371 /// debugging info. 372 int getDwarfRegNum(unsigned RegNum, bool isEH) const { 373 const DwarfLLVMRegPair *M = isEH ? EHL2DwarfRegs : L2DwarfRegs; 374 unsigned Size = isEH ? EHL2DwarfRegsSize : L2DwarfRegsSize; 375 376 DwarfLLVMRegPair Key = { RegNum, 0 }; 377 const DwarfLLVMRegPair *I = std::lower_bound(M, M+Size, Key); 378 if (I == M+Size || I->FromReg != RegNum) 379 return -1; 380 return I->ToReg; 381 } 382 383 /// getLLVMRegNum - Map a dwarf register back to a target register. 384 /// 385 int getLLVMRegNum(unsigned RegNum, bool isEH) const { 386 const DwarfLLVMRegPair *M = isEH ? EHDwarf2LRegs : Dwarf2LRegs; 387 unsigned Size = isEH ? EHDwarf2LRegsSize : Dwarf2LRegsSize; 388 389 DwarfLLVMRegPair Key = { RegNum, 0 }; 390 const DwarfLLVMRegPair *I = std::lower_bound(M, M+Size, Key); 391 assert(I != M+Size && I->FromReg == RegNum && "Invalid RegNum"); 392 return I->ToReg; 393 } 394 395 /// getSEHRegNum - Map a target register to an equivalent SEH register 396 /// number. Returns LLVM register number if there is no equivalent value. 397 int getSEHRegNum(unsigned RegNum) const { 398 const DenseMap<unsigned, int>::const_iterator I = L2SEHRegs.find(RegNum); 399 if (I == L2SEHRegs.end()) return (int)RegNum; 400 return I->second; 401 } 402 403 regclass_iterator regclass_begin() const { return Classes; } 404 regclass_iterator regclass_end() const { return Classes+NumClasses; } 405 406 unsigned getNumRegClasses() const { 407 return (unsigned)(regclass_end()-regclass_begin()); 408 } 409 410 /// getRegClass - Returns the register class associated with the enumeration 411 /// value. See class MCOperandInfo. 412 const MCRegisterClass getRegClass(unsigned i) const { 413 assert(i < getNumRegClasses() && "Register Class ID out of range"); 414 return Classes[i]; 415 } 416 417 /// getEncodingValue - Returns the encoding for RegNo 418 uint16_t getEncodingValue(unsigned RegNo) const { 419 assert(RegNo < NumRegs && 420 "Attempting to get encoding for invalid register number!"); 421 return RegEncodingTable[RegNo]; 422 } 423 424}; 425 426//===----------------------------------------------------------------------===// 427// Register List Iterators 428//===----------------------------------------------------------------------===// 429 430// MCRegisterInfo provides lists of super-registers, sub-registers, and 431// aliasing registers. Use these iterator classes to traverse the lists. 432 433/// MCSubRegIterator enumerates all sub-registers of Reg. 434class MCSubRegIterator : public MCRegisterInfo::RegListIterator { 435public: 436 MCSubRegIterator(unsigned Reg, const MCRegisterInfo *MCRI) 437 : RegListIterator(MCRI->RegLists + MCRI->get(Reg).SubRegs) {} 438}; 439 440/// MCSuperRegIterator enumerates all super-registers of Reg. 441class MCSuperRegIterator : public MCRegisterInfo::RegListIterator { 442public: 443 MCSuperRegIterator(unsigned Reg, const MCRegisterInfo *MCRI) 444 : RegListIterator(MCRI->RegLists + MCRI->get(Reg).SuperRegs) {} 445}; 446 447/// MCRegAliasIterator enumerates all registers aliasing Reg. 448/// If IncludeSelf is set, Reg itself is included in the list. 449class MCRegAliasIterator : public MCRegisterInfo::RegListIterator { 450public: 451 MCRegAliasIterator(unsigned Reg, const MCRegisterInfo *MCRI, bool IncludeSelf) 452 : RegListIterator(MCRI->RegLists + MCRI->get(Reg).Overlaps + !IncludeSelf) 453 {} 454}; 455 456inline 457unsigned MCRegisterInfo::getMatchingSuperReg(unsigned Reg, unsigned SubIdx, 458 const MCRegisterClass *RC) const { 459 for (MCSuperRegIterator Supers(Reg, this); Supers.isValid(); ++Supers) 460 if (Reg == getSubReg(*Supers, SubIdx) && RC->contains(*Supers)) 461 return *Supers; 462 return 0; 463} 464 465//===----------------------------------------------------------------------===// 466// Register Units 467//===----------------------------------------------------------------------===// 468 469// Register units are used to compute register aliasing. Every register has at 470// least one register unit, but it can have more. Two registers overlap if and 471// only if they have a common register unit. 472// 473// A target with a complicated sub-register structure will typically have many 474// fewer register units than actual registers. MCRI::getNumRegUnits() returns 475// the number of register units in the target. 476 477// MCRegUnitIterator enumerates a list of register units for Reg. The list is 478// in ascending numerical order. 479class MCRegUnitIterator : public MCRegisterInfo::DiffListIterator { 480public: 481 /// MCRegUnitIterator - Create an iterator that traverses the register units 482 /// in Reg. 483 MCRegUnitIterator(unsigned Reg, const MCRegisterInfo *MCRI) { 484 // Decode the RegUnits MCRegisterDesc field. 485 unsigned RU = MCRI->get(Reg).RegUnits; 486 unsigned Scale = RU & 15; 487 unsigned Offset = RU >> 4; 488 489 // Initialize the iterator to Reg * Scale, and the List pointer to 490 // DiffLists + Offset. 491 init(Reg * Scale, MCRI->DiffLists + Offset); 492 493 // That may not be a valid unit, we need to advance by one to get the real 494 // unit number. The first differential can be 0 which would normally 495 // terminate the list, but since we know every register has at least one 496 // unit, we can allow a 0 differential here. 497 advance(); 498 } 499}; 500 501// Each register unit has one or two root registers. The complete set of 502// registers containing a register unit is the union of the roots and their 503// super-registers. All registers aliasing Unit can be visited like this: 504// 505// for (MCRegUnitRootIterator RI(Unit, MCRI); RI.isValid(); ++RI) { 506// unsigned Root = *RI; 507// visit(Root); 508// for (MCSuperRegIterator SI(Root, MCRI); SI.isValid(); ++SI) 509// visit(*SI); 510// } 511 512/// MCRegUnitRootIterator enumerates the root registers of a register unit. 513class MCRegUnitRootIterator { 514 uint16_t Reg0; 515 uint16_t Reg1; 516public: 517 MCRegUnitRootIterator(unsigned RegUnit, const MCRegisterInfo *MCRI) { 518 assert(RegUnit < MCRI->getNumRegUnits() && "Invalid register unit"); 519 Reg0 = MCRI->RegUnitRoots[RegUnit][0]; 520 Reg1 = MCRI->RegUnitRoots[RegUnit][1]; 521 } 522 523 /// Dereference to get the current root register. 524 unsigned operator*() const { 525 return Reg0; 526 } 527 528 /// isValid - Check if the iterator is at the end of the list. 529 bool isValid() const { 530 return Reg0; 531 } 532 533 /// Preincrement to move to the next root register. 534 void operator++() { 535 assert(isValid() && "Cannot move off the end of the list."); 536 Reg0 = Reg1; 537 Reg1 = 0; 538 } 539}; 540 541} // End llvm namespace 542 543#endif 544