12661b411ccc81b1fe19194d3f43b2630cbef3f28Andrew Trick//===-- llvm/MC/MCSchedule.h - Scheduling -----------------------*- C++ -*-===// 22661b411ccc81b1fe19194d3f43b2630cbef3f28Andrew Trick// 32661b411ccc81b1fe19194d3f43b2630cbef3f28Andrew Trick// The LLVM Compiler Infrastructure 42661b411ccc81b1fe19194d3f43b2630cbef3f28Andrew Trick// 52661b411ccc81b1fe19194d3f43b2630cbef3f28Andrew Trick// This file is distributed under the University of Illinois Open Source 62661b411ccc81b1fe19194d3f43b2630cbef3f28Andrew Trick// License. See LICENSE.TXT for details. 72661b411ccc81b1fe19194d3f43b2630cbef3f28Andrew Trick// 82661b411ccc81b1fe19194d3f43b2630cbef3f28Andrew Trick//===----------------------------------------------------------------------===// 92661b411ccc81b1fe19194d3f43b2630cbef3f28Andrew Trick// 102661b411ccc81b1fe19194d3f43b2630cbef3f28Andrew Trick// This file defines the classes used to describe a subtarget's machine model 112661b411ccc81b1fe19194d3f43b2630cbef3f28Andrew Trick// for scheduling and other instruction cost heuristics. 122661b411ccc81b1fe19194d3f43b2630cbef3f28Andrew Trick// 132661b411ccc81b1fe19194d3f43b2630cbef3f28Andrew Trick//===----------------------------------------------------------------------===// 142661b411ccc81b1fe19194d3f43b2630cbef3f28Andrew Trick 15674be02d525d4e24bc6943ed9274958c580bcfbcJakub Staszak#ifndef LLVM_MC_MCSCHEDULE_H 16674be02d525d4e24bc6943ed9274958c580bcfbcJakub Staszak#define LLVM_MC_MCSCHEDULE_H 172661b411ccc81b1fe19194d3f43b2630cbef3f28Andrew Trick 182661b411ccc81b1fe19194d3f43b2630cbef3f28Andrew Trick#include "llvm/Support/DataTypes.h" 1972d048b69705f01d48bdef7b235ec96b24290767Andrew Trick#include <cassert> 202661b411ccc81b1fe19194d3f43b2630cbef3f28Andrew Trick 212661b411ccc81b1fe19194d3f43b2630cbef3f28Andrew Tricknamespace llvm { 222661b411ccc81b1fe19194d3f43b2630cbef3f28Andrew Trick 232661b411ccc81b1fe19194d3f43b2630cbef3f28Andrew Trickstruct InstrItinerary; 242661b411ccc81b1fe19194d3f43b2630cbef3f28Andrew Trick 2572d048b69705f01d48bdef7b235ec96b24290767Andrew Trick/// Define a kind of processor resource that will be modeled by the scheduler. 2672d048b69705f01d48bdef7b235ec96b24290767Andrew Trickstruct MCProcResourceDesc { 2772d048b69705f01d48bdef7b235ec96b24290767Andrew Trick#ifndef NDEBUG 2872d048b69705f01d48bdef7b235ec96b24290767Andrew Trick const char *Name; 2972d048b69705f01d48bdef7b235ec96b24290767Andrew Trick#endif 306312cb099734263f348f36a31b8892b1373a7076Andrew Trick unsigned NumUnits; // Number of resource of this kind 3172d048b69705f01d48bdef7b235ec96b24290767Andrew Trick unsigned SuperIdx; // Index of the resources kind that contains this kind. 3272d048b69705f01d48bdef7b235ec96b24290767Andrew Trick 33b86a0cdb674549d8493043331cecd9cbf53b80daAndrew Trick // Number of resources that may be buffered. 34b86a0cdb674549d8493043331cecd9cbf53b80daAndrew Trick // 3536b56886974eae4f9c5ebc96befd3e7bfe5de338Stephen Hines // Buffered resources (BufferSize != 0) may be consumed at some indeterminate 3636b56886974eae4f9c5ebc96befd3e7bfe5de338Stephen Hines // cycle after dispatch. This should be used for out-of-order cpus when 3736b56886974eae4f9c5ebc96befd3e7bfe5de338Stephen Hines // instructions that use this resource can be buffered in a reservaton 3836b56886974eae4f9c5ebc96befd3e7bfe5de338Stephen Hines // station. 3936b56886974eae4f9c5ebc96befd3e7bfe5de338Stephen Hines // 4036b56886974eae4f9c5ebc96befd3e7bfe5de338Stephen Hines // Unbuffered resources (BufferSize == 0) always consume their resource some 4136b56886974eae4f9c5ebc96befd3e7bfe5de338Stephen Hines // fixed number of cycles after dispatch. If a resource is unbuffered, then 4236b56886974eae4f9c5ebc96befd3e7bfe5de338Stephen Hines // the scheduler will avoid scheduling instructions with conflicting resources 4336b56886974eae4f9c5ebc96befd3e7bfe5de338Stephen Hines // in the same cycle. This is for in-order cpus, or the in-order portion of 4436b56886974eae4f9c5ebc96befd3e7bfe5de338Stephen Hines // an out-of-order cpus. 45b86a0cdb674549d8493043331cecd9cbf53b80daAndrew Trick int BufferSize; 466312cb099734263f348f36a31b8892b1373a7076Andrew Trick 4772d048b69705f01d48bdef7b235ec96b24290767Andrew Trick bool operator==(const MCProcResourceDesc &Other) const { 486312cb099734263f348f36a31b8892b1373a7076Andrew Trick return NumUnits == Other.NumUnits && SuperIdx == Other.SuperIdx 49b86a0cdb674549d8493043331cecd9cbf53b80daAndrew Trick && BufferSize == Other.BufferSize; 5072d048b69705f01d48bdef7b235ec96b24290767Andrew Trick } 5172d048b69705f01d48bdef7b235ec96b24290767Andrew Trick}; 5272d048b69705f01d48bdef7b235ec96b24290767Andrew Trick 5372d048b69705f01d48bdef7b235ec96b24290767Andrew Trick/// Identify one of the processor resource kinds consumed by a particular 5472d048b69705f01d48bdef7b235ec96b24290767Andrew Trick/// scheduling class for the specified number of cycles. 5572d048b69705f01d48bdef7b235ec96b24290767Andrew Trickstruct MCWriteProcResEntry { 5672d048b69705f01d48bdef7b235ec96b24290767Andrew Trick unsigned ProcResourceIdx; 5772d048b69705f01d48bdef7b235ec96b24290767Andrew Trick unsigned Cycles; 5872d048b69705f01d48bdef7b235ec96b24290767Andrew Trick 5972d048b69705f01d48bdef7b235ec96b24290767Andrew Trick bool operator==(const MCWriteProcResEntry &Other) const { 6072d048b69705f01d48bdef7b235ec96b24290767Andrew Trick return ProcResourceIdx == Other.ProcResourceIdx && Cycles == Other.Cycles; 6172d048b69705f01d48bdef7b235ec96b24290767Andrew Trick } 6272d048b69705f01d48bdef7b235ec96b24290767Andrew Trick}; 6372d048b69705f01d48bdef7b235ec96b24290767Andrew Trick 6472d048b69705f01d48bdef7b235ec96b24290767Andrew Trick/// Specify the latency in cpu cycles for a particular scheduling class and def 65fdd6fa89b960088b368231ec08e56a0c0b1e6930Andrew Trick/// index. -1 indicates an invalid latency. Heuristics would typically consider 66fdd6fa89b960088b368231ec08e56a0c0b1e6930Andrew Trick/// an instruction with invalid latency to have infinite latency. Also identify 67fdd6fa89b960088b368231ec08e56a0c0b1e6930Andrew Trick/// the WriteResources of this def. When the operand expands to a sequence of 68fdd6fa89b960088b368231ec08e56a0c0b1e6930Andrew Trick/// writes, this ID is the last write in the sequence. 6972d048b69705f01d48bdef7b235ec96b24290767Andrew Trickstruct MCWriteLatencyEntry { 70fdd6fa89b960088b368231ec08e56a0c0b1e6930Andrew Trick int Cycles; 7172d048b69705f01d48bdef7b235ec96b24290767Andrew Trick unsigned WriteResourceID; 7272d048b69705f01d48bdef7b235ec96b24290767Andrew Trick 7372d048b69705f01d48bdef7b235ec96b24290767Andrew Trick bool operator==(const MCWriteLatencyEntry &Other) const { 7472d048b69705f01d48bdef7b235ec96b24290767Andrew Trick return Cycles == Other.Cycles && WriteResourceID == Other.WriteResourceID; 7572d048b69705f01d48bdef7b235ec96b24290767Andrew Trick } 7672d048b69705f01d48bdef7b235ec96b24290767Andrew Trick}; 7772d048b69705f01d48bdef7b235ec96b24290767Andrew Trick 7872d048b69705f01d48bdef7b235ec96b24290767Andrew Trick/// Specify the number of cycles allowed after instruction issue before a 7972d048b69705f01d48bdef7b235ec96b24290767Andrew Trick/// particular use operand reads its registers. This effectively reduces the 8072d048b69705f01d48bdef7b235ec96b24290767Andrew Trick/// write's latency. Here we allow negative cycles for corner cases where 8172d048b69705f01d48bdef7b235ec96b24290767Andrew Trick/// latency increases. This rule only applies when the entry's WriteResource 8272d048b69705f01d48bdef7b235ec96b24290767Andrew Trick/// matches the write's WriteResource. 8372d048b69705f01d48bdef7b235ec96b24290767Andrew Trick/// 8472d048b69705f01d48bdef7b235ec96b24290767Andrew Trick/// MCReadAdvanceEntries are sorted first by operand index (UseIdx), then by 8572d048b69705f01d48bdef7b235ec96b24290767Andrew Trick/// WriteResourceIdx. 8672d048b69705f01d48bdef7b235ec96b24290767Andrew Trickstruct MCReadAdvanceEntry { 8772d048b69705f01d48bdef7b235ec96b24290767Andrew Trick unsigned UseIdx; 8872d048b69705f01d48bdef7b235ec96b24290767Andrew Trick unsigned WriteResourceID; 8972d048b69705f01d48bdef7b235ec96b24290767Andrew Trick int Cycles; 9072d048b69705f01d48bdef7b235ec96b24290767Andrew Trick 9172d048b69705f01d48bdef7b235ec96b24290767Andrew Trick bool operator==(const MCReadAdvanceEntry &Other) const { 9272d048b69705f01d48bdef7b235ec96b24290767Andrew Trick return UseIdx == Other.UseIdx && WriteResourceID == Other.WriteResourceID 9372d048b69705f01d48bdef7b235ec96b24290767Andrew Trick && Cycles == Other.Cycles; 9472d048b69705f01d48bdef7b235ec96b24290767Andrew Trick } 9572d048b69705f01d48bdef7b235ec96b24290767Andrew Trick}; 9672d048b69705f01d48bdef7b235ec96b24290767Andrew Trick 9772d048b69705f01d48bdef7b235ec96b24290767Andrew Trick/// Summarize the scheduling resources required for an instruction of a 9872d048b69705f01d48bdef7b235ec96b24290767Andrew Trick/// particular scheduling class. 9972d048b69705f01d48bdef7b235ec96b24290767Andrew Trick/// 10072d048b69705f01d48bdef7b235ec96b24290767Andrew Trick/// Defined as an aggregate struct for creating tables with initializer lists. 10172d048b69705f01d48bdef7b235ec96b24290767Andrew Trickstruct MCSchedClassDesc { 10272d048b69705f01d48bdef7b235ec96b24290767Andrew Trick static const unsigned short InvalidNumMicroOps = UINT16_MAX; 10372d048b69705f01d48bdef7b235ec96b24290767Andrew Trick static const unsigned short VariantNumMicroOps = UINT16_MAX - 1; 10472d048b69705f01d48bdef7b235ec96b24290767Andrew Trick 10572d048b69705f01d48bdef7b235ec96b24290767Andrew Trick#ifndef NDEBUG 10672d048b69705f01d48bdef7b235ec96b24290767Andrew Trick const char* Name; 10772d048b69705f01d48bdef7b235ec96b24290767Andrew Trick#endif 10872d048b69705f01d48bdef7b235ec96b24290767Andrew Trick unsigned short NumMicroOps; 10972d048b69705f01d48bdef7b235ec96b24290767Andrew Trick bool BeginGroup; 11072d048b69705f01d48bdef7b235ec96b24290767Andrew Trick bool EndGroup; 11172d048b69705f01d48bdef7b235ec96b24290767Andrew Trick unsigned WriteProcResIdx; // First index into WriteProcResTable. 11272d048b69705f01d48bdef7b235ec96b24290767Andrew Trick unsigned NumWriteProcResEntries; 11372d048b69705f01d48bdef7b235ec96b24290767Andrew Trick unsigned WriteLatencyIdx; // First index into WriteLatencyTable. 11472d048b69705f01d48bdef7b235ec96b24290767Andrew Trick unsigned NumWriteLatencyEntries; 11572d048b69705f01d48bdef7b235ec96b24290767Andrew Trick unsigned ReadAdvanceIdx; // First index into ReadAdvanceTable. 11672d048b69705f01d48bdef7b235ec96b24290767Andrew Trick unsigned NumReadAdvanceEntries; 11772d048b69705f01d48bdef7b235ec96b24290767Andrew Trick 11872d048b69705f01d48bdef7b235ec96b24290767Andrew Trick bool isValid() const { 11972d048b69705f01d48bdef7b235ec96b24290767Andrew Trick return NumMicroOps != InvalidNumMicroOps; 12072d048b69705f01d48bdef7b235ec96b24290767Andrew Trick } 12172d048b69705f01d48bdef7b235ec96b24290767Andrew Trick bool isVariant() const { 12272d048b69705f01d48bdef7b235ec96b24290767Andrew Trick return NumMicroOps == VariantNumMicroOps; 12372d048b69705f01d48bdef7b235ec96b24290767Andrew Trick } 12472d048b69705f01d48bdef7b235ec96b24290767Andrew Trick}; 12572d048b69705f01d48bdef7b235ec96b24290767Andrew Trick 1262661b411ccc81b1fe19194d3f43b2630cbef3f28Andrew Trick/// Machine model for scheduling, bundling, and heuristics. 1272661b411ccc81b1fe19194d3f43b2630cbef3f28Andrew Trick/// 1282661b411ccc81b1fe19194d3f43b2630cbef3f28Andrew Trick/// The machine model directly provides basic information about the 1292661b411ccc81b1fe19194d3f43b2630cbef3f28Andrew Trick/// microarchitecture to the scheduler in the form of properties. It also 13072d048b69705f01d48bdef7b235ec96b24290767Andrew Trick/// optionally refers to scheduler resource tables and itinerary 13172d048b69705f01d48bdef7b235ec96b24290767Andrew Trick/// tables. Scheduler resource tables model the latency and cost for each 132135fe6ac5f5b80ef68c19b3ec7bb0063e28f2babBenjamin Kramer/// instruction type. Itinerary tables are an independent mechanism that 1332661b411ccc81b1fe19194d3f43b2630cbef3f28Andrew Trick/// provides a detailed reservation table describing each cycle of instruction 1342661b411ccc81b1fe19194d3f43b2630cbef3f28Andrew Trick/// execution. Subtargets may define any or all of the above categories of data 1352661b411ccc81b1fe19194d3f43b2630cbef3f28Andrew Trick/// depending on the type of CPU and selected scheduler. 1362661b411ccc81b1fe19194d3f43b2630cbef3f28Andrew Trickclass MCSchedModel { 1372661b411ccc81b1fe19194d3f43b2630cbef3f28Andrew Trickpublic: 1382661b411ccc81b1fe19194d3f43b2630cbef3f28Andrew Trick static MCSchedModel DefaultSchedModel; // For unknown processors. 1392661b411ccc81b1fe19194d3f43b2630cbef3f28Andrew Trick 1402661b411ccc81b1fe19194d3f43b2630cbef3f28Andrew Trick // IssueWidth is the maximum number of instructions that may be scheduled in 1412661b411ccc81b1fe19194d3f43b2630cbef3f28Andrew Trick // the same per-cycle group. 1422661b411ccc81b1fe19194d3f43b2630cbef3f28Andrew Trick unsigned IssueWidth; 1432661b411ccc81b1fe19194d3f43b2630cbef3f28Andrew Trick static const unsigned DefaultIssueWidth = 1; 1442661b411ccc81b1fe19194d3f43b2630cbef3f28Andrew Trick 145b86a0cdb674549d8493043331cecd9cbf53b80daAndrew Trick // MicroOpBufferSize is the number of micro-ops that the processor may buffer 146b86a0cdb674549d8493043331cecd9cbf53b80daAndrew Trick // for out-of-order execution. 1472661b411ccc81b1fe19194d3f43b2630cbef3f28Andrew Trick // 148b86a0cdb674549d8493043331cecd9cbf53b80daAndrew Trick // "0" means operations that are not ready in this cycle are not considered 149b86a0cdb674549d8493043331cecd9cbf53b80daAndrew Trick // for scheduling (they go in the pending queue). Latency is paramount. This 150b86a0cdb674549d8493043331cecd9cbf53b80daAndrew Trick // may be more efficient if many instructions are pending in a schedule. 1512661b411ccc81b1fe19194d3f43b2630cbef3f28Andrew Trick // 152b86a0cdb674549d8493043331cecd9cbf53b80daAndrew Trick // "1" means all instructions are considered for scheduling regardless of 153b86a0cdb674549d8493043331cecd9cbf53b80daAndrew Trick // whether they are ready in this cycle. Latency still causes issue stalls, 154b86a0cdb674549d8493043331cecd9cbf53b80daAndrew Trick // but we balance those stalls against other heuristics. 1552661b411ccc81b1fe19194d3f43b2630cbef3f28Andrew Trick // 156b86a0cdb674549d8493043331cecd9cbf53b80daAndrew Trick // "> 1" means the processor is out-of-order. This is a machine independent 15736b56886974eae4f9c5ebc96befd3e7bfe5de338Stephen Hines // estimate of highly machine specific characteristics such as the register 158b86a0cdb674549d8493043331cecd9cbf53b80daAndrew Trick // renaming pool and reorder buffer. 159b86a0cdb674549d8493043331cecd9cbf53b80daAndrew Trick unsigned MicroOpBufferSize; 160b86a0cdb674549d8493043331cecd9cbf53b80daAndrew Trick static const unsigned DefaultMicroOpBufferSize = 0; 1612661b411ccc81b1fe19194d3f43b2630cbef3f28Andrew Trick 162dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hines // LoopMicroOpBufferSize is the number of micro-ops that the processor may 163dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hines // buffer for optimized loop execution. More generally, this represents the 164dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hines // optimal number of micro-ops in a loop body. A loop may be partially 165dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hines // unrolled to bring the count of micro-ops in the loop body closer to this 166dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hines // number. 167dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hines unsigned LoopMicroOpBufferSize; 168dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hines static const unsigned DefaultLoopMicroOpBufferSize = 0; 169dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hines 1702661b411ccc81b1fe19194d3f43b2630cbef3f28Andrew Trick // LoadLatency is the expected latency of load instructions. 1712661b411ccc81b1fe19194d3f43b2630cbef3f28Andrew Trick // 1722661b411ccc81b1fe19194d3f43b2630cbef3f28Andrew Trick // If MinLatency >= 0, this may be overriden for individual load opcodes by 1732661b411ccc81b1fe19194d3f43b2630cbef3f28Andrew Trick // InstrItinerary OperandCycles. 1742661b411ccc81b1fe19194d3f43b2630cbef3f28Andrew Trick unsigned LoadLatency; 1752661b411ccc81b1fe19194d3f43b2630cbef3f28Andrew Trick static const unsigned DefaultLoadLatency = 4; 1762661b411ccc81b1fe19194d3f43b2630cbef3f28Andrew Trick 1772661b411ccc81b1fe19194d3f43b2630cbef3f28Andrew Trick // HighLatency is the expected latency of "very high latency" operations. 1782661b411ccc81b1fe19194d3f43b2630cbef3f28Andrew Trick // See TargetInstrInfo::isHighLatencyDef(). 1792661b411ccc81b1fe19194d3f43b2630cbef3f28Andrew Trick // By default, this is set to an arbitrarily high number of cycles 1802661b411ccc81b1fe19194d3f43b2630cbef3f28Andrew Trick // likely to have some impact on scheduling heuristics. 1812661b411ccc81b1fe19194d3f43b2630cbef3f28Andrew Trick // If MinLatency >= 0, this may be overriden by InstrItinData OperandCycles. 1822661b411ccc81b1fe19194d3f43b2630cbef3f28Andrew Trick unsigned HighLatency; 1832661b411ccc81b1fe19194d3f43b2630cbef3f28Andrew Trick static const unsigned DefaultHighLatency = 10; 1842661b411ccc81b1fe19194d3f43b2630cbef3f28Andrew Trick 185d43b5c97cff06d7840b974ca84fa0639d2567968Andrew Trick // MispredictPenalty is the typical number of extra cycles the processor 186d43b5c97cff06d7840b974ca84fa0639d2567968Andrew Trick // takes to recover from a branch misprediction. 187d43b5c97cff06d7840b974ca84fa0639d2567968Andrew Trick unsigned MispredictPenalty; 188d43b5c97cff06d7840b974ca84fa0639d2567968Andrew Trick static const unsigned DefaultMispredictPenalty = 10; 189d43b5c97cff06d7840b974ca84fa0639d2567968Andrew Trick 190070156437752179833b1e5fddd50caa03fd7c12fAndrew Trick bool CompleteModel; 191070156437752179833b1e5fddd50caa03fd7c12fAndrew Trick 1922661b411ccc81b1fe19194d3f43b2630cbef3f28Andrew Trickprivate: 19372d048b69705f01d48bdef7b235ec96b24290767Andrew Trick unsigned ProcID; 19472d048b69705f01d48bdef7b235ec96b24290767Andrew Trick const MCProcResourceDesc *ProcResourceTable; 19572d048b69705f01d48bdef7b235ec96b24290767Andrew Trick const MCSchedClassDesc *SchedClassTable; 19672d048b69705f01d48bdef7b235ec96b24290767Andrew Trick unsigned NumProcResourceKinds; 19772d048b69705f01d48bdef7b235ec96b24290767Andrew Trick unsigned NumSchedClasses; 1982661b411ccc81b1fe19194d3f43b2630cbef3f28Andrew Trick // Instruction itinerary tables used by InstrItineraryData. 1992661b411ccc81b1fe19194d3f43b2630cbef3f28Andrew Trick friend class InstrItineraryData; 2002661b411ccc81b1fe19194d3f43b2630cbef3f28Andrew Trick const InstrItinerary *InstrItineraries; 2012661b411ccc81b1fe19194d3f43b2630cbef3f28Andrew Trick 2022661b411ccc81b1fe19194d3f43b2630cbef3f28Andrew Trickpublic: 2032661b411ccc81b1fe19194d3f43b2630cbef3f28Andrew Trick // Default's must be specified as static const literals so that tablegenerated 2042661b411ccc81b1fe19194d3f43b2630cbef3f28Andrew Trick // target code can use it in static initializers. The defaults need to be 2052661b411ccc81b1fe19194d3f43b2630cbef3f28Andrew Trick // initialized in this default ctor because some clients directly instantiate 2062661b411ccc81b1fe19194d3f43b2630cbef3f28Andrew Trick // MCSchedModel instead of using a generated itinerary. 207ebd78710eb12794d9b8ca0307ae1f916e0ecbe80Jakob Stoklund Olesen MCSchedModel(): IssueWidth(DefaultIssueWidth), 208b86a0cdb674549d8493043331cecd9cbf53b80daAndrew Trick MicroOpBufferSize(DefaultMicroOpBufferSize), 209dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hines LoopMicroOpBufferSize(DefaultLoopMicroOpBufferSize), 2102661b411ccc81b1fe19194d3f43b2630cbef3f28Andrew Trick LoadLatency(DefaultLoadLatency), 2112661b411ccc81b1fe19194d3f43b2630cbef3f28Andrew Trick HighLatency(DefaultHighLatency), 212d43b5c97cff06d7840b974ca84fa0639d2567968Andrew Trick MispredictPenalty(DefaultMispredictPenalty), 213dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hines CompleteModel(true), ProcID(0), ProcResourceTable(nullptr), 214dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hines SchedClassTable(nullptr), NumProcResourceKinds(0), 215dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hines NumSchedClasses(0), InstrItineraries(nullptr) { 216e127dfd0b175b5a336e61fecaad7fc2aec65d95cAndrew Trick (void)NumProcResourceKinds; 217e127dfd0b175b5a336e61fecaad7fc2aec65d95cAndrew Trick (void)NumSchedClasses; 218e127dfd0b175b5a336e61fecaad7fc2aec65d95cAndrew Trick } 2192661b411ccc81b1fe19194d3f43b2630cbef3f28Andrew Trick 2202661b411ccc81b1fe19194d3f43b2630cbef3f28Andrew Trick // Table-gen driven ctor. 221dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hines MCSchedModel(unsigned iw, int mbs, int lmbs, unsigned ll, unsigned hl, 222070156437752179833b1e5fddd50caa03fd7c12fAndrew Trick unsigned mp, bool cm, unsigned pi, const MCProcResourceDesc *pr, 223e127dfd0b175b5a336e61fecaad7fc2aec65d95cAndrew Trick const MCSchedClassDesc *sc, unsigned npr, unsigned nsc, 2242661b411ccc81b1fe19194d3f43b2630cbef3f28Andrew Trick const InstrItinerary *ii): 225dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hines IssueWidth(iw), MicroOpBufferSize(mbs), LoopMicroOpBufferSize(lmbs), 226dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hines LoadLatency(ll), HighLatency(hl), 227070156437752179833b1e5fddd50caa03fd7c12fAndrew Trick MispredictPenalty(mp), CompleteModel(cm), ProcID(pi), 228070156437752179833b1e5fddd50caa03fd7c12fAndrew Trick ProcResourceTable(pr), SchedClassTable(sc), NumProcResourceKinds(npr), 229070156437752179833b1e5fddd50caa03fd7c12fAndrew Trick NumSchedClasses(nsc), InstrItineraries(ii) {} 23072d048b69705f01d48bdef7b235ec96b24290767Andrew Trick 23199ab6c6035aec3c0e9b0cc5b76a4666fc5fd7b7bAndrew Trick unsigned getProcessorID() const { return ProcID; } 23299ab6c6035aec3c0e9b0cc5b76a4666fc5fd7b7bAndrew Trick 23372d048b69705f01d48bdef7b235ec96b24290767Andrew Trick /// Does this machine model include instruction-level scheduling. 23439adb180bc2822146618b5bf9059eb7f134914b2Andrew Trick bool hasInstrSchedModel() const { return SchedClassTable; } 23572d048b69705f01d48bdef7b235ec96b24290767Andrew Trick 236070156437752179833b1e5fddd50caa03fd7c12fAndrew Trick /// Return true if this machine model data for all instructions with a 237070156437752179833b1e5fddd50caa03fd7c12fAndrew Trick /// scheduling class (itinerary class or SchedRW list). 238070156437752179833b1e5fddd50caa03fd7c12fAndrew Trick bool isComplete() const { return CompleteModel; } 239070156437752179833b1e5fddd50caa03fd7c12fAndrew Trick 2408d4abb2446f80986ad5136bbec30c5da18cd6f4bAndrew Trick unsigned getNumProcResourceKinds() const { 2418d4abb2446f80986ad5136bbec30c5da18cd6f4bAndrew Trick return NumProcResourceKinds; 2428d4abb2446f80986ad5136bbec30c5da18cd6f4bAndrew Trick } 2438d4abb2446f80986ad5136bbec30c5da18cd6f4bAndrew Trick 24472d048b69705f01d48bdef7b235ec96b24290767Andrew Trick const MCProcResourceDesc *getProcResource(unsigned ProcResourceIdx) const { 24572d048b69705f01d48bdef7b235ec96b24290767Andrew Trick assert(hasInstrSchedModel() && "No scheduling machine model"); 24672d048b69705f01d48bdef7b235ec96b24290767Andrew Trick 24772d048b69705f01d48bdef7b235ec96b24290767Andrew Trick assert(ProcResourceIdx < NumProcResourceKinds && "bad proc resource idx"); 24872d048b69705f01d48bdef7b235ec96b24290767Andrew Trick return &ProcResourceTable[ProcResourceIdx]; 24972d048b69705f01d48bdef7b235ec96b24290767Andrew Trick } 25072d048b69705f01d48bdef7b235ec96b24290767Andrew Trick 25172d048b69705f01d48bdef7b235ec96b24290767Andrew Trick const MCSchedClassDesc *getSchedClassDesc(unsigned SchedClassIdx) const { 25272d048b69705f01d48bdef7b235ec96b24290767Andrew Trick assert(hasInstrSchedModel() && "No scheduling machine model"); 25372d048b69705f01d48bdef7b235ec96b24290767Andrew Trick 25472d048b69705f01d48bdef7b235ec96b24290767Andrew Trick assert(SchedClassIdx < NumSchedClasses && "bad scheduling class idx"); 25572d048b69705f01d48bdef7b235ec96b24290767Andrew Trick return &SchedClassTable[SchedClassIdx]; 25672d048b69705f01d48bdef7b235ec96b24290767Andrew Trick } 2572661b411ccc81b1fe19194d3f43b2630cbef3f28Andrew Trick}; 2582661b411ccc81b1fe19194d3f43b2630cbef3f28Andrew Trick 2592661b411ccc81b1fe19194d3f43b2630cbef3f28Andrew Trick} // End llvm namespace 2602661b411ccc81b1fe19194d3f43b2630cbef3f28Andrew Trick 2612661b411ccc81b1fe19194d3f43b2630cbef3f28Andrew Trick#endif 262