MCSchedule.h revision 070156437752179833b1e5fddd50caa03fd7c12f
1//===-- llvm/MC/MCSchedule.h - Scheduling -----------------------*- C++ -*-===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This file defines the classes used to describe a subtarget's machine model 11// for scheduling and other instruction cost heuristics. 12// 13//===----------------------------------------------------------------------===// 14 15#ifndef LLVM_MC_MCSCHEDULE_H 16#define LLVM_MC_MCSCHEDULE_H 17 18#include "llvm/Support/DataTypes.h" 19#include <cassert> 20 21namespace llvm { 22 23struct InstrItinerary; 24 25/// Define a kind of processor resource that will be modeled by the scheduler. 26struct MCProcResourceDesc { 27#ifndef NDEBUG 28 const char *Name; 29#endif 30 unsigned NumUnits; // Number of resource of this kind 31 unsigned SuperIdx; // Index of the resources kind that contains this kind. 32 33 // Number of resources that may be buffered. 34 // 35 // Buffered resources (BufferSize > 0 || BufferSize == -1) may be consumed at 36 // some indeterminate cycle after dispatch (e.g. for instructions that may 37 // issue out-of-order). Unbuffered resources (BufferSize == 0) always consume 38 // their resource some fixed number of cycles after dispatch (e.g. for 39 // instruction interlocking that may stall the pipeline). 40 int BufferSize; 41 42 bool operator==(const MCProcResourceDesc &Other) const { 43 return NumUnits == Other.NumUnits && SuperIdx == Other.SuperIdx 44 && BufferSize == Other.BufferSize; 45 } 46}; 47 48/// Identify one of the processor resource kinds consumed by a particular 49/// scheduling class for the specified number of cycles. 50struct MCWriteProcResEntry { 51 unsigned ProcResourceIdx; 52 unsigned Cycles; 53 54 bool operator==(const MCWriteProcResEntry &Other) const { 55 return ProcResourceIdx == Other.ProcResourceIdx && Cycles == Other.Cycles; 56 } 57}; 58 59/// Specify the latency in cpu cycles for a particular scheduling class and def 60/// index. -1 indicates an invalid latency. Heuristics would typically consider 61/// an instruction with invalid latency to have infinite latency. Also identify 62/// the WriteResources of this def. When the operand expands to a sequence of 63/// writes, this ID is the last write in the sequence. 64struct MCWriteLatencyEntry { 65 int Cycles; 66 unsigned WriteResourceID; 67 68 bool operator==(const MCWriteLatencyEntry &Other) const { 69 return Cycles == Other.Cycles && WriteResourceID == Other.WriteResourceID; 70 } 71}; 72 73/// Specify the number of cycles allowed after instruction issue before a 74/// particular use operand reads its registers. This effectively reduces the 75/// write's latency. Here we allow negative cycles for corner cases where 76/// latency increases. This rule only applies when the entry's WriteResource 77/// matches the write's WriteResource. 78/// 79/// MCReadAdvanceEntries are sorted first by operand index (UseIdx), then by 80/// WriteResourceIdx. 81struct MCReadAdvanceEntry { 82 unsigned UseIdx; 83 unsigned WriteResourceID; 84 int Cycles; 85 86 bool operator==(const MCReadAdvanceEntry &Other) const { 87 return UseIdx == Other.UseIdx && WriteResourceID == Other.WriteResourceID 88 && Cycles == Other.Cycles; 89 } 90}; 91 92/// Summarize the scheduling resources required for an instruction of a 93/// particular scheduling class. 94/// 95/// Defined as an aggregate struct for creating tables with initializer lists. 96struct MCSchedClassDesc { 97 static const unsigned short InvalidNumMicroOps = UINT16_MAX; 98 static const unsigned short VariantNumMicroOps = UINT16_MAX - 1; 99 100#ifndef NDEBUG 101 const char* Name; 102#endif 103 unsigned short NumMicroOps; 104 bool BeginGroup; 105 bool EndGroup; 106 unsigned WriteProcResIdx; // First index into WriteProcResTable. 107 unsigned NumWriteProcResEntries; 108 unsigned WriteLatencyIdx; // First index into WriteLatencyTable. 109 unsigned NumWriteLatencyEntries; 110 unsigned ReadAdvanceIdx; // First index into ReadAdvanceTable. 111 unsigned NumReadAdvanceEntries; 112 113 bool isValid() const { 114 return NumMicroOps != InvalidNumMicroOps; 115 } 116 bool isVariant() const { 117 return NumMicroOps == VariantNumMicroOps; 118 } 119}; 120 121/// Machine model for scheduling, bundling, and heuristics. 122/// 123/// The machine model directly provides basic information about the 124/// microarchitecture to the scheduler in the form of properties. It also 125/// optionally refers to scheduler resource tables and itinerary 126/// tables. Scheduler resource tables model the latency and cost for each 127/// instruction type. Itinerary tables are an independant mechanism that 128/// provides a detailed reservation table describing each cycle of instruction 129/// execution. Subtargets may define any or all of the above categories of data 130/// depending on the type of CPU and selected scheduler. 131class MCSchedModel { 132public: 133 static MCSchedModel DefaultSchedModel; // For unknown processors. 134 135 // IssueWidth is the maximum number of instructions that may be scheduled in 136 // the same per-cycle group. 137 unsigned IssueWidth; 138 static const unsigned DefaultIssueWidth = 1; 139 140 // MicroOpBufferSize is the number of micro-ops that the processor may buffer 141 // for out-of-order execution. 142 // 143 // "0" means operations that are not ready in this cycle are not considered 144 // for scheduling (they go in the pending queue). Latency is paramount. This 145 // may be more efficient if many instructions are pending in a schedule. 146 // 147 // "1" means all instructions are considered for scheduling regardless of 148 // whether they are ready in this cycle. Latency still causes issue stalls, 149 // but we balance those stalls against other heuristics. 150 // 151 // "> 1" means the processor is out-of-order. This is a machine independent 152 // estimate of highly machine specific characteristics such are the register 153 // renaming pool and reorder buffer. 154 unsigned MicroOpBufferSize; 155 static const unsigned DefaultMicroOpBufferSize = 0; 156 157 // LoadLatency is the expected latency of load instructions. 158 // 159 // If MinLatency >= 0, this may be overriden for individual load opcodes by 160 // InstrItinerary OperandCycles. 161 unsigned LoadLatency; 162 static const unsigned DefaultLoadLatency = 4; 163 164 // HighLatency is the expected latency of "very high latency" operations. 165 // See TargetInstrInfo::isHighLatencyDef(). 166 // By default, this is set to an arbitrarily high number of cycles 167 // likely to have some impact on scheduling heuristics. 168 // If MinLatency >= 0, this may be overriden by InstrItinData OperandCycles. 169 unsigned HighLatency; 170 static const unsigned DefaultHighLatency = 10; 171 172 // MispredictPenalty is the typical number of extra cycles the processor 173 // takes to recover from a branch misprediction. 174 unsigned MispredictPenalty; 175 static const unsigned DefaultMispredictPenalty = 10; 176 177 bool CompleteModel; 178 179private: 180 unsigned ProcID; 181 const MCProcResourceDesc *ProcResourceTable; 182 const MCSchedClassDesc *SchedClassTable; 183 unsigned NumProcResourceKinds; 184 unsigned NumSchedClasses; 185 // Instruction itinerary tables used by InstrItineraryData. 186 friend class InstrItineraryData; 187 const InstrItinerary *InstrItineraries; 188 189public: 190 // Default's must be specified as static const literals so that tablegenerated 191 // target code can use it in static initializers. The defaults need to be 192 // initialized in this default ctor because some clients directly instantiate 193 // MCSchedModel instead of using a generated itinerary. 194 MCSchedModel(): IssueWidth(DefaultIssueWidth), 195 MicroOpBufferSize(DefaultMicroOpBufferSize), 196 LoadLatency(DefaultLoadLatency), 197 HighLatency(DefaultHighLatency), 198 MispredictPenalty(DefaultMispredictPenalty), 199 CompleteModel(true), 200 ProcID(0), ProcResourceTable(0), SchedClassTable(0), 201 NumProcResourceKinds(0), NumSchedClasses(0), 202 InstrItineraries(0) { 203 (void)NumProcResourceKinds; 204 (void)NumSchedClasses; 205 } 206 207 // Table-gen driven ctor. 208 MCSchedModel(unsigned iw, int mbs, unsigned ll, unsigned hl, 209 unsigned mp, bool cm, unsigned pi, const MCProcResourceDesc *pr, 210 const MCSchedClassDesc *sc, unsigned npr, unsigned nsc, 211 const InstrItinerary *ii): 212 IssueWidth(iw), MicroOpBufferSize(mbs), LoadLatency(ll), HighLatency(hl), 213 MispredictPenalty(mp), CompleteModel(cm), ProcID(pi), 214 ProcResourceTable(pr), SchedClassTable(sc), NumProcResourceKinds(npr), 215 NumSchedClasses(nsc), InstrItineraries(ii) {} 216 217 unsigned getProcessorID() const { return ProcID; } 218 219 /// Does this machine model include instruction-level scheduling. 220 bool hasInstrSchedModel() const { return SchedClassTable; } 221 222 /// Return true if this machine model data for all instructions with a 223 /// scheduling class (itinerary class or SchedRW list). 224 bool isComplete() const { return CompleteModel; } 225 226 unsigned getNumProcResourceKinds() const { 227 return NumProcResourceKinds; 228 } 229 230 const MCProcResourceDesc *getProcResource(unsigned ProcResourceIdx) const { 231 assert(hasInstrSchedModel() && "No scheduling machine model"); 232 233 assert(ProcResourceIdx < NumProcResourceKinds && "bad proc resource idx"); 234 return &ProcResourceTable[ProcResourceIdx]; 235 } 236 237 const MCSchedClassDesc *getSchedClassDesc(unsigned SchedClassIdx) const { 238 assert(hasInstrSchedModel() && "No scheduling machine model"); 239 240 assert(SchedClassIdx < NumSchedClasses && "bad scheduling class idx"); 241 return &SchedClassTable[SchedClassIdx]; 242 } 243}; 244 245} // End llvm namespace 246 247#endif 248