MCSchedule.h revision 34301ceca8913f3126339f332d3dc6f2d7ac0d78
1//===-- llvm/MC/MCSchedule.h - Scheduling -----------------------*- C++ -*-===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This file defines the classes used to describe a subtarget's machine model 11// for scheduling and other instruction cost heuristics. 12// 13//===----------------------------------------------------------------------===// 14 15#ifndef LLVM_MC_MCSCHEDMODEL_H 16#define LLVM_MC_MCSCHEDMODEL_H 17 18#include "llvm/Support/DataTypes.h" 19#include <cassert> 20 21namespace llvm { 22 23struct InstrItinerary; 24 25/// Define a kind of processor resource that will be modeled by the scheduler. 26struct MCProcResourceDesc { 27#ifndef NDEBUG 28 const char *Name; 29#endif 30 unsigned Count; // Number of resource of this kind 31 unsigned SuperIdx; // Index of the resources kind that contains this kind. 32 33 bool operator==(const MCProcResourceDesc &Other) const { 34 return Count == Other.Count && SuperIdx == Other.SuperIdx; 35 } 36}; 37 38/// Identify one of the processor resource kinds consumed by a particular 39/// scheduling class for the specified number of cycles. 40struct MCWriteProcResEntry { 41 unsigned ProcResourceIdx; 42 unsigned Cycles; 43 44 bool operator==(const MCWriteProcResEntry &Other) const { 45 return ProcResourceIdx == Other.ProcResourceIdx && Cycles == Other.Cycles; 46 } 47}; 48 49/// Specify the latency in cpu cycles for a particular scheduling class and def 50/// index. Also identify the WriteResources of this def. When the operand 51/// expands to a sequence of writes, this ID is the last write in the sequence. 52struct MCWriteLatencyEntry { 53 unsigned Cycles; 54 unsigned WriteResourceID; 55 56 bool operator==(const MCWriteLatencyEntry &Other) const { 57 return Cycles == Other.Cycles && WriteResourceID == Other.WriteResourceID; 58 } 59}; 60 61/// Specify the number of cycles allowed after instruction issue before a 62/// particular use operand reads its registers. This effectively reduces the 63/// write's latency. Here we allow negative cycles for corner cases where 64/// latency increases. This rule only applies when the entry's WriteResource 65/// matches the write's WriteResource. 66/// 67/// MCReadAdvanceEntries are sorted first by operand index (UseIdx), then by 68/// WriteResourceIdx. 69struct MCReadAdvanceEntry { 70 unsigned UseIdx; 71 unsigned WriteResourceID; 72 int Cycles; 73 74 bool operator==(const MCReadAdvanceEntry &Other) const { 75 return UseIdx == Other.UseIdx && WriteResourceID == Other.WriteResourceID 76 && Cycles == Other.Cycles; 77 } 78}; 79 80/// Summarize the scheduling resources required for an instruction of a 81/// particular scheduling class. 82/// 83/// Defined as an aggregate struct for creating tables with initializer lists. 84struct MCSchedClassDesc { 85 static const unsigned short InvalidNumMicroOps = UINT16_MAX; 86 static const unsigned short VariantNumMicroOps = UINT16_MAX - 1; 87 88#ifndef NDEBUG 89 const char* Name; 90#endif 91 unsigned short NumMicroOps; 92 bool BeginGroup; 93 bool EndGroup; 94 unsigned WriteProcResIdx; // First index into WriteProcResTable. 95 unsigned NumWriteProcResEntries; 96 unsigned WriteLatencyIdx; // First index into WriteLatencyTable. 97 unsigned NumWriteLatencyEntries; 98 unsigned ReadAdvanceIdx; // First index into ReadAdvanceTable. 99 unsigned NumReadAdvanceEntries; 100 101 bool isValid() const { 102 return NumMicroOps != InvalidNumMicroOps; 103 } 104 bool isVariant() const { 105 return NumMicroOps == VariantNumMicroOps; 106 } 107}; 108 109/// Machine model for scheduling, bundling, and heuristics. 110/// 111/// The machine model directly provides basic information about the 112/// microarchitecture to the scheduler in the form of properties. It also 113/// optionally refers to scheduler resource tables and itinerary 114/// tables. Scheduler resource tables model the latency and cost for each 115/// instruction type. Itinerary tables are an independant mechanism that 116/// provides a detailed reservation table describing each cycle of instruction 117/// execution. Subtargets may define any or all of the above categories of data 118/// depending on the type of CPU and selected scheduler. 119class MCSchedModel { 120public: 121 static MCSchedModel DefaultSchedModel; // For unknown processors. 122 123 // IssueWidth is the maximum number of instructions that may be scheduled in 124 // the same per-cycle group. 125 unsigned IssueWidth; 126 static const unsigned DefaultIssueWidth = 1; 127 128 // MinLatency is the minimum latency between a register write 129 // followed by a data dependent read. This determines which 130 // instructions may be scheduled in the same per-cycle group. This 131 // is distinct from *expected* latency, which determines the likely 132 // critical path but does not guarantee a pipeline 133 // hazard. MinLatency can always be overridden by the number of 134 // InstrStage cycles. 135 // 136 // (-1) Standard in-order processor. 137 // Use InstrItinerary OperandCycles as MinLatency. 138 // If no OperandCycles exist, then use the cycle of the last InstrStage. 139 // 140 // (0) Out-of-order processor, or in-order with bundled dependencies. 141 // RAW dependencies may be dispatched in the same cycle. 142 // Optional InstrItinerary OperandCycles provides expected latency. 143 // 144 // (>0) In-order processor with variable latencies. 145 // Use the greater of this value or the cycle of the last InstrStage. 146 // Optional InstrItinerary OperandCycles provides expected latency. 147 // TODO: can't yet specify both min and expected latency per operand. 148 int MinLatency; 149 static const unsigned DefaultMinLatency = -1; 150 151 // LoadLatency is the expected latency of load instructions. 152 // 153 // If MinLatency >= 0, this may be overriden for individual load opcodes by 154 // InstrItinerary OperandCycles. 155 unsigned LoadLatency; 156 static const unsigned DefaultLoadLatency = 4; 157 158 // HighLatency is the expected latency of "very high latency" operations. 159 // See TargetInstrInfo::isHighLatencyDef(). 160 // By default, this is set to an arbitrarily high number of cycles 161 // likely to have some impact on scheduling heuristics. 162 // If MinLatency >= 0, this may be overriden by InstrItinData OperandCycles. 163 unsigned HighLatency; 164 static const unsigned DefaultHighLatency = 10; 165 166 // MispredictPenalty is the typical number of extra cycles the processor 167 // takes to recover from a branch misprediction. 168 unsigned MispredictPenalty; 169 static const unsigned DefaultMispredictPenalty = 10; 170 171private: 172 unsigned ProcID; 173 const MCProcResourceDesc *ProcResourceTable; 174 const MCSchedClassDesc *SchedClassTable; 175 unsigned NumProcResourceKinds; 176 unsigned NumSchedClasses; 177 // Instruction itinerary tables used by InstrItineraryData. 178 friend class InstrItineraryData; 179 const InstrItinerary *InstrItineraries; 180 181public: 182 // Default's must be specified as static const literals so that tablegenerated 183 // target code can use it in static initializers. The defaults need to be 184 // initialized in this default ctor because some clients directly instantiate 185 // MCSchedModel instead of using a generated itinerary. 186 MCSchedModel(): IssueWidth(DefaultIssueWidth), 187 MinLatency(DefaultMinLatency), 188 LoadLatency(DefaultLoadLatency), 189 HighLatency(DefaultHighLatency), 190 MispredictPenalty(DefaultMispredictPenalty), 191 ProcID(0), ProcResourceTable(0), SchedClassTable(0), 192 NumProcResourceKinds(0), NumSchedClasses(0), 193 InstrItineraries(0) { 194 (void)NumProcResourceKinds; 195 (void)NumSchedClasses; 196 } 197 198 // Table-gen driven ctor. 199 MCSchedModel(unsigned iw, int ml, unsigned ll, unsigned hl, unsigned mp, 200 unsigned pi, const MCProcResourceDesc *pr, 201 const MCSchedClassDesc *sc, unsigned npr, unsigned nsc, 202 const InstrItinerary *ii): 203 IssueWidth(iw), MinLatency(ml), LoadLatency(ll), HighLatency(hl), 204 MispredictPenalty(mp), ProcID(pi), ProcResourceTable(pr), 205 SchedClassTable(sc), NumProcResourceKinds(npr), NumSchedClasses(nsc), 206 InstrItineraries(ii) {} 207 208 unsigned getProcessorID() const { return ProcID; } 209 210 /// Does this machine model include instruction-level scheduling. 211 bool hasInstrSchedModel() const { return SchedClassTable != NULL; } 212 213 const MCProcResourceDesc *getProcResource(unsigned ProcResourceIdx) const { 214 assert(hasInstrSchedModel() && "No scheduling machine model"); 215 216 assert(ProcResourceIdx < NumProcResourceKinds && "bad proc resource idx"); 217 return &ProcResourceTable[ProcResourceIdx]; 218 } 219 220 const MCSchedClassDesc *getSchedClassDesc(unsigned SchedClassIdx) const { 221 assert(hasInstrSchedModel() && "No scheduling machine model"); 222 223 assert(SchedClassIdx < NumSchedClasses && "bad scheduling class idx"); 224 return &SchedClassTable[SchedClassIdx]; 225 } 226}; 227 228} // End llvm namespace 229 230#endif 231