MCSchedule.h revision 8d4abb2446f80986ad5136bbec30c5da18cd6f4b
1//===-- llvm/MC/MCSchedule.h - Scheduling -----------------------*- C++ -*-===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This file defines the classes used to describe a subtarget's machine model 11// for scheduling and other instruction cost heuristics. 12// 13//===----------------------------------------------------------------------===// 14 15#ifndef LLVM_MC_MCSCHEDMODEL_H 16#define LLVM_MC_MCSCHEDMODEL_H 17 18#include "llvm/Support/DataTypes.h" 19#include <cassert> 20 21namespace llvm { 22 23struct InstrItinerary; 24 25/// Define a kind of processor resource that will be modeled by the scheduler. 26struct MCProcResourceDesc { 27#ifndef NDEBUG 28 const char *Name; 29#endif 30 unsigned NumUnits; // Number of resource of this kind 31 unsigned SuperIdx; // Index of the resources kind that contains this kind. 32 33 // Buffered resources may be consumed at some indeterminate cycle after 34 // dispatch (e.g. for instructions that may issue out-of-order). Unbuffered 35 // resources always consume their resource some fixed number of cycles after 36 // dispatch (e.g. for instruction interlocking that may stall the pipeline). 37 bool IsBuffered; 38 39 bool operator==(const MCProcResourceDesc &Other) const { 40 return NumUnits == Other.NumUnits && SuperIdx == Other.SuperIdx 41 && IsBuffered == Other.IsBuffered; 42 } 43}; 44 45/// Identify one of the processor resource kinds consumed by a particular 46/// scheduling class for the specified number of cycles. 47struct MCWriteProcResEntry { 48 unsigned ProcResourceIdx; 49 unsigned Cycles; 50 51 bool operator==(const MCWriteProcResEntry &Other) const { 52 return ProcResourceIdx == Other.ProcResourceIdx && Cycles == Other.Cycles; 53 } 54}; 55 56/// Specify the latency in cpu cycles for a particular scheduling class and def 57/// index. -1 indicates an invalid latency. Heuristics would typically consider 58/// an instruction with invalid latency to have infinite latency. Also identify 59/// the WriteResources of this def. When the operand expands to a sequence of 60/// writes, this ID is the last write in the sequence. 61struct MCWriteLatencyEntry { 62 int Cycles; 63 unsigned WriteResourceID; 64 65 bool operator==(const MCWriteLatencyEntry &Other) const { 66 return Cycles == Other.Cycles && WriteResourceID == Other.WriteResourceID; 67 } 68}; 69 70/// Specify the number of cycles allowed after instruction issue before a 71/// particular use operand reads its registers. This effectively reduces the 72/// write's latency. Here we allow negative cycles for corner cases where 73/// latency increases. This rule only applies when the entry's WriteResource 74/// matches the write's WriteResource. 75/// 76/// MCReadAdvanceEntries are sorted first by operand index (UseIdx), then by 77/// WriteResourceIdx. 78struct MCReadAdvanceEntry { 79 unsigned UseIdx; 80 unsigned WriteResourceID; 81 int Cycles; 82 83 bool operator==(const MCReadAdvanceEntry &Other) const { 84 return UseIdx == Other.UseIdx && WriteResourceID == Other.WriteResourceID 85 && Cycles == Other.Cycles; 86 } 87}; 88 89/// Summarize the scheduling resources required for an instruction of a 90/// particular scheduling class. 91/// 92/// Defined as an aggregate struct for creating tables with initializer lists. 93struct MCSchedClassDesc { 94 static const unsigned short InvalidNumMicroOps = UINT16_MAX; 95 static const unsigned short VariantNumMicroOps = UINT16_MAX - 1; 96 97#ifndef NDEBUG 98 const char* Name; 99#endif 100 unsigned short NumMicroOps; 101 bool BeginGroup; 102 bool EndGroup; 103 unsigned WriteProcResIdx; // First index into WriteProcResTable. 104 unsigned NumWriteProcResEntries; 105 unsigned WriteLatencyIdx; // First index into WriteLatencyTable. 106 unsigned NumWriteLatencyEntries; 107 unsigned ReadAdvanceIdx; // First index into ReadAdvanceTable. 108 unsigned NumReadAdvanceEntries; 109 110 bool isValid() const { 111 return NumMicroOps != InvalidNumMicroOps; 112 } 113 bool isVariant() const { 114 return NumMicroOps == VariantNumMicroOps; 115 } 116}; 117 118/// Machine model for scheduling, bundling, and heuristics. 119/// 120/// The machine model directly provides basic information about the 121/// microarchitecture to the scheduler in the form of properties. It also 122/// optionally refers to scheduler resource tables and itinerary 123/// tables. Scheduler resource tables model the latency and cost for each 124/// instruction type. Itinerary tables are an independant mechanism that 125/// provides a detailed reservation table describing each cycle of instruction 126/// execution. Subtargets may define any or all of the above categories of data 127/// depending on the type of CPU and selected scheduler. 128class MCSchedModel { 129public: 130 static MCSchedModel DefaultSchedModel; // For unknown processors. 131 132 // IssueWidth is the maximum number of instructions that may be scheduled in 133 // the same per-cycle group. 134 unsigned IssueWidth; 135 static const unsigned DefaultIssueWidth = 1; 136 137 // MinLatency is the minimum latency between a register write 138 // followed by a data dependent read. This determines which 139 // instructions may be scheduled in the same per-cycle group. This 140 // is distinct from *expected* latency, which determines the likely 141 // critical path but does not guarantee a pipeline 142 // hazard. MinLatency can always be overridden by the number of 143 // InstrStage cycles. 144 // 145 // (-1) Standard in-order processor. 146 // Use InstrItinerary OperandCycles as MinLatency. 147 // If no OperandCycles exist, then use the cycle of the last InstrStage. 148 // 149 // (0) Out-of-order processor, or in-order with bundled dependencies. 150 // RAW dependencies may be dispatched in the same cycle. 151 // Optional InstrItinerary OperandCycles provides expected latency. 152 // 153 // (>0) In-order processor with variable latencies. 154 // Use the greater of this value or the cycle of the last InstrStage. 155 // Optional InstrItinerary OperandCycles provides expected latency. 156 // TODO: can't yet specify both min and expected latency per operand. 157 int MinLatency; 158 static const unsigned DefaultMinLatency = -1; 159 160 // LoadLatency is the expected latency of load instructions. 161 // 162 // If MinLatency >= 0, this may be overriden for individual load opcodes by 163 // InstrItinerary OperandCycles. 164 unsigned LoadLatency; 165 static const unsigned DefaultLoadLatency = 4; 166 167 // HighLatency is the expected latency of "very high latency" operations. 168 // See TargetInstrInfo::isHighLatencyDef(). 169 // By default, this is set to an arbitrarily high number of cycles 170 // likely to have some impact on scheduling heuristics. 171 // If MinLatency >= 0, this may be overriden by InstrItinData OperandCycles. 172 unsigned HighLatency; 173 static const unsigned DefaultHighLatency = 10; 174 175 // MispredictPenalty is the typical number of extra cycles the processor 176 // takes to recover from a branch misprediction. 177 unsigned MispredictPenalty; 178 static const unsigned DefaultMispredictPenalty = 10; 179 180private: 181 unsigned ProcID; 182 const MCProcResourceDesc *ProcResourceTable; 183 const MCSchedClassDesc *SchedClassTable; 184 unsigned NumProcResourceKinds; 185 unsigned NumSchedClasses; 186 // Instruction itinerary tables used by InstrItineraryData. 187 friend class InstrItineraryData; 188 const InstrItinerary *InstrItineraries; 189 190public: 191 // Default's must be specified as static const literals so that tablegenerated 192 // target code can use it in static initializers. The defaults need to be 193 // initialized in this default ctor because some clients directly instantiate 194 // MCSchedModel instead of using a generated itinerary. 195 MCSchedModel(): IssueWidth(DefaultIssueWidth), 196 MinLatency(DefaultMinLatency), 197 LoadLatency(DefaultLoadLatency), 198 HighLatency(DefaultHighLatency), 199 MispredictPenalty(DefaultMispredictPenalty), 200 ProcID(0), ProcResourceTable(0), SchedClassTable(0), 201 NumProcResourceKinds(0), NumSchedClasses(0), 202 InstrItineraries(0) { 203 (void)NumProcResourceKinds; 204 (void)NumSchedClasses; 205 } 206 207 // Table-gen driven ctor. 208 MCSchedModel(unsigned iw, int ml, unsigned ll, unsigned hl, unsigned mp, 209 unsigned pi, const MCProcResourceDesc *pr, 210 const MCSchedClassDesc *sc, unsigned npr, unsigned nsc, 211 const InstrItinerary *ii): 212 IssueWidth(iw), MinLatency(ml), LoadLatency(ll), HighLatency(hl), 213 MispredictPenalty(mp), ProcID(pi), ProcResourceTable(pr), 214 SchedClassTable(sc), NumProcResourceKinds(npr), NumSchedClasses(nsc), 215 InstrItineraries(ii) {} 216 217 unsigned getProcessorID() const { return ProcID; } 218 219 /// Does this machine model include instruction-level scheduling. 220 bool hasInstrSchedModel() const { return SchedClassTable; } 221 222 unsigned getNumProcResourceKinds() const { 223 return NumProcResourceKinds; 224 } 225 226 const MCProcResourceDesc *getProcResource(unsigned ProcResourceIdx) const { 227 assert(hasInstrSchedModel() && "No scheduling machine model"); 228 229 assert(ProcResourceIdx < NumProcResourceKinds && "bad proc resource idx"); 230 return &ProcResourceTable[ProcResourceIdx]; 231 } 232 233 const MCSchedClassDesc *getSchedClassDesc(unsigned SchedClassIdx) const { 234 assert(hasInstrSchedModel() && "No scheduling machine model"); 235 236 assert(SchedClassIdx < NumSchedClasses && "bad scheduling class idx"); 237 return &SchedClassTable[SchedClassIdx]; 238 } 239}; 240 241} // End llvm namespace 242 243#endif 244