MCSchedule.h revision d43b5c97cff06d7840b974ca84fa0639d2567968 
1//===-- llvm/MC/MCSchedule.h - Scheduling -----------------------*- C++ -*-===//
2//
3//                     The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10// This file defines the classes used to describe a subtarget's machine model
11// for scheduling and other instruction cost heuristics.
12//
13//===----------------------------------------------------------------------===//
14
15#ifndef LLVM_MC_MCSCHEDMODEL_H
16#define LLVM_MC_MCSCHEDMODEL_H
17
18#include "llvm/Support/DataTypes.h"
19
20namespace llvm {
21
22struct InstrItinerary;
23
24/// Machine model for scheduling, bundling, and heuristics.
25///
26/// The machine model directly provides basic information about the
27/// microarchitecture to the scheduler in the form of properties. It also
28/// optionally refers to scheduler resources tables and itinerary
29/// tables. Scheduler resources tables model the latency and cost for each
30/// instruction type. Itinerary tables are an independant mechanism that
31/// provides a detailed reservation table describing each cycle of instruction
32/// execution. Subtargets may define any or all of the above categories of data
33/// depending on the type of CPU and selected scheduler.
34class MCSchedModel {
35public:
36  static MCSchedModel DefaultSchedModel; // For unknown processors.
37
38  // IssueWidth is the maximum number of instructions that may be scheduled in
39  // the same per-cycle group.
40  unsigned IssueWidth;
41  static const unsigned DefaultIssueWidth = 1;
42
43  // MinLatency is the minimum latency between a register write
44  // followed by a data dependent read. This determines which
45  // instructions may be scheduled in the same per-cycle group. This
46  // is distinct from *expected* latency, which determines the likely
47  // critical path but does not guarantee a pipeline
48  // hazard. MinLatency can always be overridden by the number of
49  // InstrStage cycles.
50  //
51  // (-1) Standard in-order processor.
52  //      Use InstrItinerary OperandCycles as MinLatency.
53  //      If no OperandCycles exist, then use the cycle of the last InstrStage.
54  //
55  //  (0) Out-of-order processor, or in-order with bundled dependencies.
56  //      RAW dependencies may be dispatched in the same cycle.
57  //      Optional InstrItinerary OperandCycles provides expected latency.
58  //
59  // (>0) In-order processor with variable latencies.
60  //      Use the greater of this value or the cycle of the last InstrStage.
61  //      Optional InstrItinerary OperandCycles provides expected latency.
62  //      TODO: can't yet specify both min and expected latency per operand.
63  int MinLatency;
64  static const unsigned DefaultMinLatency = -1;
65
66  // LoadLatency is the expected latency of load instructions.
67  //
68  // If MinLatency >= 0, this may be overriden for individual load opcodes by
69  // InstrItinerary OperandCycles.
70  unsigned LoadLatency;
71  static const unsigned DefaultLoadLatency = 4;
72
73  // HighLatency is the expected latency of "very high latency" operations.
74  // See TargetInstrInfo::isHighLatencyDef().
75  // By default, this is set to an arbitrarily high number of cycles
76  // likely to have some impact on scheduling heuristics.
77  // If MinLatency >= 0, this may be overriden by InstrItinData OperandCycles.
78  unsigned HighLatency;
79  static const unsigned DefaultHighLatency = 10;
80
81  // MispredictPenalty is the typical number of extra cycles the processor
82  // takes to recover from a branch misprediction.
83  unsigned MispredictPenalty;
84  static const unsigned DefaultMispredictPenalty = 10;
85
86private:
87  // TODO: Add a reference to proc resource types and sched resource tables.
88
89  // Instruction itinerary tables used by InstrItineraryData.
90  friend class InstrItineraryData;
91  const InstrItinerary *InstrItineraries;
92
93public:
94  // Default's must be specified as static const literals so that tablegenerated
95  // target code can use it in static initializers. The defaults need to be
96  // initialized in this default ctor because some clients directly instantiate
97  // MCSchedModel instead of using a generated itinerary.
98  MCSchedModel(): IssueWidth(DefaultIssueWidth),
99                  MinLatency(DefaultMinLatency),
100                  LoadLatency(DefaultLoadLatency),
101                  HighLatency(DefaultHighLatency),
102                  MispredictPenalty(DefaultMispredictPenalty),
103                  InstrItineraries(0) {}
104
105  // Table-gen driven ctor.
106  MCSchedModel(unsigned iw, int ml, unsigned ll, unsigned hl, unsigned mp,
107               const InstrItinerary *ii):
108    IssueWidth(iw), MinLatency(ml), LoadLatency(ll), HighLatency(hl),
109    MispredictPenalty(mp), InstrItineraries(ii){}
110};
111
112} // End llvm namespace
113
114#endif
115