MCSubtargetInfo.h revision 72d048b69705f01d48bdef7b235ec96b24290767 
1//==-- llvm/MC/MCSubtargetInfo.h - Subtarget Information ---------*- C++ -*-==//
2//
3//                     The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10// This file describes the subtarget options of a Target machine.
11//
12//===----------------------------------------------------------------------===//
13
14#ifndef LLVM_MC_MCSUBTARGET_H
15#define LLVM_MC_MCSUBTARGET_H
16
17#include "llvm/MC/SubtargetFeature.h"
18#include "llvm/MC/MCInstrItineraries.h"
19#include <string>
20
21namespace llvm {
22
23class StringRef;
24
25//===----------------------------------------------------------------------===//
26///
27/// MCSubtargetInfo - Generic base class for all target subtargets.
28///
29class MCSubtargetInfo {
30  std::string TargetTriple;            // Target triple
31  const SubtargetFeatureKV *ProcFeatures;  // Processor feature list
32  const SubtargetFeatureKV *ProcDesc;  // Processor descriptions
33
34  // Scheduler machine model
35  const SubtargetInfoKV *ProcSchedModels;
36  const MCWriteProcResEntry *WriteProcResTable;
37  const MCWriteLatencyEntry *WriteLatencyTable;
38  const MCReadAdvanceEntry *ReadAdvanceTable;
39
40  const InstrStage *Stages;            // Instruction itinerary stages
41  const unsigned *OperandCycles;       // Itinerary operand cycles
42  const unsigned *ForwardingPaths;     // Forwarding paths
43  unsigned NumFeatures;                // Number of processor features
44  unsigned NumProcs;                   // Number of processors
45  uint64_t FeatureBits;                // Feature bits for current CPU + FS
46
47public:
48  void InitMCSubtargetInfo(StringRef TT, StringRef CPU, StringRef FS,
49                           const SubtargetFeatureKV *PF,
50                           const SubtargetFeatureKV *PD,
51                           const SubtargetInfoKV *ProcSched,
52                           const InstrStage *IS,
53                           const unsigned *OC, const unsigned *FP,
54                           unsigned NF, unsigned NP);
55
56  /// getTargetTriple - Return the target triple string.
57  StringRef getTargetTriple() const {
58    return TargetTriple;
59  }
60
61  /// getFeatureBits - Return the feature bits.
62  ///
63  uint64_t getFeatureBits() const {
64    return FeatureBits;
65  }
66
67  /// ReInitMCSubtargetInfo - Change CPU (and optionally supplemented with
68  /// feature string), recompute and return feature bits.
69  uint64_t ReInitMCSubtargetInfo(StringRef CPU, StringRef FS);
70
71  /// ToggleFeature - Toggle a feature and returns the re-computed feature
72  /// bits. This version does not change the implied bits.
73  uint64_t ToggleFeature(uint64_t FB);
74
75  /// ToggleFeature - Toggle a feature and returns the re-computed feature
76  /// bits. This version will also change all implied bits.
77  uint64_t ToggleFeature(StringRef FS);
78
79  /// getSchedModelForCPU - Get the machine model of a CPU.
80  ///
81  const MCSchedModel *getSchedModelForCPU(StringRef CPU) const;
82
83  /// Return an iterator at the first process resource consumed by the given
84  /// scheduling class.
85  const MCWriteProcResEntry *getWriteProcResBegin(
86    const MCSchedClassDesc *SC) const {
87    return &WriteProcResTable[SC->WriteProcResIdx];
88  }
89  const MCWriteProcResEntry *getWriteProcResEnd(
90    const MCSchedClassDesc *SC) const {
91    return getWriteProcResBegin(SC) + SC->NumWriteProcResEntries;
92  }
93
94  const MCWriteLatencyEntry *getWriteLatencyEntry(const MCSchedClassDesc *SC,
95                                                  unsigned DefIdx) const {
96    assert(DefIdx < SC->NumWriteLatencyEntries &&
97           "MachineModel does not specify a WriteResource for DefIdx");
98
99    return &WriteLatencyTable[SC->WriteLatencyIdx + DefIdx];
100  }
101
102  int getReadAdvanceCycles(const MCSchedClassDesc *SC, unsigned UseIdx,
103                           unsigned WriteResID) const {
104    for (const MCReadAdvanceEntry *I = &ReadAdvanceTable[SC->ReadAdvanceIdx],
105           *E = I + SC->NumReadAdvanceEntries; I != E; ++I) {
106      if (I->UseIdx < UseIdx)
107        continue;
108      if (I->UseIdx > UseIdx)
109        break;
110      // Find the first WriteResIdx match, which has the highest cycle count.
111      if (!I->WriteResourceID || I->WriteResourceID == WriteResID) {
112        return I->Cycles;
113      }
114    }
115    return 0;
116  }
117
118  /// getInstrItineraryForCPU - Get scheduling itinerary of a CPU.
119  ///
120  InstrItineraryData getInstrItineraryForCPU(StringRef CPU) const;
121};
122
123} // End llvm namespace
124
125#endif
126