MCSubtargetInfo.h revision a2a47d1c50a7acecd729109c334ce3c496f0d549 
1//==-- llvm/MC/MCSubtargetInfo.h - Subtarget Information ---------*- C++ -*-==//
2//
3//                     The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10// This file describes the subtarget options of a Target machine.
11//
12//===----------------------------------------------------------------------===//
13
14#ifndef LLVM_MC_MCSUBTARGET_H
15#define LLVM_MC_MCSUBTARGET_H
16
17#include "llvm/MC/SubtargetFeature.h"
18#include "llvm/MC/MCInstrItineraries.h"
19#include <string>
20
21namespace llvm {
22
23class StringRef;
24
25//===----------------------------------------------------------------------===//
26///
27/// MCSubtargetInfo - Generic base class for all target subtargets.
28///
29class MCSubtargetInfo {
30  std::string TargetTriple;            // Target triple
31  const SubtargetFeatureKV *ProcFeatures;  // Processor feature list
32  const SubtargetFeatureKV *ProcDesc;  // Processor descriptions
33
34  // Scheduler machine model
35  const SubtargetInfoKV *ProcSchedModels;
36  const MCWriteProcResEntry *WriteProcResTable;
37  const MCWriteLatencyEntry *WriteLatencyTable;
38  const MCReadAdvanceEntry *ReadAdvanceTable;
39  const MCSchedModel *CPUSchedModel;
40
41  const InstrStage *Stages;            // Instruction itinerary stages
42  const unsigned *OperandCycles;       // Itinerary operand cycles
43  const unsigned *ForwardingPaths;     // Forwarding paths
44  unsigned NumFeatures;                // Number of processor features
45  unsigned NumProcs;                   // Number of processors
46  uint64_t FeatureBits;                // Feature bits for current CPU + FS
47
48public:
49  void InitMCSubtargetInfo(StringRef TT, StringRef CPU, StringRef FS,
50                           const SubtargetFeatureKV *PF,
51                           const SubtargetFeatureKV *PD,
52                           const SubtargetInfoKV *ProcSched,
53                           const MCWriteProcResEntry *WPR,
54                           const MCWriteLatencyEntry *WL,
55                           const MCReadAdvanceEntry *RA,
56                           const InstrStage *IS,
57                           const unsigned *OC, const unsigned *FP,
58                           unsigned NF, unsigned NP);
59
60  /// getTargetTriple - Return the target triple string.
61  StringRef getTargetTriple() const {
62    return TargetTriple;
63  }
64
65  /// getFeatureBits - Return the feature bits.
66  ///
67  uint64_t getFeatureBits() const {
68    return FeatureBits;
69  }
70
71  /// InitMCProcessorInfo - Set or change the CPU (optionally supplemented with
72  /// feature string). Recompute feature bits and scheduling model.
73  void InitMCProcessorInfo(StringRef CPU, StringRef FS);
74
75  /// ToggleFeature - Toggle a feature and returns the re-computed feature
76  /// bits. This version does not change the implied bits.
77  uint64_t ToggleFeature(uint64_t FB);
78
79  /// ToggleFeature - Toggle a feature and returns the re-computed feature
80  /// bits. This version will also change all implied bits.
81  uint64_t ToggleFeature(StringRef FS);
82
83  /// getSchedModelForCPU - Get the machine model of a CPU.
84  ///
85  const MCSchedModel *getSchedModelForCPU(StringRef CPU) const;
86
87  /// getSchedModel - Get the machine model for this subtarget's CPU.
88  ///
89  const MCSchedModel *getSchedModel() const { return CPUSchedModel; }
90
91  /// Return an iterator at the first process resource consumed by the given
92  /// scheduling class.
93  const MCWriteProcResEntry *getWriteProcResBegin(
94    const MCSchedClassDesc *SC) const {
95    return &WriteProcResTable[SC->WriteProcResIdx];
96  }
97  const MCWriteProcResEntry *getWriteProcResEnd(
98    const MCSchedClassDesc *SC) const {
99    return getWriteProcResBegin(SC) + SC->NumWriteProcResEntries;
100  }
101
102  const MCWriteLatencyEntry *getWriteLatencyEntry(const MCSchedClassDesc *SC,
103                                                  unsigned DefIdx) const {
104    assert(DefIdx < SC->NumWriteLatencyEntries &&
105           "MachineModel does not specify a WriteResource for DefIdx");
106
107    return &WriteLatencyTable[SC->WriteLatencyIdx + DefIdx];
108  }
109
110  int getReadAdvanceCycles(const MCSchedClassDesc *SC, unsigned UseIdx,
111                           unsigned WriteResID) const {
112    for (const MCReadAdvanceEntry *I = &ReadAdvanceTable[SC->ReadAdvanceIdx],
113           *E = I + SC->NumReadAdvanceEntries; I != E; ++I) {
114      if (I->UseIdx < UseIdx)
115        continue;
116      if (I->UseIdx > UseIdx)
117        break;
118      // Find the first WriteResIdx match, which has the highest cycle count.
119      if (!I->WriteResourceID || I->WriteResourceID == WriteResID) {
120        return I->Cycles;
121      }
122    }
123    return 0;
124  }
125
126  /// getInstrItineraryForCPU - Get scheduling itinerary of a CPU.
127  ///
128  InstrItineraryData getInstrItineraryForCPU(StringRef CPU) const;
129
130  /// Initialize an InstrItineraryData instance.
131  void initInstrItins(InstrItineraryData &InstrItins) const;
132};
133
134} // End llvm namespace
135
136#endif
137