Target.td revision 09a2769a7f709baf2d6fa9204e529b2e18aee4dd
154e7afa84d945f9137f9372ecde432f9e1a702fcGreg Clayton//===- Target.td - Target Independent TableGen interface ---*- tablegen -*-===// 254e7afa84d945f9137f9372ecde432f9e1a702fcGreg Clayton// 354e7afa84d945f9137f9372ecde432f9e1a702fcGreg Clayton// The LLVM Compiler Infrastructure 454e7afa84d945f9137f9372ecde432f9e1a702fcGreg Clayton// 554e7afa84d945f9137f9372ecde432f9e1a702fcGreg Clayton// This file is distributed under the University of Illinois Open Source 654e7afa84d945f9137f9372ecde432f9e1a702fcGreg Clayton// License. See LICENSE.TXT for details. 754e7afa84d945f9137f9372ecde432f9e1a702fcGreg Clayton// 854e7afa84d945f9137f9372ecde432f9e1a702fcGreg Clayton//===----------------------------------------------------------------------===// 954e7afa84d945f9137f9372ecde432f9e1a702fcGreg Clayton// 1054e7afa84d945f9137f9372ecde432f9e1a702fcGreg Clayton// This file defines the target-independent interfaces which should be 1154e7afa84d945f9137f9372ecde432f9e1a702fcGreg Clayton// implemented by each target which is using a TableGen based code generator. 1254e7afa84d945f9137f9372ecde432f9e1a702fcGreg Clayton// 1354e7afa84d945f9137f9372ecde432f9e1a702fcGreg Clayton//===----------------------------------------------------------------------===// 1454e7afa84d945f9137f9372ecde432f9e1a702fcGreg Clayton 1554e7afa84d945f9137f9372ecde432f9e1a702fcGreg Clayton// Include all information about LLVM intrinsics. 1654e7afa84d945f9137f9372ecde432f9e1a702fcGreg Claytoninclude "llvm/Intrinsics.td" 17eca14c7b52fdd83705787ca354758d7cd93b8894Peter Collingbourne 1854e7afa84d945f9137f9372ecde432f9e1a702fcGreg Clayton//===----------------------------------------------------------------------===// 19b9db9d5bb01963774f28540dbe2c5a11f586ff29Daniel Malea// Register file description - These classes are used to fill in the target 20b9db9d5bb01963774f28540dbe2c5a11f586ff29Daniel Malea// description classes. 21b9db9d5bb01963774f28540dbe2c5a11f586ff29Daniel Malea 22b9db9d5bb01963774f28540dbe2c5a11f586ff29Daniel Maleaclass RegisterClass; // Forward def 23b9db9d5bb01963774f28540dbe2c5a11f586ff29Daniel Malea 24b9db9d5bb01963774f28540dbe2c5a11f586ff29Daniel Malea// Register - You should define one instance of this class for each register 25b9db9d5bb01963774f28540dbe2c5a11f586ff29Daniel Malea// in the target machine. String n will become the "name" of the register. 264bb4f30fef9281506baf536a254cac17ae68bd73Filipe Cabecinhasclass Register<string n> { 274bb4f30fef9281506baf536a254cac17ae68bd73Filipe Cabecinhas string Namespace = ""; 284bb4f30fef9281506baf536a254cac17ae68bd73Filipe Cabecinhas string AsmName = n; 29f2b0fef6c754acd4f6a3d7cc5cc5f3ad9be98be7Filipe Cabecinhas 30dc3e063595c1b87729242b83baa0ea92a5987704Johnny Chen // SpillSize - If this value is set to a non-zero value, it is the size in 31f2b0fef6c754acd4f6a3d7cc5cc5f3ad9be98be7Filipe Cabecinhas // bits of the spill slot required to hold this register. If this value is 32f2b0fef6c754acd4f6a3d7cc5cc5f3ad9be98be7Filipe Cabecinhas // set to zero, the information is inferred from any register classes the 33f2b0fef6c754acd4f6a3d7cc5cc5f3ad9be98be7Filipe Cabecinhas // register belongs to. 34d4c21f0e25545061dcbaef597531a4796dbe15efCharles Davis int SpillSize = 0; 35f2b0fef6c754acd4f6a3d7cc5cc5f3ad9be98be7Filipe Cabecinhas 36f2b0fef6c754acd4f6a3d7cc5cc5f3ad9be98be7Filipe Cabecinhas // SpillAlignment - This value is used to specify the alignment required for 37d4c21f0e25545061dcbaef597531a4796dbe15efCharles Davis // spilling the register. Like SpillSize, this should only be explicitly 38f2b0fef6c754acd4f6a3d7cc5cc5f3ad9be98be7Filipe Cabecinhas // specified if the register is not in a register class. 39d4c21f0e25545061dcbaef597531a4796dbe15efCharles Davis int SpillAlignment = 0; 40f2b0fef6c754acd4f6a3d7cc5cc5f3ad9be98be7Filipe Cabecinhas 41eca14c7b52fdd83705787ca354758d7cd93b8894Peter Collingbourne // Aliases - A list of registers that this register overlaps with. A read or 42eca14c7b52fdd83705787ca354758d7cd93b8894Peter Collingbourne // modification of this register can potentially read or modify the aliased 43f2b0fef6c754acd4f6a3d7cc5cc5f3ad9be98be7Filipe Cabecinhas // registers. 44 list<Register> Aliases = []; 45 46 // SubRegs - A list of registers that are parts of this register. Note these 47 // are "immediate" sub-registers and the registers within the list do not 48 // themselves overlap. e.g. For X86, EAX's SubRegs list contains only [AX], 49 // not [AX, AH, AL]. 50 list<Register> SubRegs = []; 51 52 // DwarfNumbers - Numbers used internally by gcc/gdb to identify the register. 53 // These values can be determined by locating the <target>.h file in the 54 // directory llvmgcc/gcc/config/<target>/ and looking for REGISTER_NAMES. The 55 // order of these names correspond to the enumeration used by gcc. A value of 56 // -1 indicates that the gcc number is undefined and -2 that register number 57 // is invalid for this mode/flavour. 58 list<int> DwarfNumbers = []; 59} 60 61// RegisterWithSubRegs - This can be used to define instances of Register which 62// need to specify sub-registers. 63// List "subregs" specifies which registers are sub-registers to this one. This 64// is used to populate the SubRegs and AliasSet fields of TargetRegisterDesc. 65// This allows the code generator to be careful not to put two values with 66// overlapping live ranges into registers which alias. 67class RegisterWithSubRegs<string n, list<Register> subregs> : Register<n> { 68 let SubRegs = subregs; 69} 70 71// SubRegSet - This can be used to define a specific mapping of registers to 72// indices, for use as named subregs of a particular physical register. Each 73// register in 'subregs' becomes an addressable subregister at index 'n' of the 74// corresponding register in 'regs'. 75class SubRegSet<int n, list<Register> regs, list<Register> subregs> { 76 int index = n; 77 78 list<Register> From = regs; 79 list<Register> To = subregs; 80} 81 82// RegisterClass - Now that all of the registers are defined, and aliases 83// between registers are defined, specify which registers belong to which 84// register classes. This also defines the default allocation order of 85// registers by register allocators. 86// 87class RegisterClass<string namespace, list<ValueType> regTypes, int alignment, 88 list<Register> regList> { 89 string Namespace = namespace; 90 91 // RegType - Specify the list ValueType of the registers in this register 92 // class. Note that all registers in a register class must have the same 93 // ValueTypes. This is a list because some targets permit storing different 94 // types in same register, for example vector values with 128-bit total size, 95 // but different count/size of items, like SSE on x86. 96 // 97 list<ValueType> RegTypes = regTypes; 98 99 // Size - Specify the spill size in bits of the registers. A default value of 100 // zero lets tablgen pick an appropriate size. 101 int Size = 0; 102 103 // Alignment - Specify the alignment required of the registers when they are 104 // stored or loaded to memory. 105 // 106 int Alignment = alignment; 107 108 // CopyCost - This value is used to specify the cost of copying a value 109 // between two registers in this register class. The default value is one 110 // meaning it takes a single instruction to perform the copying. A negative 111 // value means copying is extremely expensive or impossible. 112 int CopyCost = 1; 113 114 // MemberList - Specify which registers are in this class. If the 115 // allocation_order_* method are not specified, this also defines the order of 116 // allocation used by the register allocator. 117 // 118 list<Register> MemberList = regList; 119 120 // SubClassList - Specify which register classes correspond to subregisters 121 // of this class. The order should be by subregister set index. 122 list<RegisterClass> SubRegClassList = []; 123 124 // MethodProtos/MethodBodies - These members can be used to insert arbitrary 125 // code into a generated register class. The normal usage of this is to 126 // overload virtual methods. 127 code MethodProtos = [{}]; 128 code MethodBodies = [{}]; 129} 130 131 132//===----------------------------------------------------------------------===// 133// DwarfRegNum - This class provides a mapping of the llvm register enumeration 134// to the register numbering used by gcc and gdb. These values are used by a 135// debug information writer (ex. DwarfWriter) to describe where values may be 136// located during execution. 137class DwarfRegNum<list<int> Numbers> { 138 // DwarfNumbers - Numbers used internally by gcc/gdb to identify the register. 139 // These values can be determined by locating the <target>.h file in the 140 // directory llvmgcc/gcc/config/<target>/ and looking for REGISTER_NAMES. The 141 // order of these names correspond to the enumeration used by gcc. A value of 142 // -1 indicates that the gcc number is undefined and -2 that register number is 143 // invalid for this mode/flavour. 144 list<int> DwarfNumbers = Numbers; 145} 146 147//===----------------------------------------------------------------------===// 148// Pull in the common support for scheduling 149// 150include "llvm/Target/TargetSchedule.td" 151 152class Predicate; // Forward def 153 154//===----------------------------------------------------------------------===// 155// Instruction set description - These classes correspond to the C++ classes in 156// the Target/TargetInstrInfo.h file. 157// 158class Instruction { 159 string Namespace = ""; 160 161 dag OutOperandList; // An dag containing the MI def operand list. 162 dag InOperandList; // An dag containing the MI use operand list. 163 string AsmString = ""; // The .s format to print the instruction with. 164 165 // Pattern - Set to the DAG pattern for this instruction, if we know of one, 166 // otherwise, uninitialized. 167 list<dag> Pattern; 168 169 // The follow state will eventually be inferred automatically from the 170 // instruction pattern. 171 172 list<Register> Uses = []; // Default to using no non-operand registers 173 list<Register> Defs = []; // Default to modifying no non-operand registers 174 175 // Predicates - List of predicates which will be turned into isel matching 176 // code. 177 list<Predicate> Predicates = []; 178 179 // Code size. 180 int CodeSize = 0; 181 182 // Added complexity passed onto matching pattern. 183 int AddedComplexity = 0; 184 185 // These bits capture information about the high-level semantics of the 186 // instruction. 187 bit isReturn = 0; // Is this instruction a return instruction? 188 bit isBranch = 0; // Is this instruction a branch instruction? 189 bit isIndirectBranch = 0; // Is this instruction an indirect branch? 190 bit isBarrier = 0; // Can control flow fall through this instruction? 191 bit isCall = 0; // Is this instruction a call instruction? 192 bit canFoldAsLoad = 0; // Can this be folded as a simple memory operand? 193 bit mayLoad = 0; // Is it possible for this inst to read memory? 194 bit mayStore = 0; // Is it possible for this inst to write memory? 195 bit isTwoAddress = 0; // Is this a two address instruction? 196 bit isConvertibleToThreeAddress = 0; // Can this 2-addr instruction promote? 197 bit isCommutable = 0; // Is this 3 operand instruction commutable? 198 bit isTerminator = 0; // Is this part of the terminator for a basic block? 199 bit isReMaterializable = 0; // Is this instruction re-materializable? 200 bit isPredicable = 0; // Is this instruction predicable? 201 bit hasDelaySlot = 0; // Does this instruction have an delay slot? 202 bit usesCustomInserter = 0; // Pseudo instr needing special help. 203 bit hasCtrlDep = 0; // Does this instruction r/w ctrl-flow chains? 204 bit isNotDuplicable = 0; // Is it unsafe to duplicate this instruction? 205 bit isAsCheapAsAMove = 0; // As cheap (or cheaper) than a move instruction. 206 bit hasExtraSrcRegAllocReq = 0; // Sources have special regalloc requirement? 207 bit hasExtraDefRegAllocReq = 0; // Defs have special regalloc requirement? 208 209 // Side effect flags - When set, the flags have these meanings: 210 // 211 // hasSideEffects - The instruction has side effects that are not 212 // captured by any operands of the instruction or other flags. 213 // 214 // neverHasSideEffects - Set on an instruction with no pattern if it has no 215 // side effects. 216 bit hasSideEffects = 0; 217 bit neverHasSideEffects = 0; 218 219 // Is this instruction a "real" instruction (with a distinct machine 220 // encoding), or is it a pseudo instruction used for codegen modeling 221 // purposes. 222 bit isCodeGenOnly = 0; 223 224 InstrItinClass Itinerary = NoItinerary;// Execution steps used for scheduling. 225 226 string Constraints = ""; // OperandConstraint, e.g. $src = $dst. 227 228 /// DisableEncoding - List of operand names (e.g. "$op1,$op2") that should not 229 /// be encoded into the output machineinstr. 230 string DisableEncoding = ""; 231} 232 233/// Predicates - These are extra conditionals which are turned into instruction 234/// selector matching code. Currently each predicate is just a string. 235class Predicate<string cond> { 236 string CondString = cond; 237} 238 239/// NoHonorSignDependentRounding - This predicate is true if support for 240/// sign-dependent-rounding is not enabled. 241def NoHonorSignDependentRounding 242 : Predicate<"!HonorSignDependentRoundingFPMath()">; 243 244class Requires<list<Predicate> preds> { 245 list<Predicate> Predicates = preds; 246} 247 248/// ops definition - This is just a simple marker used to identify the operands 249/// list for an instruction. outs and ins are identical both syntatically and 250/// semantically, they are used to define def operands and use operands to 251/// improve readibility. This should be used like this: 252/// (outs R32:$dst), (ins R32:$src1, R32:$src2) or something similar. 253def ops; 254def outs; 255def ins; 256 257/// variable_ops definition - Mark this instruction as taking a variable number 258/// of operands. 259def variable_ops; 260 261 262/// PointerLikeRegClass - Values that are designed to have pointer width are 263/// derived from this. TableGen treats the register class as having a symbolic 264/// type that it doesn't know, and resolves the actual regclass to use by using 265/// the TargetRegisterInfo::getPointerRegClass() hook at codegen time. 266class PointerLikeRegClass<int Kind> { 267 int RegClassKind = Kind; 268} 269 270 271/// ptr_rc definition - Mark this operand as being a pointer value whose 272/// register class is resolved dynamically via a callback to TargetInstrInfo. 273/// FIXME: We should probably change this to a class which contain a list of 274/// flags. But currently we have but one flag. 275def ptr_rc : PointerLikeRegClass<0>; 276 277/// unknown definition - Mark this operand as being of unknown type, causing 278/// it to be resolved by inference in the context it is used. 279def unknown; 280 281/// AsmOperandClass - Representation for the kinds of operands which the target 282/// specific parser can create and the assembly matcher may need to distinguish. 283/// 284/// Operand classes are used to define the order in which instructions are 285/// matched, to ensure that the instruction which gets matched for any 286/// particular list of operands is deterministic. 287/// 288/// The target specific parser must be able to classify a parsed operand into a 289/// unique class which does not partially overlap with any other classes. It can 290/// match a subset of some other class, in which case the super class field 291/// should be defined. 292class AsmOperandClass { 293 /// The name to use for this class, which should be usable as an enum value. 294 string Name = ?; 295 296 /// The super class of this operand. 297 AsmOperandClass SuperClass = ?; 298 299 /// The name of the method on the target specific operand to call to test 300 /// whether the operand is an instance of this class. If not set, this will 301 /// default to "isFoo", where Foo is the AsmOperandClass name. The method 302 /// signature should be: 303 /// bool isFoo() const; 304 string PredicateMethod = ?; 305 306 /// The name of the method on the target specific operand to call to add the 307 /// target specific operand to an MCInst. If not set, this will default to 308 /// "addFooOperands", where Foo is the AsmOperandClass name. The method 309 /// signature should be: 310 /// void addFooOperands(MCInst &Inst, unsigned N) const; 311 string RenderMethod = ?; 312} 313 314def ImmAsmOperand : AsmOperandClass { 315 let Name = "Imm"; 316} 317 318/// Operand Types - These provide the built-in operand types that may be used 319/// by a target. Targets can optionally provide their own operand types as 320/// needed, though this should not be needed for RISC targets. 321class Operand<ValueType ty> { 322 ValueType Type = ty; 323 string PrintMethod = "printOperand"; 324 string AsmOperandLowerMethod = ?; 325 dag MIOperandInfo = (ops); 326 327 // ParserMatchClass - The "match class" that operands of this type fit 328 // in. Match classes are used to define the order in which instructions are 329 // match, to ensure that which instructions gets matched is deterministic. 330 // 331 // The target specific parser must be able to classify an parsed operand 332 // into a unique class, which does not partially overlap with any other 333 // classes. It can match a subset of some other class, in which case 334 // ParserMatchSuperClass should be set to the name of that class. 335 AsmOperandClass ParserMatchClass = ImmAsmOperand; 336} 337 338def i1imm : Operand<i1>; 339def i8imm : Operand<i8>; 340def i16imm : Operand<i16>; 341def i32imm : Operand<i32>; 342def i64imm : Operand<i64>; 343 344def f32imm : Operand<f32>; 345def f64imm : Operand<f64>; 346 347/// zero_reg definition - Special node to stand for the zero register. 348/// 349def zero_reg; 350 351/// PredicateOperand - This can be used to define a predicate operand for an 352/// instruction. OpTypes specifies the MIOperandInfo for the operand, and 353/// AlwaysVal specifies the value of this predicate when set to "always 354/// execute". 355class PredicateOperand<ValueType ty, dag OpTypes, dag AlwaysVal> 356 : Operand<ty> { 357 let MIOperandInfo = OpTypes; 358 dag DefaultOps = AlwaysVal; 359} 360 361/// OptionalDefOperand - This is used to define a optional definition operand 362/// for an instruction. DefaultOps is the register the operand represents if 363/// none is supplied, e.g. zero_reg. 364class OptionalDefOperand<ValueType ty, dag OpTypes, dag defaultops> 365 : Operand<ty> { 366 let MIOperandInfo = OpTypes; 367 dag DefaultOps = defaultops; 368} 369 370 371// InstrInfo - This class should only be instantiated once to provide parameters 372// which are global to the target machine. 373// 374class InstrInfo { 375 // If the target wants to associate some target-specific information with each 376 // instruction, it should provide these two lists to indicate how to assemble 377 // the target specific information into the 32 bits available. 378 // 379 list<string> TSFlagsFields = []; 380 list<int> TSFlagsShifts = []; 381 382 // Target can specify its instructions in either big or little-endian formats. 383 // For instance, while both Sparc and PowerPC are big-endian platforms, the 384 // Sparc manual specifies its instructions in the format [31..0] (big), while 385 // PowerPC specifies them using the format [0..31] (little). 386 bit isLittleEndianEncoding = 0; 387} 388 389// Standard Pseudo Instructions. 390let isCodeGenOnly = 1 in { 391def PHI : Instruction { 392 let OutOperandList = (outs); 393 let InOperandList = (ins variable_ops); 394 let AsmString = "PHINODE"; 395 let Namespace = "TargetOpcode"; 396} 397def INLINEASM : Instruction { 398 let OutOperandList = (outs); 399 let InOperandList = (ins variable_ops); 400 let AsmString = ""; 401 let Namespace = "TargetOpcode"; 402} 403def DBG_LABEL : Instruction { 404 let OutOperandList = (outs); 405 let InOperandList = (ins i32imm:$id); 406 let AsmString = ""; 407 let Namespace = "TargetOpcode"; 408 let hasCtrlDep = 1; 409 let isNotDuplicable = 1; 410} 411def EH_LABEL : Instruction { 412 let OutOperandList = (outs); 413 let InOperandList = (ins i32imm:$id); 414 let AsmString = ""; 415 let Namespace = "TargetOpcode"; 416 let hasCtrlDep = 1; 417 let isNotDuplicable = 1; 418} 419def GC_LABEL : Instruction { 420 let OutOperandList = (outs); 421 let InOperandList = (ins i32imm:$id); 422 let AsmString = ""; 423 let Namespace = "TargetOpcode"; 424 let hasCtrlDep = 1; 425 let isNotDuplicable = 1; 426} 427def KILL : Instruction { 428 let OutOperandList = (outs); 429 let InOperandList = (ins variable_ops); 430 let AsmString = ""; 431 let Namespace = "TargetOpcode"; 432 let neverHasSideEffects = 1; 433} 434def EXTRACT_SUBREG : Instruction { 435 let OutOperandList = (outs unknown:$dst); 436 let InOperandList = (ins unknown:$supersrc, i32imm:$subidx); 437 let AsmString = ""; 438 let Namespace = "TargetOpcode"; 439 let neverHasSideEffects = 1; 440} 441def INSERT_SUBREG : Instruction { 442 let OutOperandList = (outs unknown:$dst); 443 let InOperandList = (ins unknown:$supersrc, unknown:$subsrc, i32imm:$subidx); 444 let AsmString = ""; 445 let Namespace = "TargetOpcode"; 446 let neverHasSideEffects = 1; 447 let Constraints = "$supersrc = $dst"; 448} 449def IMPLICIT_DEF : Instruction { 450 let OutOperandList = (outs unknown:$dst); 451 let InOperandList = (ins); 452 let AsmString = ""; 453 let Namespace = "TargetOpcode"; 454 let neverHasSideEffects = 1; 455 let isReMaterializable = 1; 456 let isAsCheapAsAMove = 1; 457} 458def SUBREG_TO_REG : Instruction { 459 let OutOperandList = (outs unknown:$dst); 460 let InOperandList = (ins unknown:$implsrc, unknown:$subsrc, i32imm:$subidx); 461 let AsmString = ""; 462 let Namespace = "TargetOpcode"; 463 let neverHasSideEffects = 1; 464} 465def COPY_TO_REGCLASS : Instruction { 466 let OutOperandList = (outs unknown:$dst); 467 let InOperandList = (ins unknown:$src, i32imm:$regclass); 468 let AsmString = ""; 469 let Namespace = "TargetOpcode"; 470 let neverHasSideEffects = 1; 471 let isAsCheapAsAMove = 1; 472} 473def DBG_VALUE : Instruction { 474 let OutOperandList = (outs); 475 let InOperandList = (ins variable_ops); 476 let AsmString = "DBG_VALUE"; 477 let Namespace = "TargetOpcode"; 478 let isAsCheapAsAMove = 1; 479} 480} 481 482//===----------------------------------------------------------------------===// 483// AsmParser - This class can be implemented by targets that wish to implement 484// .s file parsing. 485// 486// Subtargets can have multiple different assembly parsers (e.g. AT&T vs Intel 487// syntax on X86 for example). 488// 489class AsmParser { 490 // AsmParserClassName - This specifies the suffix to use for the asmparser 491 // class. Generated AsmParser classes are always prefixed with the target 492 // name. 493 string AsmParserClassName = "AsmParser"; 494 495 // AsmParserInstCleanup - If non-empty, this is the name of a custom function on the 496 // AsmParser class to call on every matched instruction. This can be used to 497 // perform target specific instruction post-processing. 498 string AsmParserInstCleanup = ""; 499 500 // Variant - AsmParsers can be of multiple different variants. Variants are 501 // used to support targets that need to parser multiple formats for the 502 // assembly language. 503 int Variant = 0; 504 505 // CommentDelimiter - If given, the delimiter string used to recognize 506 // comments which are hard coded in the .td assembler strings for individual 507 // instructions. 508 string CommentDelimiter = ""; 509 510 // RegisterPrefix - If given, the token prefix which indicates a register 511 // token. This is used by the matcher to automatically recognize hard coded 512 // register tokens as constrained registers, instead of tokens, for the 513 // purposes of matching. 514 string RegisterPrefix = ""; 515} 516def DefaultAsmParser : AsmParser; 517 518 519//===----------------------------------------------------------------------===// 520// AsmWriter - This class can be implemented by targets that need to customize 521// the format of the .s file writer. 522// 523// Subtargets can have multiple different asmwriters (e.g. AT&T vs Intel syntax 524// on X86 for example). 525// 526class AsmWriter { 527 // AsmWriterClassName - This specifies the suffix to use for the asmwriter 528 // class. Generated AsmWriter classes are always prefixed with the target 529 // name. 530 string AsmWriterClassName = "AsmPrinter"; 531 532 // InstFormatName - AsmWriters can specify the name of the format string to 533 // print instructions with. 534 string InstFormatName = "AsmString"; 535 536 // Variant - AsmWriters can be of multiple different variants. Variants are 537 // used to support targets that need to emit assembly code in ways that are 538 // mostly the same for different targets, but have minor differences in 539 // syntax. If the asmstring contains {|} characters in them, this integer 540 // will specify which alternative to use. For example "{x|y|z}" with Variant 541 // == 1, will expand to "y". 542 int Variant = 0; 543 544 545 // FirstOperandColumn/OperandSpacing - If the assembler syntax uses a columnar 546 // layout, the asmwriter can actually generate output in this columns (in 547 // verbose-asm mode). These two values indicate the width of the first column 548 // (the "opcode" area) and the width to reserve for subsequent operands. When 549 // verbose asm mode is enabled, operands will be indented to respect this. 550 int FirstOperandColumn = -1; 551 552 // OperandSpacing - Space between operand columns. 553 int OperandSpacing = -1; 554} 555def DefaultAsmWriter : AsmWriter; 556 557 558//===----------------------------------------------------------------------===// 559// Target - This class contains the "global" target information 560// 561class Target { 562 // InstructionSet - Instruction set description for this target. 563 InstrInfo InstructionSet; 564 565 // AssemblyParsers - The AsmParser instances available for this target. 566 list<AsmParser> AssemblyParsers = [DefaultAsmParser]; 567 568 // AssemblyWriters - The AsmWriter instances available for this target. 569 list<AsmWriter> AssemblyWriters = [DefaultAsmWriter]; 570} 571 572//===----------------------------------------------------------------------===// 573// SubtargetFeature - A characteristic of the chip set. 574// 575class SubtargetFeature<string n, string a, string v, string d, 576 list<SubtargetFeature> i = []> { 577 // Name - Feature name. Used by command line (-mattr=) to determine the 578 // appropriate target chip. 579 // 580 string Name = n; 581 582 // Attribute - Attribute to be set by feature. 583 // 584 string Attribute = a; 585 586 // Value - Value the attribute to be set to by feature. 587 // 588 string Value = v; 589 590 // Desc - Feature description. Used by command line (-mattr=) to display help 591 // information. 592 // 593 string Desc = d; 594 595 // Implies - Features that this feature implies are present. If one of those 596 // features isn't set, then this one shouldn't be set either. 597 // 598 list<SubtargetFeature> Implies = i; 599} 600 601//===----------------------------------------------------------------------===// 602// Processor chip sets - These values represent each of the chip sets supported 603// by the scheduler. Each Processor definition requires corresponding 604// instruction itineraries. 605// 606class Processor<string n, ProcessorItineraries pi, list<SubtargetFeature> f> { 607 // Name - Chip set name. Used by command line (-mcpu=) to determine the 608 // appropriate target chip. 609 // 610 string Name = n; 611 612 // ProcItin - The scheduling information for the target processor. 613 // 614 ProcessorItineraries ProcItin = pi; 615 616 // Features - list of 617 list<SubtargetFeature> Features = f; 618} 619 620//===----------------------------------------------------------------------===// 621// Pull in the common support for calling conventions. 622// 623include "llvm/Target/TargetCallingConv.td" 624 625//===----------------------------------------------------------------------===// 626// Pull in the common support for DAG isel generation. 627// 628include "llvm/Target/TargetSelectionDAG.td" 629