Target.td revision 23ed37a6b76e79272194fb46597f7280661b828f
1//===- Target.td - Target Independent TableGen interface ---*- tablegen -*-===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This file defines the target-independent interfaces which should be 11// implemented by each target which is using a TableGen based code generator. 12// 13//===----------------------------------------------------------------------===// 14 15// Include all information about LLVM intrinsics. 16include "llvm/IR/Intrinsics.td" 17 18//===----------------------------------------------------------------------===// 19// Register file description - These classes are used to fill in the target 20// description classes. 21 22class RegisterClass; // Forward def 23 24// SubRegIndex - Use instances of SubRegIndex to identify subregisters. 25class SubRegIndex<int size, int offset = 0> { 26 string Namespace = ""; 27 28 // Size - Size (in bits) of the sub-registers represented by this index. 29 int Size = size; 30 31 // Offset - Offset of the first bit that is part of this sub-register index. 32 // Set it to -1 if the same index is used to represent sub-registers that can 33 // be at different offsets (for example when using an index to access an 34 // element in a register tuple). 35 int Offset = offset; 36 37 // ComposedOf - A list of two SubRegIndex instances, [A, B]. 38 // This indicates that this SubRegIndex is the result of composing A and B. 39 // See ComposedSubRegIndex. 40 list<SubRegIndex> ComposedOf = []; 41 42 // CoveringSubRegIndices - A list of two or more sub-register indexes that 43 // cover this sub-register. 44 // 45 // This field should normally be left blank as TableGen can infer it. 46 // 47 // TableGen automatically detects sub-registers that straddle the registers 48 // in the SubRegs field of a Register definition. For example: 49 // 50 // Q0 = dsub_0 -> D0, dsub_1 -> D1 51 // Q1 = dsub_0 -> D2, dsub_1 -> D3 52 // D1_D2 = dsub_0 -> D1, dsub_1 -> D2 53 // QQ0 = qsub_0 -> Q0, qsub_1 -> Q1 54 // 55 // TableGen will infer that D1_D2 is a sub-register of QQ0. It will be given 56 // the synthetic index dsub_1_dsub_2 unless some SubRegIndex is defined with 57 // CoveringSubRegIndices = [dsub_1, dsub_2]. 58 list<SubRegIndex> CoveringSubRegIndices = []; 59} 60 61// ComposedSubRegIndex - A sub-register that is the result of composing A and B. 62// Offset is set to the sum of A and B's Offsets. Size is set to B's Size. 63class ComposedSubRegIndex<SubRegIndex A, SubRegIndex B> 64 : SubRegIndex<B.Size, !if(!eq(A.Offset, -1), -1, 65 !if(!eq(B.Offset, -1), -1, 66 !add(A.Offset, B.Offset)))> { 67 // See SubRegIndex. 68 let ComposedOf = [A, B]; 69} 70 71// RegAltNameIndex - The alternate name set to use for register operands of 72// this register class when printing. 73class RegAltNameIndex { 74 string Namespace = ""; 75} 76def NoRegAltName : RegAltNameIndex; 77 78// Register - You should define one instance of this class for each register 79// in the target machine. String n will become the "name" of the register. 80class Register<string n, list<string> altNames = []> { 81 string Namespace = ""; 82 string AsmName = n; 83 list<string> AltNames = altNames; 84 85 // Aliases - A list of registers that this register overlaps with. A read or 86 // modification of this register can potentially read or modify the aliased 87 // registers. 88 list<Register> Aliases = []; 89 90 // SubRegs - A list of registers that are parts of this register. Note these 91 // are "immediate" sub-registers and the registers within the list do not 92 // themselves overlap. e.g. For X86, EAX's SubRegs list contains only [AX], 93 // not [AX, AH, AL]. 94 list<Register> SubRegs = []; 95 96 // SubRegIndices - For each register in SubRegs, specify the SubRegIndex used 97 // to address it. Sub-sub-register indices are automatically inherited from 98 // SubRegs. 99 list<SubRegIndex> SubRegIndices = []; 100 101 // RegAltNameIndices - The alternate name indices which are valid for this 102 // register. 103 list<RegAltNameIndex> RegAltNameIndices = []; 104 105 // DwarfNumbers - Numbers used internally by gcc/gdb to identify the register. 106 // These values can be determined by locating the <target>.h file in the 107 // directory llvmgcc/gcc/config/<target>/ and looking for REGISTER_NAMES. The 108 // order of these names correspond to the enumeration used by gcc. A value of 109 // -1 indicates that the gcc number is undefined and -2 that register number 110 // is invalid for this mode/flavour. 111 list<int> DwarfNumbers = []; 112 113 // CostPerUse - Additional cost of instructions using this register compared 114 // to other registers in its class. The register allocator will try to 115 // minimize the number of instructions using a register with a CostPerUse. 116 // This is used by the x86-64 and ARM Thumb targets where some registers 117 // require larger instruction encodings. 118 int CostPerUse = 0; 119 120 // CoveredBySubRegs - When this bit is set, the value of this register is 121 // completely determined by the value of its sub-registers. For example, the 122 // x86 register AX is covered by its sub-registers AL and AH, but EAX is not 123 // covered by its sub-register AX. 124 bit CoveredBySubRegs = 0; 125 126 // HWEncoding - The target specific hardware encoding for this register. 127 bits<16> HWEncoding = 0; 128} 129 130// RegisterWithSubRegs - This can be used to define instances of Register which 131// need to specify sub-registers. 132// List "subregs" specifies which registers are sub-registers to this one. This 133// is used to populate the SubRegs and AliasSet fields of TargetRegisterDesc. 134// This allows the code generator to be careful not to put two values with 135// overlapping live ranges into registers which alias. 136class RegisterWithSubRegs<string n, list<Register> subregs> : Register<n> { 137 let SubRegs = subregs; 138} 139 140// DAGOperand - An empty base class that unifies RegisterClass's and other forms 141// of Operand's that are legal as type qualifiers in DAG patterns. This should 142// only ever be used for defining multiclasses that are polymorphic over both 143// RegisterClass's and other Operand's. 144class DAGOperand { } 145 146// RegisterClass - Now that all of the registers are defined, and aliases 147// between registers are defined, specify which registers belong to which 148// register classes. This also defines the default allocation order of 149// registers by register allocators. 150// 151class RegisterClass<string namespace, list<ValueType> regTypes, int alignment, 152 dag regList, RegAltNameIndex idx = NoRegAltName> 153 : DAGOperand { 154 string Namespace = namespace; 155 156 // RegType - Specify the list ValueType of the registers in this register 157 // class. Note that all registers in a register class must have the same 158 // ValueTypes. This is a list because some targets permit storing different 159 // types in same register, for example vector values with 128-bit total size, 160 // but different count/size of items, like SSE on x86. 161 // 162 list<ValueType> RegTypes = regTypes; 163 164 // Size - Specify the spill size in bits of the registers. A default value of 165 // zero lets tablgen pick an appropriate size. 166 int Size = 0; 167 168 // Alignment - Specify the alignment required of the registers when they are 169 // stored or loaded to memory. 170 // 171 int Alignment = alignment; 172 173 // CopyCost - This value is used to specify the cost of copying a value 174 // between two registers in this register class. The default value is one 175 // meaning it takes a single instruction to perform the copying. A negative 176 // value means copying is extremely expensive or impossible. 177 int CopyCost = 1; 178 179 // MemberList - Specify which registers are in this class. If the 180 // allocation_order_* method are not specified, this also defines the order of 181 // allocation used by the register allocator. 182 // 183 dag MemberList = regList; 184 185 // AltNameIndex - The alternate register name to use when printing operands 186 // of this register class. Every register in the register class must have 187 // a valid alternate name for the given index. 188 RegAltNameIndex altNameIndex = idx; 189 190 // isAllocatable - Specify that the register class can be used for virtual 191 // registers and register allocation. Some register classes are only used to 192 // model instruction operand constraints, and should have isAllocatable = 0. 193 bit isAllocatable = 1; 194 195 // AltOrders - List of alternative allocation orders. The default order is 196 // MemberList itself, and that is good enough for most targets since the 197 // register allocators automatically remove reserved registers and move 198 // callee-saved registers to the end. 199 list<dag> AltOrders = []; 200 201 // AltOrderSelect - The body of a function that selects the allocation order 202 // to use in a given machine function. The code will be inserted in a 203 // function like this: 204 // 205 // static inline unsigned f(const MachineFunction &MF) { ... } 206 // 207 // The function should return 0 to select the default order defined by 208 // MemberList, 1 to select the first AltOrders entry and so on. 209 code AltOrderSelect = [{}]; 210} 211 212// The memberList in a RegisterClass is a dag of set operations. TableGen 213// evaluates these set operations and expand them into register lists. These 214// are the most common operation, see test/TableGen/SetTheory.td for more 215// examples of what is possible: 216// 217// (add R0, R1, R2) - Set Union. Each argument can be an individual register, a 218// register class, or a sub-expression. This is also the way to simply list 219// registers. 220// 221// (sub GPR, SP) - Set difference. Subtract the last arguments from the first. 222// 223// (and GPR, CSR) - Set intersection. All registers from the first set that are 224// also in the second set. 225// 226// (sequence "R%u", 0, 15) -> [R0, R1, ..., R15]. Generate a sequence of 227// numbered registers. Takes an optional 4th operand which is a stride to use 228// when generating the sequence. 229// 230// (shl GPR, 4) - Remove the first N elements. 231// 232// (trunc GPR, 4) - Truncate after the first N elements. 233// 234// (rotl GPR, 1) - Rotate N places to the left. 235// 236// (rotr GPR, 1) - Rotate N places to the right. 237// 238// (decimate GPR, 2) - Pick every N'th element, starting with the first. 239// 240// (interleave A, B, ...) - Interleave the elements from each argument list. 241// 242// All of these operators work on ordered sets, not lists. That means 243// duplicates are removed from sub-expressions. 244 245// Set operators. The rest is defined in TargetSelectionDAG.td. 246def sequence; 247def decimate; 248def interleave; 249 250// RegisterTuples - Automatically generate super-registers by forming tuples of 251// sub-registers. This is useful for modeling register sequence constraints 252// with pseudo-registers that are larger than the architectural registers. 253// 254// The sub-register lists are zipped together: 255// 256// def EvenOdd : RegisterTuples<[sube, subo], [(add R0, R2), (add R1, R3)]>; 257// 258// Generates the same registers as: 259// 260// let SubRegIndices = [sube, subo] in { 261// def R0_R1 : RegisterWithSubRegs<"", [R0, R1]>; 262// def R2_R3 : RegisterWithSubRegs<"", [R2, R3]>; 263// } 264// 265// The generated pseudo-registers inherit super-classes and fields from their 266// first sub-register. Most fields from the Register class are inferred, and 267// the AsmName and Dwarf numbers are cleared. 268// 269// RegisterTuples instances can be used in other set operations to form 270// register classes and so on. This is the only way of using the generated 271// registers. 272class RegisterTuples<list<SubRegIndex> Indices, list<dag> Regs> { 273 // SubRegs - N lists of registers to be zipped up. Super-registers are 274 // synthesized from the first element of each SubRegs list, the second 275 // element and so on. 276 list<dag> SubRegs = Regs; 277 278 // SubRegIndices - N SubRegIndex instances. This provides the names of the 279 // sub-registers in the synthesized super-registers. 280 list<SubRegIndex> SubRegIndices = Indices; 281} 282 283 284//===----------------------------------------------------------------------===// 285// DwarfRegNum - This class provides a mapping of the llvm register enumeration 286// to the register numbering used by gcc and gdb. These values are used by a 287// debug information writer to describe where values may be located during 288// execution. 289class DwarfRegNum<list<int> Numbers> { 290 // DwarfNumbers - Numbers used internally by gcc/gdb to identify the register. 291 // These values can be determined by locating the <target>.h file in the 292 // directory llvmgcc/gcc/config/<target>/ and looking for REGISTER_NAMES. The 293 // order of these names correspond to the enumeration used by gcc. A value of 294 // -1 indicates that the gcc number is undefined and -2 that register number 295 // is invalid for this mode/flavour. 296 list<int> DwarfNumbers = Numbers; 297} 298 299// DwarfRegAlias - This class declares that a given register uses the same dwarf 300// numbers as another one. This is useful for making it clear that the two 301// registers do have the same number. It also lets us build a mapping 302// from dwarf register number to llvm register. 303class DwarfRegAlias<Register reg> { 304 Register DwarfAlias = reg; 305} 306 307//===----------------------------------------------------------------------===// 308// Pull in the common support for scheduling 309// 310include "llvm/Target/TargetSchedule.td" 311 312class Predicate; // Forward def 313 314//===----------------------------------------------------------------------===// 315// Instruction set description - These classes correspond to the C++ classes in 316// the Target/TargetInstrInfo.h file. 317// 318class Instruction { 319 string Namespace = ""; 320 321 dag OutOperandList; // An dag containing the MI def operand list. 322 dag InOperandList; // An dag containing the MI use operand list. 323 string AsmString = ""; // The .s format to print the instruction with. 324 325 // Pattern - Set to the DAG pattern for this instruction, if we know of one, 326 // otherwise, uninitialized. 327 list<dag> Pattern; 328 329 // The follow state will eventually be inferred automatically from the 330 // instruction pattern. 331 332 list<Register> Uses = []; // Default to using no non-operand registers 333 list<Register> Defs = []; // Default to modifying no non-operand registers 334 335 // Predicates - List of predicates which will be turned into isel matching 336 // code. 337 list<Predicate> Predicates = []; 338 339 // Size - Size of encoded instruction, or zero if the size cannot be determined 340 // from the opcode. 341 int Size = 0; 342 343 // DecoderNamespace - The "namespace" in which this instruction exists, on 344 // targets like ARM which multiple ISA namespaces exist. 345 string DecoderNamespace = ""; 346 347 // Code size, for instruction selection. 348 // FIXME: What does this actually mean? 349 int CodeSize = 0; 350 351 // Added complexity passed onto matching pattern. 352 int AddedComplexity = 0; 353 354 // These bits capture information about the high-level semantics of the 355 // instruction. 356 bit isReturn = 0; // Is this instruction a return instruction? 357 bit isBranch = 0; // Is this instruction a branch instruction? 358 bit isIndirectBranch = 0; // Is this instruction an indirect branch? 359 bit isCompare = 0; // Is this instruction a comparison instruction? 360 bit isMoveImm = 0; // Is this instruction a move immediate instruction? 361 bit isBitcast = 0; // Is this instruction a bitcast instruction? 362 bit isSelect = 0; // Is this instruction a select instruction? 363 bit isBarrier = 0; // Can control flow fall through this instruction? 364 bit isCall = 0; // Is this instruction a call instruction? 365 bit canFoldAsLoad = 0; // Can this be folded as a simple memory operand? 366 bit mayLoad = ?; // Is it possible for this inst to read memory? 367 bit mayStore = ?; // Is it possible for this inst to write memory? 368 bit isConvertibleToThreeAddress = 0; // Can this 2-addr instruction promote? 369 bit isCommutable = 0; // Is this 3 operand instruction commutable? 370 bit isTerminator = 0; // Is this part of the terminator for a basic block? 371 bit isReMaterializable = 0; // Is this instruction re-materializable? 372 bit isPredicable = 0; // Is this instruction predicable? 373 bit hasDelaySlot = 0; // Does this instruction have an delay slot? 374 bit usesCustomInserter = 0; // Pseudo instr needing special help. 375 bit hasPostISelHook = 0; // To be *adjusted* after isel by target hook. 376 bit hasCtrlDep = 0; // Does this instruction r/w ctrl-flow chains? 377 bit isNotDuplicable = 0; // Is it unsafe to duplicate this instruction? 378 bit isAsCheapAsAMove = 0; // As cheap (or cheaper) than a move instruction. 379 bit hasExtraSrcRegAllocReq = 0; // Sources have special regalloc requirement? 380 bit hasExtraDefRegAllocReq = 0; // Defs have special regalloc requirement? 381 bit isPseudo = 0; // Is this instruction a pseudo-instruction? 382 // If so, won't have encoding information for 383 // the [MC]CodeEmitter stuff. 384 385 // Side effect flags - When set, the flags have these meanings: 386 // 387 // hasSideEffects - The instruction has side effects that are not 388 // captured by any operands of the instruction or other flags. 389 // 390 // neverHasSideEffects (deprecated) - Set on an instruction with no pattern 391 // if it has no side effects. This is now equivalent to setting 392 // "hasSideEffects = 0". 393 bit hasSideEffects = ?; 394 bit neverHasSideEffects = 0; 395 396 // Is this instruction a "real" instruction (with a distinct machine 397 // encoding), or is it a pseudo instruction used for codegen modeling 398 // purposes. 399 // FIXME: For now this is distinct from isPseudo, above, as code-gen-only 400 // instructions can (and often do) still have encoding information 401 // associated with them. Once we've migrated all of them over to true 402 // pseudo-instructions that are lowered to real instructions prior to 403 // the printer/emitter, we can remove this attribute and just use isPseudo. 404 // 405 // The intended use is: 406 // isPseudo: Does not have encoding information and should be expanded, 407 // at the latest, during lowering to MCInst. 408 // 409 // isCodeGenOnly: Does have encoding information and can go through to the 410 // CodeEmitter unchanged, but duplicates a canonical instruction 411 // definition's encoding and should be ignored when constructing the 412 // assembler match tables. 413 bit isCodeGenOnly = 0; 414 415 // Is this instruction a pseudo instruction for use by the assembler parser. 416 bit isAsmParserOnly = 0; 417 418 InstrItinClass Itinerary = NoItinerary;// Execution steps used for scheduling. 419 420 // Scheduling information from TargetSchedule.td. 421 list<SchedReadWrite> SchedRW; 422 423 string Constraints = ""; // OperandConstraint, e.g. $src = $dst. 424 425 /// DisableEncoding - List of operand names (e.g. "$op1,$op2") that should not 426 /// be encoded into the output machineinstr. 427 string DisableEncoding = ""; 428 429 string PostEncoderMethod = ""; 430 string DecoderMethod = ""; 431 432 /// Target-specific flags. This becomes the TSFlags field in TargetInstrDesc. 433 bits<64> TSFlags = 0; 434 435 ///@name Assembler Parser Support 436 ///@{ 437 438 string AsmMatchConverter = ""; 439 440 /// TwoOperandAliasConstraint - Enable TableGen to auto-generate a 441 /// two-operand matcher inst-alias for a three operand instruction. 442 /// For example, the arm instruction "add r3, r3, r5" can be written 443 /// as "add r3, r5". The constraint is of the same form as a tied-operand 444 /// constraint. For example, "$Rn = $Rd". 445 string TwoOperandAliasConstraint = ""; 446 447 ///@} 448} 449 450/// PseudoInstExpansion - Expansion information for a pseudo-instruction. 451/// Which instruction it expands to and how the operands map from the 452/// pseudo. 453class PseudoInstExpansion<dag Result> { 454 dag ResultInst = Result; // The instruction to generate. 455 bit isPseudo = 1; 456} 457 458/// Predicates - These are extra conditionals which are turned into instruction 459/// selector matching code. Currently each predicate is just a string. 460class Predicate<string cond> { 461 string CondString = cond; 462 463 /// AssemblerMatcherPredicate - If this feature can be used by the assembler 464 /// matcher, this is true. Targets should set this by inheriting their 465 /// feature from the AssemblerPredicate class in addition to Predicate. 466 bit AssemblerMatcherPredicate = 0; 467 468 /// AssemblerCondString - Name of the subtarget feature being tested used 469 /// as alternative condition string used for assembler matcher. 470 /// e.g. "ModeThumb" is translated to "(Bits & ModeThumb) != 0". 471 /// "!ModeThumb" is translated to "(Bits & ModeThumb) == 0". 472 /// It can also list multiple features separated by ",". 473 /// e.g. "ModeThumb,FeatureThumb2" is translated to 474 /// "(Bits & ModeThumb) != 0 && (Bits & FeatureThumb2) != 0". 475 string AssemblerCondString = ""; 476 477 /// PredicateName - User-level name to use for the predicate. Mainly for use 478 /// in diagnostics such as missing feature errors in the asm matcher. 479 string PredicateName = ""; 480} 481 482/// NoHonorSignDependentRounding - This predicate is true if support for 483/// sign-dependent-rounding is not enabled. 484def NoHonorSignDependentRounding 485 : Predicate<"!TM.Options.HonorSignDependentRoundingFPMath()">; 486 487class Requires<list<Predicate> preds> { 488 list<Predicate> Predicates = preds; 489} 490 491/// ops definition - This is just a simple marker used to identify the operand 492/// list for an instruction. outs and ins are identical both syntactically and 493/// semanticallyr; they are used to define def operands and use operands to 494/// improve readibility. This should be used like this: 495/// (outs R32:$dst), (ins R32:$src1, R32:$src2) or something similar. 496def ops; 497def outs; 498def ins; 499 500/// variable_ops definition - Mark this instruction as taking a variable number 501/// of operands. 502def variable_ops; 503 504 505/// PointerLikeRegClass - Values that are designed to have pointer width are 506/// derived from this. TableGen treats the register class as having a symbolic 507/// type that it doesn't know, and resolves the actual regclass to use by using 508/// the TargetRegisterInfo::getPointerRegClass() hook at codegen time. 509class PointerLikeRegClass<int Kind> { 510 int RegClassKind = Kind; 511} 512 513 514/// ptr_rc definition - Mark this operand as being a pointer value whose 515/// register class is resolved dynamically via a callback to TargetInstrInfo. 516/// FIXME: We should probably change this to a class which contain a list of 517/// flags. But currently we have but one flag. 518def ptr_rc : PointerLikeRegClass<0>; 519 520/// unknown definition - Mark this operand as being of unknown type, causing 521/// it to be resolved by inference in the context it is used. 522class unknown_class; 523def unknown : unknown_class; 524 525/// AsmOperandClass - Representation for the kinds of operands which the target 526/// specific parser can create and the assembly matcher may need to distinguish. 527/// 528/// Operand classes are used to define the order in which instructions are 529/// matched, to ensure that the instruction which gets matched for any 530/// particular list of operands is deterministic. 531/// 532/// The target specific parser must be able to classify a parsed operand into a 533/// unique class which does not partially overlap with any other classes. It can 534/// match a subset of some other class, in which case the super class field 535/// should be defined. 536class AsmOperandClass { 537 /// The name to use for this class, which should be usable as an enum value. 538 string Name = ?; 539 540 /// The super classes of this operand. 541 list<AsmOperandClass> SuperClasses = []; 542 543 /// The name of the method on the target specific operand to call to test 544 /// whether the operand is an instance of this class. If not set, this will 545 /// default to "isFoo", where Foo is the AsmOperandClass name. The method 546 /// signature should be: 547 /// bool isFoo() const; 548 string PredicateMethod = ?; 549 550 /// The name of the method on the target specific operand to call to add the 551 /// target specific operand to an MCInst. If not set, this will default to 552 /// "addFooOperands", where Foo is the AsmOperandClass name. The method 553 /// signature should be: 554 /// void addFooOperands(MCInst &Inst, unsigned N) const; 555 string RenderMethod = ?; 556 557 /// The name of the method on the target specific operand to call to custom 558 /// handle the operand parsing. This is useful when the operands do not relate 559 /// to immediates or registers and are very instruction specific (as flags to 560 /// set in a processor register, coprocessor number, ...). 561 string ParserMethod = ?; 562 563 // The diagnostic type to present when referencing this operand in a 564 // match failure error message. By default, use a generic "invalid operand" 565 // diagnostic. The target AsmParser maps these codes to text. 566 string DiagnosticType = ""; 567} 568 569def ImmAsmOperand : AsmOperandClass { 570 let Name = "Imm"; 571} 572 573/// Operand Types - These provide the built-in operand types that may be used 574/// by a target. Targets can optionally provide their own operand types as 575/// needed, though this should not be needed for RISC targets. 576class Operand<ValueType ty> : DAGOperand { 577 ValueType Type = ty; 578 string PrintMethod = "printOperand"; 579 string EncoderMethod = ""; 580 string DecoderMethod = ""; 581 string AsmOperandLowerMethod = ?; 582 string OperandType = "OPERAND_UNKNOWN"; 583 dag MIOperandInfo = (ops); 584 585 // ParserMatchClass - The "match class" that operands of this type fit 586 // in. Match classes are used to define the order in which instructions are 587 // match, to ensure that which instructions gets matched is deterministic. 588 // 589 // The target specific parser must be able to classify an parsed operand into 590 // a unique class, which does not partially overlap with any other classes. It 591 // can match a subset of some other class, in which case the AsmOperandClass 592 // should declare the other operand as one of its super classes. 593 AsmOperandClass ParserMatchClass = ImmAsmOperand; 594} 595 596class RegisterOperand<RegisterClass regclass, string pm = "printOperand"> 597 : DAGOperand { 598 // RegClass - The register class of the operand. 599 RegisterClass RegClass = regclass; 600 // PrintMethod - The target method to call to print register operands of 601 // this type. The method normally will just use an alt-name index to look 602 // up the name to print. Default to the generic printOperand(). 603 string PrintMethod = pm; 604 // ParserMatchClass - The "match class" that operands of this type fit 605 // in. Match classes are used to define the order in which instructions are 606 // match, to ensure that which instructions gets matched is deterministic. 607 // 608 // The target specific parser must be able to classify an parsed operand into 609 // a unique class, which does not partially overlap with any other classes. It 610 // can match a subset of some other class, in which case the AsmOperandClass 611 // should declare the other operand as one of its super classes. 612 AsmOperandClass ParserMatchClass; 613} 614 615let OperandType = "OPERAND_IMMEDIATE" in { 616def i1imm : Operand<i1>; 617def i8imm : Operand<i8>; 618def i16imm : Operand<i16>; 619def i32imm : Operand<i32>; 620def i64imm : Operand<i64>; 621 622def f32imm : Operand<f32>; 623def f64imm : Operand<f64>; 624} 625 626/// zero_reg definition - Special node to stand for the zero register. 627/// 628def zero_reg; 629 630/// OperandWithDefaultOps - This Operand class can be used as the parent class 631/// for an Operand that needs to be initialized with a default value if 632/// no value is supplied in a pattern. This class can be used to simplify the 633/// pattern definitions for instructions that have target specific flags 634/// encoded as immediate operands. 635class OperandWithDefaultOps<ValueType ty, dag defaultops> 636 : Operand<ty> { 637 dag DefaultOps = defaultops; 638} 639 640/// PredicateOperand - This can be used to define a predicate operand for an 641/// instruction. OpTypes specifies the MIOperandInfo for the operand, and 642/// AlwaysVal specifies the value of this predicate when set to "always 643/// execute". 644class PredicateOperand<ValueType ty, dag OpTypes, dag AlwaysVal> 645 : OperandWithDefaultOps<ty, AlwaysVal> { 646 let MIOperandInfo = OpTypes; 647} 648 649/// OptionalDefOperand - This is used to define a optional definition operand 650/// for an instruction. DefaultOps is the register the operand represents if 651/// none is supplied, e.g. zero_reg. 652class OptionalDefOperand<ValueType ty, dag OpTypes, dag defaultops> 653 : OperandWithDefaultOps<ty, defaultops> { 654 let MIOperandInfo = OpTypes; 655} 656 657 658// InstrInfo - This class should only be instantiated once to provide parameters 659// which are global to the target machine. 660// 661class InstrInfo { 662 // Target can specify its instructions in either big or little-endian formats. 663 // For instance, while both Sparc and PowerPC are big-endian platforms, the 664 // Sparc manual specifies its instructions in the format [31..0] (big), while 665 // PowerPC specifies them using the format [0..31] (little). 666 bit isLittleEndianEncoding = 0; 667 668 // The instruction properties mayLoad, mayStore, and hasSideEffects are unset 669 // by default, and TableGen will infer their value from the instruction 670 // pattern when possible. 671 // 672 // Normally, TableGen will issue an error it it can't infer the value of a 673 // property that hasn't been set explicitly. When guessInstructionProperties 674 // is set, it will guess a safe value instead. 675 // 676 // This option is a temporary migration help. It will go away. 677 bit guessInstructionProperties = 1; 678} 679 680// Standard Pseudo Instructions. 681// This list must match TargetOpcodes.h and CodeGenTarget.cpp. 682// Only these instructions are allowed in the TargetOpcode namespace. 683let isCodeGenOnly = 1, isPseudo = 1, Namespace = "TargetOpcode" in { 684def PHI : Instruction { 685 let OutOperandList = (outs); 686 let InOperandList = (ins variable_ops); 687 let AsmString = "PHINODE"; 688} 689def INLINEASM : Instruction { 690 let OutOperandList = (outs); 691 let InOperandList = (ins variable_ops); 692 let AsmString = ""; 693 let neverHasSideEffects = 1; // Note side effect is encoded in an operand. 694} 695def PROLOG_LABEL : Instruction { 696 let OutOperandList = (outs); 697 let InOperandList = (ins i32imm:$id); 698 let AsmString = ""; 699 let hasCtrlDep = 1; 700 let isNotDuplicable = 1; 701} 702def EH_LABEL : Instruction { 703 let OutOperandList = (outs); 704 let InOperandList = (ins i32imm:$id); 705 let AsmString = ""; 706 let hasCtrlDep = 1; 707 let isNotDuplicable = 1; 708} 709def GC_LABEL : Instruction { 710 let OutOperandList = (outs); 711 let InOperandList = (ins i32imm:$id); 712 let AsmString = ""; 713 let hasCtrlDep = 1; 714 let isNotDuplicable = 1; 715} 716def KILL : Instruction { 717 let OutOperandList = (outs); 718 let InOperandList = (ins variable_ops); 719 let AsmString = ""; 720 let neverHasSideEffects = 1; 721} 722def EXTRACT_SUBREG : Instruction { 723 let OutOperandList = (outs unknown:$dst); 724 let InOperandList = (ins unknown:$supersrc, i32imm:$subidx); 725 let AsmString = ""; 726 let neverHasSideEffects = 1; 727} 728def INSERT_SUBREG : Instruction { 729 let OutOperandList = (outs unknown:$dst); 730 let InOperandList = (ins unknown:$supersrc, unknown:$subsrc, i32imm:$subidx); 731 let AsmString = ""; 732 let neverHasSideEffects = 1; 733 let Constraints = "$supersrc = $dst"; 734} 735def IMPLICIT_DEF : Instruction { 736 let OutOperandList = (outs unknown:$dst); 737 let InOperandList = (ins); 738 let AsmString = ""; 739 let neverHasSideEffects = 1; 740 let isReMaterializable = 1; 741 let isAsCheapAsAMove = 1; 742} 743def SUBREG_TO_REG : Instruction { 744 let OutOperandList = (outs unknown:$dst); 745 let InOperandList = (ins unknown:$implsrc, unknown:$subsrc, i32imm:$subidx); 746 let AsmString = ""; 747 let neverHasSideEffects = 1; 748} 749def COPY_TO_REGCLASS : Instruction { 750 let OutOperandList = (outs unknown:$dst); 751 let InOperandList = (ins unknown:$src, i32imm:$regclass); 752 let AsmString = ""; 753 let neverHasSideEffects = 1; 754 let isAsCheapAsAMove = 1; 755} 756def DBG_VALUE : Instruction { 757 let OutOperandList = (outs); 758 let InOperandList = (ins variable_ops); 759 let AsmString = "DBG_VALUE"; 760 let neverHasSideEffects = 1; 761} 762def REG_SEQUENCE : Instruction { 763 let OutOperandList = (outs unknown:$dst); 764 let InOperandList = (ins variable_ops); 765 let AsmString = ""; 766 let neverHasSideEffects = 1; 767 let isAsCheapAsAMove = 1; 768} 769def COPY : Instruction { 770 let OutOperandList = (outs unknown:$dst); 771 let InOperandList = (ins unknown:$src); 772 let AsmString = ""; 773 let neverHasSideEffects = 1; 774 let isAsCheapAsAMove = 1; 775} 776def BUNDLE : Instruction { 777 let OutOperandList = (outs); 778 let InOperandList = (ins variable_ops); 779 let AsmString = "BUNDLE"; 780} 781def LIFETIME_START : Instruction { 782 let OutOperandList = (outs); 783 let InOperandList = (ins i32imm:$id); 784 let AsmString = "LIFETIME_START"; 785 let neverHasSideEffects = 1; 786} 787def LIFETIME_END : Instruction { 788 let OutOperandList = (outs); 789 let InOperandList = (ins i32imm:$id); 790 let AsmString = "LIFETIME_END"; 791 let neverHasSideEffects = 1; 792} 793} 794 795//===----------------------------------------------------------------------===// 796// AsmParser - This class can be implemented by targets that wish to implement 797// .s file parsing. 798// 799// Subtargets can have multiple different assembly parsers (e.g. AT&T vs Intel 800// syntax on X86 for example). 801// 802class AsmParser { 803 // AsmParserClassName - This specifies the suffix to use for the asmparser 804 // class. Generated AsmParser classes are always prefixed with the target 805 // name. 806 string AsmParserClassName = "AsmParser"; 807 808 // AsmParserInstCleanup - If non-empty, this is the name of a custom member 809 // function of the AsmParser class to call on every matched instruction. 810 // This can be used to perform target specific instruction post-processing. 811 string AsmParserInstCleanup = ""; 812 813 // ShouldEmitMatchRegisterName - Set to false if the target needs a hand 814 // written register name matcher 815 bit ShouldEmitMatchRegisterName = 1; 816} 817def DefaultAsmParser : AsmParser; 818 819//===----------------------------------------------------------------------===// 820// AsmParserVariant - Subtargets can have multiple different assembly parsers 821// (e.g. AT&T vs Intel syntax on X86 for example). This class can be 822// implemented by targets to describe such variants. 823// 824class AsmParserVariant { 825 // Variant - AsmParsers can be of multiple different variants. Variants are 826 // used to support targets that need to parser multiple formats for the 827 // assembly language. 828 int Variant = 0; 829 830 // Name - The AsmParser variant name (e.g., AT&T vs Intel). 831 string Name = ""; 832 833 // CommentDelimiter - If given, the delimiter string used to recognize 834 // comments which are hard coded in the .td assembler strings for individual 835 // instructions. 836 string CommentDelimiter = ""; 837 838 // RegisterPrefix - If given, the token prefix which indicates a register 839 // token. This is used by the matcher to automatically recognize hard coded 840 // register tokens as constrained registers, instead of tokens, for the 841 // purposes of matching. 842 string RegisterPrefix = ""; 843} 844def DefaultAsmParserVariant : AsmParserVariant; 845 846/// AssemblerPredicate - This is a Predicate that can be used when the assembler 847/// matches instructions and aliases. 848class AssemblerPredicate<string cond, string name = ""> { 849 bit AssemblerMatcherPredicate = 1; 850 string AssemblerCondString = cond; 851 string PredicateName = name; 852} 853 854/// TokenAlias - This class allows targets to define assembler token 855/// operand aliases. That is, a token literal operand which is equivalent 856/// to another, canonical, token literal. For example, ARM allows: 857/// vmov.u32 s4, #0 -> vmov.i32, #0 858/// 'u32' is a more specific designator for the 32-bit integer type specifier 859/// and is legal for any instruction which accepts 'i32' as a datatype suffix. 860/// def : TokenAlias<".u32", ".i32">; 861/// 862/// This works by marking the match class of 'From' as a subclass of the 863/// match class of 'To'. 864class TokenAlias<string From, string To> { 865 string FromToken = From; 866 string ToToken = To; 867} 868 869/// MnemonicAlias - This class allows targets to define assembler mnemonic 870/// aliases. This should be used when all forms of one mnemonic are accepted 871/// with a different mnemonic. For example, X86 allows: 872/// sal %al, 1 -> shl %al, 1 873/// sal %ax, %cl -> shl %ax, %cl 874/// sal %eax, %cl -> shl %eax, %cl 875/// etc. Though "sal" is accepted with many forms, all of them are directly 876/// translated to a shl, so it can be handled with (in the case of X86, it 877/// actually has one for each suffix as well): 878/// def : MnemonicAlias<"sal", "shl">; 879/// 880/// Mnemonic aliases are mapped before any other translation in the match phase, 881/// and do allow Requires predicates, e.g.: 882/// 883/// def : MnemonicAlias<"pushf", "pushfq">, Requires<[In64BitMode]>; 884/// def : MnemonicAlias<"pushf", "pushfl">, Requires<[In32BitMode]>; 885/// 886/// Mnemonic aliases can also be constrained to specific variants, e.g.: 887/// 888/// def : MnemonicAlias<"pushf", "pushfq", "att">, Requires<[In64BitMode]>; 889/// 890/// If no variant (e.g., "att" or "intel") is specified then the alias is 891/// applied unconditionally. 892class MnemonicAlias<string From, string To, string VariantName = ""> { 893 string FromMnemonic = From; 894 string ToMnemonic = To; 895 string AsmVariantName = VariantName; 896 897 // Predicates - Predicates that must be true for this remapping to happen. 898 list<Predicate> Predicates = []; 899} 900 901/// InstAlias - This defines an alternate assembly syntax that is allowed to 902/// match an instruction that has a different (more canonical) assembly 903/// representation. 904class InstAlias<string Asm, dag Result, bit Emit = 0b1> { 905 string AsmString = Asm; // The .s format to match the instruction with. 906 dag ResultInst = Result; // The MCInst to generate. 907 bit EmitAlias = Emit; // Emit the alias instead of what's aliased. 908 909 // Predicates - Predicates that must be true for this to match. 910 list<Predicate> Predicates = []; 911} 912 913//===----------------------------------------------------------------------===// 914// AsmWriter - This class can be implemented by targets that need to customize 915// the format of the .s file writer. 916// 917// Subtargets can have multiple different asmwriters (e.g. AT&T vs Intel syntax 918// on X86 for example). 919// 920class AsmWriter { 921 // AsmWriterClassName - This specifies the suffix to use for the asmwriter 922 // class. Generated AsmWriter classes are always prefixed with the target 923 // name. 924 string AsmWriterClassName = "AsmPrinter"; 925 926 // Variant - AsmWriters can be of multiple different variants. Variants are 927 // used to support targets that need to emit assembly code in ways that are 928 // mostly the same for different targets, but have minor differences in 929 // syntax. If the asmstring contains {|} characters in them, this integer 930 // will specify which alternative to use. For example "{x|y|z}" with Variant 931 // == 1, will expand to "y". 932 int Variant = 0; 933 934 935 // FirstOperandColumn/OperandSpacing - If the assembler syntax uses a columnar 936 // layout, the asmwriter can actually generate output in this columns (in 937 // verbose-asm mode). These two values indicate the width of the first column 938 // (the "opcode" area) and the width to reserve for subsequent operands. When 939 // verbose asm mode is enabled, operands will be indented to respect this. 940 int FirstOperandColumn = -1; 941 942 // OperandSpacing - Space between operand columns. 943 int OperandSpacing = -1; 944 945 // isMCAsmWriter - Is this assembly writer for an MC emitter? This controls 946 // generation of the printInstruction() method. For MC printers, it takes 947 // an MCInstr* operand, otherwise it takes a MachineInstr*. 948 bit isMCAsmWriter = 0; 949} 950def DefaultAsmWriter : AsmWriter; 951 952 953//===----------------------------------------------------------------------===// 954// Target - This class contains the "global" target information 955// 956class Target { 957 // InstructionSet - Instruction set description for this target. 958 InstrInfo InstructionSet; 959 960 // AssemblyParsers - The AsmParser instances available for this target. 961 list<AsmParser> AssemblyParsers = [DefaultAsmParser]; 962 963 /// AssemblyParserVariants - The AsmParserVariant instances available for 964 /// this target. 965 list<AsmParserVariant> AssemblyParserVariants = [DefaultAsmParserVariant]; 966 967 // AssemblyWriters - The AsmWriter instances available for this target. 968 list<AsmWriter> AssemblyWriters = [DefaultAsmWriter]; 969} 970 971//===----------------------------------------------------------------------===// 972// SubtargetFeature - A characteristic of the chip set. 973// 974class SubtargetFeature<string n, string a, string v, string d, 975 list<SubtargetFeature> i = []> { 976 // Name - Feature name. Used by command line (-mattr=) to determine the 977 // appropriate target chip. 978 // 979 string Name = n; 980 981 // Attribute - Attribute to be set by feature. 982 // 983 string Attribute = a; 984 985 // Value - Value the attribute to be set to by feature. 986 // 987 string Value = v; 988 989 // Desc - Feature description. Used by command line (-mattr=) to display help 990 // information. 991 // 992 string Desc = d; 993 994 // Implies - Features that this feature implies are present. If one of those 995 // features isn't set, then this one shouldn't be set either. 996 // 997 list<SubtargetFeature> Implies = i; 998} 999 1000//===----------------------------------------------------------------------===// 1001// Processor chip sets - These values represent each of the chip sets supported 1002// by the scheduler. Each Processor definition requires corresponding 1003// instruction itineraries. 1004// 1005class Processor<string n, ProcessorItineraries pi, list<SubtargetFeature> f> { 1006 // Name - Chip set name. Used by command line (-mcpu=) to determine the 1007 // appropriate target chip. 1008 // 1009 string Name = n; 1010 1011 // SchedModel - The machine model for scheduling and instruction cost. 1012 // 1013 SchedMachineModel SchedModel = NoSchedModel; 1014 1015 // ProcItin - The scheduling information for the target processor. 1016 // 1017 ProcessorItineraries ProcItin = pi; 1018 1019 // Features - list of 1020 list<SubtargetFeature> Features = f; 1021} 1022 1023// ProcessorModel allows subtargets to specify the more general 1024// SchedMachineModel instead if a ProcessorItinerary. Subtargets will 1025// gradually move to this newer form. 1026// 1027// Although this class always passes NoItineraries to the Processor 1028// class, the SchedMachineModel may still define valid Itineraries. 1029class ProcessorModel<string n, SchedMachineModel m, list<SubtargetFeature> f> 1030 : Processor<n, NoItineraries, f> { 1031 let SchedModel = m; 1032} 1033 1034//===----------------------------------------------------------------------===// 1035// InstrMapping - This class is used to create mapping tables to relate 1036// instructions with each other based on the values specified in RowFields, 1037// ColFields, KeyCol and ValueCols. 1038// 1039class InstrMapping { 1040 // FilterClass - Used to limit search space only to the instructions that 1041 // define the relationship modeled by this InstrMapping record. 1042 string FilterClass; 1043 1044 // RowFields - List of fields/attributes that should be same for all the 1045 // instructions in a row of the relation table. Think of this as a set of 1046 // properties shared by all the instructions related by this relationship 1047 // model and is used to categorize instructions into subgroups. For instance, 1048 // if we want to define a relation that maps 'Add' instruction to its 1049 // predicated forms, we can define RowFields like this: 1050 // 1051 // let RowFields = BaseOp 1052 // All add instruction predicated/non-predicated will have to set their BaseOp 1053 // to the same value. 1054 // 1055 // def Add: { let BaseOp = 'ADD'; let predSense = 'nopred' } 1056 // def Add_predtrue: { let BaseOp = 'ADD'; let predSense = 'true' } 1057 // def Add_predfalse: { let BaseOp = 'ADD'; let predSense = 'false' } 1058 list<string> RowFields = []; 1059 1060 // List of fields/attributes that are same for all the instructions 1061 // in a column of the relation table. 1062 // Ex: let ColFields = 'predSense' -- It means that the columns are arranged 1063 // based on the 'predSense' values. All the instruction in a specific 1064 // column have the same value and it is fixed for the column according 1065 // to the values set in 'ValueCols'. 1066 list<string> ColFields = []; 1067 1068 // Values for the fields/attributes listed in 'ColFields'. 1069 // Ex: let KeyCol = 'nopred' -- It means that the key instruction (instruction 1070 // that models this relation) should be non-predicated. 1071 // In the example above, 'Add' is the key instruction. 1072 list<string> KeyCol = []; 1073 1074 // List of values for the fields/attributes listed in 'ColFields', one for 1075 // each column in the relation table. 1076 // 1077 // Ex: let ValueCols = [['true'],['false']] -- It adds two columns in the 1078 // table. First column requires all the instructions to have predSense 1079 // set to 'true' and second column requires it to be 'false'. 1080 list<list<string> > ValueCols = []; 1081} 1082 1083//===----------------------------------------------------------------------===// 1084// Pull in the common support for calling conventions. 1085// 1086include "llvm/Target/TargetCallingConv.td" 1087 1088//===----------------------------------------------------------------------===// 1089// Pull in the common support for DAG isel generation. 1090// 1091include "llvm/Target/TargetSelectionDAG.td" 1092