Target.td revision 2efd8acb3cc6ceb0ca32610389a53909896f99e5
1//===- Target.td - Target Independent TableGen interface ---*- tablegen -*-===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This file defines the target-independent interfaces which should be 11// implemented by each target which is using a TableGen based code generator. 12// 13//===----------------------------------------------------------------------===// 14 15// Include all information about LLVM intrinsics. 16include "llvm/Intrinsics.td" 17 18//===----------------------------------------------------------------------===// 19// Register file description - These classes are used to fill in the target 20// description classes. 21 22class RegisterClass; // Forward def 23 24// SubRegIndex - Use instances of SubRegIndex to identify subregisters. 25class SubRegIndex<list<SubRegIndex> comps = []> { 26 string Namespace = ""; 27 28 // ComposedOf - A list of two SubRegIndex instances, [A, B]. 29 // This indicates that this SubRegIndex is the result of composing A and B. 30 list<SubRegIndex> ComposedOf = comps; 31} 32 33// RegAltNameIndex - The alternate name set to use for register operands of 34// this register class when printing. 35class RegAltNameIndex { 36 string Namespace = ""; 37} 38def NoRegAltName : RegAltNameIndex; 39 40// Register - You should define one instance of this class for each register 41// in the target machine. String n will become the "name" of the register. 42class Register<string n, list<string> altNames = []> { 43 string Namespace = ""; 44 string AsmName = n; 45 list<string> AltNames = altNames; 46 47 // Aliases - A list of registers that this register overlaps with. A read or 48 // modification of this register can potentially read or modify the aliased 49 // registers. 50 list<Register> Aliases = []; 51 52 // SubRegs - A list of registers that are parts of this register. Note these 53 // are "immediate" sub-registers and the registers within the list do not 54 // themselves overlap. e.g. For X86, EAX's SubRegs list contains only [AX], 55 // not [AX, AH, AL]. 56 list<Register> SubRegs = []; 57 58 // SubRegIndices - For each register in SubRegs, specify the SubRegIndex used 59 // to address it. Sub-sub-register indices are automatically inherited from 60 // SubRegs. 61 list<SubRegIndex> SubRegIndices = []; 62 63 // RegAltNameIndices - The alternate name indices which are valid for this 64 // register. 65 list<RegAltNameIndex> RegAltNameIndices = []; 66 67 // CompositeIndices - Specify subreg indices that don't correspond directly to 68 // a register in SubRegs and are not inherited. The following formats are 69 // supported: 70 // 71 // (a) Identity - Reg:a == Reg 72 // (a b) Alias - Reg:a == Reg:b 73 // (a b,c) Composite - Reg:a == (Reg:b):c 74 // 75 // This can be used to disambiguate a sub-sub-register that exists in more 76 // than one subregister and other weird stuff. 77 list<dag> CompositeIndices = []; 78 79 // DwarfNumbers - Numbers used internally by gcc/gdb to identify the register. 80 // These values can be determined by locating the <target>.h file in the 81 // directory llvmgcc/gcc/config/<target>/ and looking for REGISTER_NAMES. The 82 // order of these names correspond to the enumeration used by gcc. A value of 83 // -1 indicates that the gcc number is undefined and -2 that register number 84 // is invalid for this mode/flavour. 85 list<int> DwarfNumbers = []; 86 87 // CostPerUse - Additional cost of instructions using this register compared 88 // to other registers in its class. The register allocator will try to 89 // minimize the number of instructions using a register with a CostPerUse. 90 // This is used by the x86-64 and ARM Thumb targets where some registers 91 // require larger instruction encodings. 92 int CostPerUse = 0; 93 94 // CoveredBySubRegs - When this bit is set, the value of this register is 95 // completely determined by the value of its sub-registers. For example, the 96 // x86 register AX is covered by its sub-registers AL and AH, but EAX is not 97 // covered by its sub-register AX. 98 bit CoveredBySubRegs = 0; 99} 100 101// RegisterWithSubRegs - This can be used to define instances of Register which 102// need to specify sub-registers. 103// List "subregs" specifies which registers are sub-registers to this one. This 104// is used to populate the SubRegs and AliasSet fields of TargetRegisterDesc. 105// This allows the code generator to be careful not to put two values with 106// overlapping live ranges into registers which alias. 107class RegisterWithSubRegs<string n, list<Register> subregs> : Register<n> { 108 let SubRegs = subregs; 109} 110 111// RegisterClass - Now that all of the registers are defined, and aliases 112// between registers are defined, specify which registers belong to which 113// register classes. This also defines the default allocation order of 114// registers by register allocators. 115// 116class RegisterClass<string namespace, list<ValueType> regTypes, int alignment, 117 dag regList, RegAltNameIndex idx = NoRegAltName> { 118 string Namespace = namespace; 119 120 // RegType - Specify the list ValueType of the registers in this register 121 // class. Note that all registers in a register class must have the same 122 // ValueTypes. This is a list because some targets permit storing different 123 // types in same register, for example vector values with 128-bit total size, 124 // but different count/size of items, like SSE on x86. 125 // 126 list<ValueType> RegTypes = regTypes; 127 128 // Size - Specify the spill size in bits of the registers. A default value of 129 // zero lets tablgen pick an appropriate size. 130 int Size = 0; 131 132 // Alignment - Specify the alignment required of the registers when they are 133 // stored or loaded to memory. 134 // 135 int Alignment = alignment; 136 137 // CopyCost - This value is used to specify the cost of copying a value 138 // between two registers in this register class. The default value is one 139 // meaning it takes a single instruction to perform the copying. A negative 140 // value means copying is extremely expensive or impossible. 141 int CopyCost = 1; 142 143 // MemberList - Specify which registers are in this class. If the 144 // allocation_order_* method are not specified, this also defines the order of 145 // allocation used by the register allocator. 146 // 147 dag MemberList = regList; 148 149 // AltNameIndex - The alternate register name to use when printing operands 150 // of this register class. Every register in the register class must have 151 // a valid alternate name for the given index. 152 RegAltNameIndex altNameIndex = idx; 153 154 // SubRegClasses - Specify the register class of subregisters as a list of 155 // dags: (RegClass SubRegIndex, SubRegindex, ...) 156 list<dag> SubRegClasses = []; 157 158 // isAllocatable - Specify that the register class can be used for virtual 159 // registers and register allocation. Some register classes are only used to 160 // model instruction operand constraints, and should have isAllocatable = 0. 161 bit isAllocatable = 1; 162 163 // AltOrders - List of alternative allocation orders. The default order is 164 // MemberList itself, and that is good enough for most targets since the 165 // register allocators automatically remove reserved registers and move 166 // callee-saved registers to the end. 167 list<dag> AltOrders = []; 168 169 // AltOrderSelect - The body of a function that selects the allocation order 170 // to use in a given machine function. The code will be inserted in a 171 // function like this: 172 // 173 // static inline unsigned f(const MachineFunction &MF) { ... } 174 // 175 // The function should return 0 to select the default order defined by 176 // MemberList, 1 to select the first AltOrders entry and so on. 177 code AltOrderSelect = [{}]; 178} 179 180// The memberList in a RegisterClass is a dag of set operations. TableGen 181// evaluates these set operations and expand them into register lists. These 182// are the most common operation, see test/TableGen/SetTheory.td for more 183// examples of what is possible: 184// 185// (add R0, R1, R2) - Set Union. Each argument can be an individual register, a 186// register class, or a sub-expression. This is also the way to simply list 187// registers. 188// 189// (sub GPR, SP) - Set difference. Subtract the last arguments from the first. 190// 191// (and GPR, CSR) - Set intersection. All registers from the first set that are 192// also in the second set. 193// 194// (sequence "R%u", 0, 15) -> [R0, R1, ..., R15]. Generate a sequence of 195// numbered registers. 196// 197// (shl GPR, 4) - Remove the first N elements. 198// 199// (trunc GPR, 4) - Truncate after the first N elements. 200// 201// (rotl GPR, 1) - Rotate N places to the left. 202// 203// (rotr GPR, 1) - Rotate N places to the right. 204// 205// (decimate GPR, 2) - Pick every N'th element, starting with the first. 206// 207// (interleave A, B, ...) - Interleave the elements from each argument list. 208// 209// All of these operators work on ordered sets, not lists. That means 210// duplicates are removed from sub-expressions. 211 212// Set operators. The rest is defined in TargetSelectionDAG.td. 213def sequence; 214def decimate; 215def interleave; 216 217// RegisterTuples - Automatically generate super-registers by forming tuples of 218// sub-registers. This is useful for modeling register sequence constraints 219// with pseudo-registers that are larger than the architectural registers. 220// 221// The sub-register lists are zipped together: 222// 223// def EvenOdd : RegisterTuples<[sube, subo], [(add R0, R2), (add R1, R3)]>; 224// 225// Generates the same registers as: 226// 227// let SubRegIndices = [sube, subo] in { 228// def R0_R1 : RegisterWithSubRegs<"", [R0, R1]>; 229// def R2_R3 : RegisterWithSubRegs<"", [R2, R3]>; 230// } 231// 232// The generated pseudo-registers inherit super-classes and fields from their 233// first sub-register. Most fields from the Register class are inferred, and 234// the AsmName and Dwarf numbers are cleared. 235// 236// RegisterTuples instances can be used in other set operations to form 237// register classes and so on. This is the only way of using the generated 238// registers. 239class RegisterTuples<list<SubRegIndex> Indices, list<dag> Regs> { 240 // SubRegs - N lists of registers to be zipped up. Super-registers are 241 // synthesized from the first element of each SubRegs list, the second 242 // element and so on. 243 list<dag> SubRegs = Regs; 244 245 // SubRegIndices - N SubRegIndex instances. This provides the names of the 246 // sub-registers in the synthesized super-registers. 247 list<SubRegIndex> SubRegIndices = Indices; 248 249 // Compose sub-register indices like in a normal Register. 250 list<dag> CompositeIndices = []; 251} 252 253 254//===----------------------------------------------------------------------===// 255// DwarfRegNum - This class provides a mapping of the llvm register enumeration 256// to the register numbering used by gcc and gdb. These values are used by a 257// debug information writer to describe where values may be located during 258// execution. 259class DwarfRegNum<list<int> Numbers> { 260 // DwarfNumbers - Numbers used internally by gcc/gdb to identify the register. 261 // These values can be determined by locating the <target>.h file in the 262 // directory llvmgcc/gcc/config/<target>/ and looking for REGISTER_NAMES. The 263 // order of these names correspond to the enumeration used by gcc. A value of 264 // -1 indicates that the gcc number is undefined and -2 that register number 265 // is invalid for this mode/flavour. 266 list<int> DwarfNumbers = Numbers; 267} 268 269// DwarfRegAlias - This class declares that a given register uses the same dwarf 270// numbers as another one. This is useful for making it clear that the two 271// registers do have the same number. It also lets us build a mapping 272// from dwarf register number to llvm register. 273class DwarfRegAlias<Register reg> { 274 Register DwarfAlias = reg; 275} 276 277//===----------------------------------------------------------------------===// 278// Pull in the common support for scheduling 279// 280include "llvm/Target/TargetSchedule.td" 281 282class Predicate; // Forward def 283 284//===----------------------------------------------------------------------===// 285// Instruction set description - These classes correspond to the C++ classes in 286// the Target/TargetInstrInfo.h file. 287// 288class Instruction { 289 string Namespace = ""; 290 291 dag OutOperandList; // An dag containing the MI def operand list. 292 dag InOperandList; // An dag containing the MI use operand list. 293 string AsmString = ""; // The .s format to print the instruction with. 294 295 // Pattern - Set to the DAG pattern for this instruction, if we know of one, 296 // otherwise, uninitialized. 297 list<dag> Pattern; 298 299 // The follow state will eventually be inferred automatically from the 300 // instruction pattern. 301 302 list<Register> Uses = []; // Default to using no non-operand registers 303 list<Register> Defs = []; // Default to modifying no non-operand registers 304 305 // Predicates - List of predicates which will be turned into isel matching 306 // code. 307 list<Predicate> Predicates = []; 308 309 // Size - Size of encoded instruction, or zero if the size cannot be determined 310 // from the opcode. 311 int Size = 0; 312 313 // DecoderNamespace - The "namespace" in which this instruction exists, on 314 // targets like ARM which multiple ISA namespaces exist. 315 string DecoderNamespace = ""; 316 317 // Code size, for instruction selection. 318 // FIXME: What does this actually mean? 319 int CodeSize = 0; 320 321 // Added complexity passed onto matching pattern. 322 int AddedComplexity = 0; 323 324 // These bits capture information about the high-level semantics of the 325 // instruction. 326 bit isReturn = 0; // Is this instruction a return instruction? 327 bit isBranch = 0; // Is this instruction a branch instruction? 328 bit isIndirectBranch = 0; // Is this instruction an indirect branch? 329 bit isCompare = 0; // Is this instruction a comparison instruction? 330 bit isMoveImm = 0; // Is this instruction a move immediate instruction? 331 bit isBitcast = 0; // Is this instruction a bitcast instruction? 332 bit isBarrier = 0; // Can control flow fall through this instruction? 333 bit isCall = 0; // Is this instruction a call instruction? 334 bit canFoldAsLoad = 0; // Can this be folded as a simple memory operand? 335 bit mayLoad = 0; // Is it possible for this inst to read memory? 336 bit mayStore = 0; // Is it possible for this inst to write memory? 337 bit isConvertibleToThreeAddress = 0; // Can this 2-addr instruction promote? 338 bit isCommutable = 0; // Is this 3 operand instruction commutable? 339 bit isTerminator = 0; // Is this part of the terminator for a basic block? 340 bit isReMaterializable = 0; // Is this instruction re-materializable? 341 bit isPredicable = 0; // Is this instruction predicable? 342 bit hasDelaySlot = 0; // Does this instruction have an delay slot? 343 bit usesCustomInserter = 0; // Pseudo instr needing special help. 344 bit hasPostISelHook = 0; // To be *adjusted* after isel by target hook. 345 bit hasCtrlDep = 0; // Does this instruction r/w ctrl-flow chains? 346 bit isNotDuplicable = 0; // Is it unsafe to duplicate this instruction? 347 bit isAsCheapAsAMove = 0; // As cheap (or cheaper) than a move instruction. 348 bit hasExtraSrcRegAllocReq = 0; // Sources have special regalloc requirement? 349 bit hasExtraDefRegAllocReq = 0; // Defs have special regalloc requirement? 350 bit isPseudo = 0; // Is this instruction a pseudo-instruction? 351 // If so, won't have encoding information for 352 // the [MC]CodeEmitter stuff. 353 354 // Side effect flags - When set, the flags have these meanings: 355 // 356 // hasSideEffects - The instruction has side effects that are not 357 // captured by any operands of the instruction or other flags. 358 // 359 // neverHasSideEffects - Set on an instruction with no pattern if it has no 360 // side effects. 361 bit hasSideEffects = 0; 362 bit neverHasSideEffects = 0; 363 364 // Is this instruction a "real" instruction (with a distinct machine 365 // encoding), or is it a pseudo instruction used for codegen modeling 366 // purposes. 367 // FIXME: For now this is distinct from isPseudo, above, as code-gen-only 368 // instructions can (and often do) still have encoding information 369 // associated with them. Once we've migrated all of them over to true 370 // pseudo-instructions that are lowered to real instructions prior to 371 // the printer/emitter, we can remove this attribute and just use isPseudo. 372 // 373 // The intended use is: 374 // isPseudo: Does not have encoding information and should be expanded, 375 // at the latest, during lowering to MCInst. 376 // 377 // isCodeGenOnly: Does have encoding information and can go through to the 378 // CodeEmitter unchanged, but duplicates a canonical instruction 379 // definition's encoding and should be ignored when constructing the 380 // assembler match tables. 381 bit isCodeGenOnly = 0; 382 383 // Is this instruction a pseudo instruction for use by the assembler parser. 384 bit isAsmParserOnly = 0; 385 386 InstrItinClass Itinerary = NoItinerary;// Execution steps used for scheduling. 387 388 string Constraints = ""; // OperandConstraint, e.g. $src = $dst. 389 390 /// DisableEncoding - List of operand names (e.g. "$op1,$op2") that should not 391 /// be encoded into the output machineinstr. 392 string DisableEncoding = ""; 393 394 string PostEncoderMethod = ""; 395 string DecoderMethod = ""; 396 397 /// Target-specific flags. This becomes the TSFlags field in TargetInstrDesc. 398 bits<64> TSFlags = 0; 399 400 ///@name Assembler Parser Support 401 ///@{ 402 403 string AsmMatchConverter = ""; 404 405 /// TwoOperandAliasConstraint - Enable TableGen to auto-generate a 406 /// two-operand matcher inst-alias for a three operand instruction. 407 /// For example, the arm instruction "add r3, r3, r5" can be written 408 /// as "add r3, r5". The constraint is of the same form as a tied-operand 409 /// constraint. For example, "$Rn = $Rd". 410 string TwoOperandAliasConstraint = ""; 411 412 ///@} 413} 414 415/// PseudoInstExpansion - Expansion information for a pseudo-instruction. 416/// Which instruction it expands to and how the operands map from the 417/// pseudo. 418class PseudoInstExpansion<dag Result> { 419 dag ResultInst = Result; // The instruction to generate. 420 bit isPseudo = 1; 421} 422 423/// Predicates - These are extra conditionals which are turned into instruction 424/// selector matching code. Currently each predicate is just a string. 425class Predicate<string cond> { 426 string CondString = cond; 427 428 /// AssemblerMatcherPredicate - If this feature can be used by the assembler 429 /// matcher, this is true. Targets should set this by inheriting their 430 /// feature from the AssemblerPredicate class in addition to Predicate. 431 bit AssemblerMatcherPredicate = 0; 432 433 /// AssemblerCondString - Name of the subtarget feature being tested used 434 /// as alternative condition string used for assembler matcher. 435 /// e.g. "ModeThumb" is translated to "(Bits & ModeThumb) != 0". 436 /// "!ModeThumb" is translated to "(Bits & ModeThumb) == 0". 437 /// It can also list multiple features separated by ",". 438 /// e.g. "ModeThumb,FeatureThumb2" is translated to 439 /// "(Bits & ModeThumb) != 0 && (Bits & FeatureThumb2) != 0". 440 string AssemblerCondString = ""; 441} 442 443/// NoHonorSignDependentRounding - This predicate is true if support for 444/// sign-dependent-rounding is not enabled. 445def NoHonorSignDependentRounding 446 : Predicate<"!TM.Options.HonorSignDependentRoundingFPMath()">; 447 448class Requires<list<Predicate> preds> { 449 list<Predicate> Predicates = preds; 450} 451 452/// ops definition - This is just a simple marker used to identify the operand 453/// list for an instruction. outs and ins are identical both syntactically and 454/// semanticallyr; they are used to define def operands and use operands to 455/// improve readibility. This should be used like this: 456/// (outs R32:$dst), (ins R32:$src1, R32:$src2) or something similar. 457def ops; 458def outs; 459def ins; 460 461/// variable_ops definition - Mark this instruction as taking a variable number 462/// of operands. 463def variable_ops; 464 465 466/// PointerLikeRegClass - Values that are designed to have pointer width are 467/// derived from this. TableGen treats the register class as having a symbolic 468/// type that it doesn't know, and resolves the actual regclass to use by using 469/// the TargetRegisterInfo::getPointerRegClass() hook at codegen time. 470class PointerLikeRegClass<int Kind> { 471 int RegClassKind = Kind; 472} 473 474 475/// ptr_rc definition - Mark this operand as being a pointer value whose 476/// register class is resolved dynamically via a callback to TargetInstrInfo. 477/// FIXME: We should probably change this to a class which contain a list of 478/// flags. But currently we have but one flag. 479def ptr_rc : PointerLikeRegClass<0>; 480 481/// unknown definition - Mark this operand as being of unknown type, causing 482/// it to be resolved by inference in the context it is used. 483def unknown; 484 485/// AsmOperandClass - Representation for the kinds of operands which the target 486/// specific parser can create and the assembly matcher may need to distinguish. 487/// 488/// Operand classes are used to define the order in which instructions are 489/// matched, to ensure that the instruction which gets matched for any 490/// particular list of operands is deterministic. 491/// 492/// The target specific parser must be able to classify a parsed operand into a 493/// unique class which does not partially overlap with any other classes. It can 494/// match a subset of some other class, in which case the super class field 495/// should be defined. 496class AsmOperandClass { 497 /// The name to use for this class, which should be usable as an enum value. 498 string Name = ?; 499 500 /// The super classes of this operand. 501 list<AsmOperandClass> SuperClasses = []; 502 503 /// The name of the method on the target specific operand to call to test 504 /// whether the operand is an instance of this class. If not set, this will 505 /// default to "isFoo", where Foo is the AsmOperandClass name. The method 506 /// signature should be: 507 /// bool isFoo() const; 508 string PredicateMethod = ?; 509 510 /// The name of the method on the target specific operand to call to add the 511 /// target specific operand to an MCInst. If not set, this will default to 512 /// "addFooOperands", where Foo is the AsmOperandClass name. The method 513 /// signature should be: 514 /// void addFooOperands(MCInst &Inst, unsigned N) const; 515 string RenderMethod = ?; 516 517 /// The name of the method on the target specific operand to call to custom 518 /// handle the operand parsing. This is useful when the operands do not relate 519 /// to immediates or registers and are very instruction specific (as flags to 520 /// set in a processor register, coprocessor number, ...). 521 string ParserMethod = ?; 522} 523 524def ImmAsmOperand : AsmOperandClass { 525 let Name = "Imm"; 526} 527 528/// Operand Types - These provide the built-in operand types that may be used 529/// by a target. Targets can optionally provide their own operand types as 530/// needed, though this should not be needed for RISC targets. 531class Operand<ValueType ty> { 532 ValueType Type = ty; 533 string PrintMethod = "printOperand"; 534 string EncoderMethod = ""; 535 string DecoderMethod = ""; 536 string AsmOperandLowerMethod = ?; 537 string OperandType = "OPERAND_UNKNOWN"; 538 dag MIOperandInfo = (ops); 539 540 // ParserMatchClass - The "match class" that operands of this type fit 541 // in. Match classes are used to define the order in which instructions are 542 // match, to ensure that which instructions gets matched is deterministic. 543 // 544 // The target specific parser must be able to classify an parsed operand into 545 // a unique class, which does not partially overlap with any other classes. It 546 // can match a subset of some other class, in which case the AsmOperandClass 547 // should declare the other operand as one of its super classes. 548 AsmOperandClass ParserMatchClass = ImmAsmOperand; 549} 550 551class RegisterOperand<RegisterClass regclass, string pm = "printOperand"> { 552 // RegClass - The register class of the operand. 553 RegisterClass RegClass = regclass; 554 // PrintMethod - The target method to call to print register operands of 555 // this type. The method normally will just use an alt-name index to look 556 // up the name to print. Default to the generic printOperand(). 557 string PrintMethod = pm; 558 // ParserMatchClass - The "match class" that operands of this type fit 559 // in. Match classes are used to define the order in which instructions are 560 // match, to ensure that which instructions gets matched is deterministic. 561 // 562 // The target specific parser must be able to classify an parsed operand into 563 // a unique class, which does not partially overlap with any other classes. It 564 // can match a subset of some other class, in which case the AsmOperandClass 565 // should declare the other operand as one of its super classes. 566 AsmOperandClass ParserMatchClass; 567} 568 569let OperandType = "OPERAND_IMMEDIATE" in { 570def i1imm : Operand<i1>; 571def i8imm : Operand<i8>; 572def i16imm : Operand<i16>; 573def i32imm : Operand<i32>; 574def i64imm : Operand<i64>; 575 576def f32imm : Operand<f32>; 577def f64imm : Operand<f64>; 578} 579 580/// zero_reg definition - Special node to stand for the zero register. 581/// 582def zero_reg; 583 584/// PredicateOperand - This can be used to define a predicate operand for an 585/// instruction. OpTypes specifies the MIOperandInfo for the operand, and 586/// AlwaysVal specifies the value of this predicate when set to "always 587/// execute". 588class PredicateOperand<ValueType ty, dag OpTypes, dag AlwaysVal> 589 : Operand<ty> { 590 let MIOperandInfo = OpTypes; 591 dag DefaultOps = AlwaysVal; 592} 593 594/// OptionalDefOperand - This is used to define a optional definition operand 595/// for an instruction. DefaultOps is the register the operand represents if 596/// none is supplied, e.g. zero_reg. 597class OptionalDefOperand<ValueType ty, dag OpTypes, dag defaultops> 598 : Operand<ty> { 599 let MIOperandInfo = OpTypes; 600 dag DefaultOps = defaultops; 601} 602 603 604// InstrInfo - This class should only be instantiated once to provide parameters 605// which are global to the target machine. 606// 607class InstrInfo { 608 // Target can specify its instructions in either big or little-endian formats. 609 // For instance, while both Sparc and PowerPC are big-endian platforms, the 610 // Sparc manual specifies its instructions in the format [31..0] (big), while 611 // PowerPC specifies them using the format [0..31] (little). 612 bit isLittleEndianEncoding = 0; 613} 614 615// Standard Pseudo Instructions. 616// This list must match TargetOpcodes.h and CodeGenTarget.cpp. 617// Only these instructions are allowed in the TargetOpcode namespace. 618let isCodeGenOnly = 1, isPseudo = 1, Namespace = "TargetOpcode" in { 619def PHI : Instruction { 620 let OutOperandList = (outs); 621 let InOperandList = (ins variable_ops); 622 let AsmString = "PHINODE"; 623} 624def INLINEASM : Instruction { 625 let OutOperandList = (outs); 626 let InOperandList = (ins variable_ops); 627 let AsmString = ""; 628 let neverHasSideEffects = 1; // Note side effect is encoded in an operand. 629} 630def PROLOG_LABEL : Instruction { 631 let OutOperandList = (outs); 632 let InOperandList = (ins i32imm:$id); 633 let AsmString = ""; 634 let hasCtrlDep = 1; 635 let isNotDuplicable = 1; 636} 637def EH_LABEL : Instruction { 638 let OutOperandList = (outs); 639 let InOperandList = (ins i32imm:$id); 640 let AsmString = ""; 641 let hasCtrlDep = 1; 642 let isNotDuplicable = 1; 643} 644def GC_LABEL : Instruction { 645 let OutOperandList = (outs); 646 let InOperandList = (ins i32imm:$id); 647 let AsmString = ""; 648 let hasCtrlDep = 1; 649 let isNotDuplicable = 1; 650} 651def KILL : Instruction { 652 let OutOperandList = (outs); 653 let InOperandList = (ins variable_ops); 654 let AsmString = ""; 655 let neverHasSideEffects = 1; 656} 657def EXTRACT_SUBREG : Instruction { 658 let OutOperandList = (outs unknown:$dst); 659 let InOperandList = (ins unknown:$supersrc, i32imm:$subidx); 660 let AsmString = ""; 661 let neverHasSideEffects = 1; 662} 663def INSERT_SUBREG : Instruction { 664 let OutOperandList = (outs unknown:$dst); 665 let InOperandList = (ins unknown:$supersrc, unknown:$subsrc, i32imm:$subidx); 666 let AsmString = ""; 667 let neverHasSideEffects = 1; 668 let Constraints = "$supersrc = $dst"; 669} 670def IMPLICIT_DEF : Instruction { 671 let OutOperandList = (outs unknown:$dst); 672 let InOperandList = (ins); 673 let AsmString = ""; 674 let neverHasSideEffects = 1; 675 let isReMaterializable = 1; 676 let isAsCheapAsAMove = 1; 677} 678def SUBREG_TO_REG : Instruction { 679 let OutOperandList = (outs unknown:$dst); 680 let InOperandList = (ins unknown:$implsrc, unknown:$subsrc, i32imm:$subidx); 681 let AsmString = ""; 682 let neverHasSideEffects = 1; 683} 684def COPY_TO_REGCLASS : Instruction { 685 let OutOperandList = (outs unknown:$dst); 686 let InOperandList = (ins unknown:$src, i32imm:$regclass); 687 let AsmString = ""; 688 let neverHasSideEffects = 1; 689 let isAsCheapAsAMove = 1; 690} 691def DBG_VALUE : Instruction { 692 let OutOperandList = (outs); 693 let InOperandList = (ins variable_ops); 694 let AsmString = "DBG_VALUE"; 695 let neverHasSideEffects = 1; 696} 697def REG_SEQUENCE : Instruction { 698 let OutOperandList = (outs unknown:$dst); 699 let InOperandList = (ins variable_ops); 700 let AsmString = ""; 701 let neverHasSideEffects = 1; 702 let isAsCheapAsAMove = 1; 703} 704def COPY : Instruction { 705 let OutOperandList = (outs unknown:$dst); 706 let InOperandList = (ins unknown:$src); 707 let AsmString = ""; 708 let neverHasSideEffects = 1; 709 let isAsCheapAsAMove = 1; 710} 711def BUNDLE : Instruction { 712 let OutOperandList = (outs); 713 let InOperandList = (ins variable_ops); 714 let AsmString = "BUNDLE"; 715} 716} 717 718//===----------------------------------------------------------------------===// 719// AsmParser - This class can be implemented by targets that wish to implement 720// .s file parsing. 721// 722// Subtargets can have multiple different assembly parsers (e.g. AT&T vs Intel 723// syntax on X86 for example). 724// 725class AsmParser { 726 // AsmParserClassName - This specifies the suffix to use for the asmparser 727 // class. Generated AsmParser classes are always prefixed with the target 728 // name. 729 string AsmParserClassName = "AsmParser"; 730 731 // AsmParserInstCleanup - If non-empty, this is the name of a custom member 732 // function of the AsmParser class to call on every matched instruction. 733 // This can be used to perform target specific instruction post-processing. 734 string AsmParserInstCleanup = ""; 735} 736def DefaultAsmParser : AsmParser; 737 738//===----------------------------------------------------------------------===// 739// AsmParserVariant - Subtargets can have multiple different assembly parsers 740// (e.g. AT&T vs Intel syntax on X86 for example). This class can be 741// implemented by targets to describe such variants. 742// 743class AsmParserVariant { 744 // Variant - AsmParsers can be of multiple different variants. Variants are 745 // used to support targets that need to parser multiple formats for the 746 // assembly language. 747 int Variant = 0; 748 749 // CommentDelimiter - If given, the delimiter string used to recognize 750 // comments which are hard coded in the .td assembler strings for individual 751 // instructions. 752 string CommentDelimiter = ""; 753 754 // RegisterPrefix - If given, the token prefix which indicates a register 755 // token. This is used by the matcher to automatically recognize hard coded 756 // register tokens as constrained registers, instead of tokens, for the 757 // purposes of matching. 758 string RegisterPrefix = ""; 759} 760def DefaultAsmParserVariant : AsmParserVariant; 761 762/// AssemblerPredicate - This is a Predicate that can be used when the assembler 763/// matches instructions and aliases. 764class AssemblerPredicate<string cond> { 765 bit AssemblerMatcherPredicate = 1; 766 string AssemblerCondString = cond; 767} 768 769/// TokenAlias - This class allows targets to define assembler token 770/// operand aliases. That is, a token literal operand which is equivalent 771/// to another, canonical, token literal. For example, ARM allows: 772/// vmov.u32 s4, #0 -> vmov.i32, #0 773/// 'u32' is a more specific designator for the 32-bit integer type specifier 774/// and is legal for any instruction which accepts 'i32' as a datatype suffix. 775/// def : TokenAlias<".u32", ".i32">; 776/// 777/// This works by marking the match class of 'From' as a subclass of the 778/// match class of 'To'. 779class TokenAlias<string From, string To> { 780 string FromToken = From; 781 string ToToken = To; 782} 783 784/// MnemonicAlias - This class allows targets to define assembler mnemonic 785/// aliases. This should be used when all forms of one mnemonic are accepted 786/// with a different mnemonic. For example, X86 allows: 787/// sal %al, 1 -> shl %al, 1 788/// sal %ax, %cl -> shl %ax, %cl 789/// sal %eax, %cl -> shl %eax, %cl 790/// etc. Though "sal" is accepted with many forms, all of them are directly 791/// translated to a shl, so it can be handled with (in the case of X86, it 792/// actually has one for each suffix as well): 793/// def : MnemonicAlias<"sal", "shl">; 794/// 795/// Mnemonic aliases are mapped before any other translation in the match phase, 796/// and do allow Requires predicates, e.g.: 797/// 798/// def : MnemonicAlias<"pushf", "pushfq">, Requires<[In64BitMode]>; 799/// def : MnemonicAlias<"pushf", "pushfl">, Requires<[In32BitMode]>; 800/// 801class MnemonicAlias<string From, string To> { 802 string FromMnemonic = From; 803 string ToMnemonic = To; 804 805 // Predicates - Predicates that must be true for this remapping to happen. 806 list<Predicate> Predicates = []; 807} 808 809/// InstAlias - This defines an alternate assembly syntax that is allowed to 810/// match an instruction that has a different (more canonical) assembly 811/// representation. 812class InstAlias<string Asm, dag Result, bit Emit = 0b1> { 813 string AsmString = Asm; // The .s format to match the instruction with. 814 dag ResultInst = Result; // The MCInst to generate. 815 bit EmitAlias = Emit; // Emit the alias instead of what's aliased. 816 817 // Predicates - Predicates that must be true for this to match. 818 list<Predicate> Predicates = []; 819} 820 821//===----------------------------------------------------------------------===// 822// AsmWriter - This class can be implemented by targets that need to customize 823// the format of the .s file writer. 824// 825// Subtargets can have multiple different asmwriters (e.g. AT&T vs Intel syntax 826// on X86 for example). 827// 828class AsmWriter { 829 // AsmWriterClassName - This specifies the suffix to use for the asmwriter 830 // class. Generated AsmWriter classes are always prefixed with the target 831 // name. 832 string AsmWriterClassName = "AsmPrinter"; 833 834 // Variant - AsmWriters can be of multiple different variants. Variants are 835 // used to support targets that need to emit assembly code in ways that are 836 // mostly the same for different targets, but have minor differences in 837 // syntax. If the asmstring contains {|} characters in them, this integer 838 // will specify which alternative to use. For example "{x|y|z}" with Variant 839 // == 1, will expand to "y". 840 int Variant = 0; 841 842 843 // FirstOperandColumn/OperandSpacing - If the assembler syntax uses a columnar 844 // layout, the asmwriter can actually generate output in this columns (in 845 // verbose-asm mode). These two values indicate the width of the first column 846 // (the "opcode" area) and the width to reserve for subsequent operands. When 847 // verbose asm mode is enabled, operands will be indented to respect this. 848 int FirstOperandColumn = -1; 849 850 // OperandSpacing - Space between operand columns. 851 int OperandSpacing = -1; 852 853 // isMCAsmWriter - Is this assembly writer for an MC emitter? This controls 854 // generation of the printInstruction() method. For MC printers, it takes 855 // an MCInstr* operand, otherwise it takes a MachineInstr*. 856 bit isMCAsmWriter = 0; 857} 858def DefaultAsmWriter : AsmWriter; 859 860 861//===----------------------------------------------------------------------===// 862// Target - This class contains the "global" target information 863// 864class Target { 865 // InstructionSet - Instruction set description for this target. 866 InstrInfo InstructionSet; 867 868 // AssemblyParsers - The AsmParser instances available for this target. 869 list<AsmParser> AssemblyParsers = [DefaultAsmParser]; 870 871 /// AssemblyParserVariants - The AsmParserVariant instances available for 872 /// this target. 873 list<AsmParserVariant> AssemblyParserVariants = [DefaultAsmParserVariant]; 874 875 // AssemblyWriters - The AsmWriter instances available for this target. 876 list<AsmWriter> AssemblyWriters = [DefaultAsmWriter]; 877} 878 879//===----------------------------------------------------------------------===// 880// SubtargetFeature - A characteristic of the chip set. 881// 882class SubtargetFeature<string n, string a, string v, string d, 883 list<SubtargetFeature> i = []> { 884 // Name - Feature name. Used by command line (-mattr=) to determine the 885 // appropriate target chip. 886 // 887 string Name = n; 888 889 // Attribute - Attribute to be set by feature. 890 // 891 string Attribute = a; 892 893 // Value - Value the attribute to be set to by feature. 894 // 895 string Value = v; 896 897 // Desc - Feature description. Used by command line (-mattr=) to display help 898 // information. 899 // 900 string Desc = d; 901 902 // Implies - Features that this feature implies are present. If one of those 903 // features isn't set, then this one shouldn't be set either. 904 // 905 list<SubtargetFeature> Implies = i; 906} 907 908//===----------------------------------------------------------------------===// 909// Processor chip sets - These values represent each of the chip sets supported 910// by the scheduler. Each Processor definition requires corresponding 911// instruction itineraries. 912// 913class Processor<string n, ProcessorItineraries pi, list<SubtargetFeature> f> { 914 // Name - Chip set name. Used by command line (-mcpu=) to determine the 915 // appropriate target chip. 916 // 917 string Name = n; 918 919 // ProcItin - The scheduling information for the target processor. 920 // 921 ProcessorItineraries ProcItin = pi; 922 923 // Features - list of 924 list<SubtargetFeature> Features = f; 925} 926 927//===----------------------------------------------------------------------===// 928// Pull in the common support for calling conventions. 929// 930include "llvm/Target/TargetCallingConv.td" 931 932//===----------------------------------------------------------------------===// 933// Pull in the common support for DAG isel generation. 934// 935include "llvm/Target/TargetSelectionDAG.td" 936