Target.td revision 4150d83abe90a5da4ddf86433b7bf4329acfa57c
1//===- Target.td - Target Independent TableGen interface ---*- tablegen -*-===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This file defines the target-independent interfaces which should be 11// implemented by each target which is using a TableGen based code generator. 12// 13//===----------------------------------------------------------------------===// 14 15// Include all information about LLVM intrinsics. 16include "llvm/Intrinsics.td" 17 18//===----------------------------------------------------------------------===// 19// Register file description - These classes are used to fill in the target 20// description classes. 21 22class RegisterClass; // Forward def 23 24// Register - You should define one instance of this class for each register 25// in the target machine. String n will become the "name" of the register. 26class Register<string n> { 27 string Namespace = ""; 28 string AsmName = n; 29 30 // SpillSize - If this value is set to a non-zero value, it is the size in 31 // bits of the spill slot required to hold this register. If this value is 32 // set to zero, the information is inferred from any register classes the 33 // register belongs to. 34 int SpillSize = 0; 35 36 // SpillAlignment - This value is used to specify the alignment required for 37 // spilling the register. Like SpillSize, this should only be explicitly 38 // specified if the register is not in a register class. 39 int SpillAlignment = 0; 40 41 // Aliases - A list of registers that this register overlaps with. A read or 42 // modification of this register can potentially read or modify the aliased 43 // registers. 44 list<Register> Aliases = []; 45 46 // SubRegs - A list of registers that are parts of this register. Note these 47 // are "immediate" sub-registers and the registers within the list do not 48 // themselves overlap. e.g. For X86, EAX's SubRegs list contains only [AX], 49 // not [AX, AH, AL]. 50 list<Register> SubRegs = []; 51 52 // DwarfNumbers - Numbers used internally by gcc/gdb to identify the register. 53 // These values can be determined by locating the <target>.h file in the 54 // directory llvmgcc/gcc/config/<target>/ and looking for REGISTER_NAMES. The 55 // order of these names correspond to the enumeration used by gcc. A value of 56 // -1 indicates that the gcc number is undefined and -2 that register number 57 // is invalid for this mode/flavour. 58 list<int> DwarfNumbers = []; 59} 60 61// RegisterWithSubRegs - This can be used to define instances of Register which 62// need to specify sub-registers. 63// List "subregs" specifies which registers are sub-registers to this one. This 64// is used to populate the SubRegs and AliasSet fields of TargetRegisterDesc. 65// This allows the code generator to be careful not to put two values with 66// overlapping live ranges into registers which alias. 67class RegisterWithSubRegs<string n, list<Register> subregs> : Register<n> { 68 let SubRegs = subregs; 69} 70 71// SubRegSet - This can be used to define a specific mapping of registers to 72// indices, for use as named subregs of a particular physical register. Each 73// register in 'subregs' becomes an addressable subregister at index 'n' of the 74// corresponding register in 'regs'. 75class SubRegSet<int n, list<Register> regs, list<Register> subregs> { 76 int index = n; 77 78 list<Register> From = regs; 79 list<Register> To = subregs; 80} 81 82// RegisterClass - Now that all of the registers are defined, and aliases 83// between registers are defined, specify which registers belong to which 84// register classes. This also defines the default allocation order of 85// registers by register allocators. 86// 87class RegisterClass<string namespace, list<ValueType> regTypes, int alignment, 88 list<Register> regList> { 89 string Namespace = namespace; 90 91 // RegType - Specify the list ValueType of the registers in this register 92 // class. Note that all registers in a register class must have the same 93 // ValueTypes. This is a list because some targets permit storing different 94 // types in same register, for example vector values with 128-bit total size, 95 // but different count/size of items, like SSE on x86. 96 // 97 list<ValueType> RegTypes = regTypes; 98 99 // Size - Specify the spill size in bits of the registers. A default value of 100 // zero lets tablgen pick an appropriate size. 101 int Size = 0; 102 103 // Alignment - Specify the alignment required of the registers when they are 104 // stored or loaded to memory. 105 // 106 int Alignment = alignment; 107 108 // CopyCost - This value is used to specify the cost of copying a value 109 // between two registers in this register class. The default value is one 110 // meaning it takes a single instruction to perform the copying. A negative 111 // value means copying is extremely expensive or impossible. 112 int CopyCost = 1; 113 114 // MemberList - Specify which registers are in this class. If the 115 // allocation_order_* method are not specified, this also defines the order of 116 // allocation used by the register allocator. 117 // 118 list<Register> MemberList = regList; 119 120 // SubClassList - Specify which register classes correspond to subregisters 121 // of this class. The order should be by subregister set index. 122 list<RegisterClass> SubRegClassList = []; 123 124 // MethodProtos/MethodBodies - These members can be used to insert arbitrary 125 // code into a generated register class. The normal usage of this is to 126 // overload virtual methods. 127 code MethodProtos = [{}]; 128 code MethodBodies = [{}]; 129} 130 131 132//===----------------------------------------------------------------------===// 133// DwarfRegNum - This class provides a mapping of the llvm register enumeration 134// to the register numbering used by gcc and gdb. These values are used by a 135// debug information writer (ex. DwarfWriter) to describe where values may be 136// located during execution. 137class DwarfRegNum<list<int> Numbers> { 138 // DwarfNumbers - Numbers used internally by gcc/gdb to identify the register. 139 // These values can be determined by locating the <target>.h file in the 140 // directory llvmgcc/gcc/config/<target>/ and looking for REGISTER_NAMES. The 141 // order of these names correspond to the enumeration used by gcc. A value of 142 // -1 indicates that the gcc number is undefined and -2 that register number is 143 // invalid for this mode/flavour. 144 list<int> DwarfNumbers = Numbers; 145} 146 147//===----------------------------------------------------------------------===// 148// Pull in the common support for scheduling 149// 150include "llvm/Target/TargetSchedule.td" 151 152class Predicate; // Forward def 153 154//===----------------------------------------------------------------------===// 155// Instruction set description - These classes correspond to the C++ classes in 156// the Target/TargetInstrInfo.h file. 157// 158class Instruction { 159 string Namespace = ""; 160 161 dag OutOperandList; // An dag containing the MI def operand list. 162 dag InOperandList; // An dag containing the MI use operand list. 163 string AsmString = ""; // The .s format to print the instruction with. 164 165 // Pattern - Set to the DAG pattern for this instruction, if we know of one, 166 // otherwise, uninitialized. 167 list<dag> Pattern; 168 169 // The follow state will eventually be inferred automatically from the 170 // instruction pattern. 171 172 list<Register> Uses = []; // Default to using no non-operand registers 173 list<Register> Defs = []; // Default to modifying no non-operand registers 174 175 // Predicates - List of predicates which will be turned into isel matching 176 // code. 177 list<Predicate> Predicates = []; 178 179 // Code size. 180 int CodeSize = 0; 181 182 // Added complexity passed onto matching pattern. 183 int AddedComplexity = 0; 184 185 // These bits capture information about the high-level semantics of the 186 // instruction. 187 bit isReturn = 0; // Is this instruction a return instruction? 188 bit isBranch = 0; // Is this instruction a branch instruction? 189 bit isIndirectBranch = 0; // Is this instruction an indirect branch? 190 bit isBarrier = 0; // Can control flow fall through this instruction? 191 bit isCall = 0; // Is this instruction a call instruction? 192 bit canFoldAsLoad = 0; // Can this be folded as a simple memory operand? 193 bit mayLoad = 0; // Is it possible for this inst to read memory? 194 bit mayStore = 0; // Is it possible for this inst to write memory? 195 bit isTwoAddress = 0; // Is this a two address instruction? 196 bit isConvertibleToThreeAddress = 0; // Can this 2-addr instruction promote? 197 bit isCommutable = 0; // Is this 3 operand instruction commutable? 198 bit isTerminator = 0; // Is this part of the terminator for a basic block? 199 bit isReMaterializable = 0; // Is this instruction re-materializable? 200 bit isPredicable = 0; // Is this instruction predicable? 201 bit hasDelaySlot = 0; // Does this instruction have an delay slot? 202 bit usesCustomDAGSchedInserter = 0; // Pseudo instr needing special help. 203 bit hasCtrlDep = 0; // Does this instruction r/w ctrl-flow chains? 204 bit isNotDuplicable = 0; // Is it unsafe to duplicate this instruction? 205 bit isAsCheapAsAMove = 0; // As cheap (or cheaper) than a move instruction. 206 207 // Side effect flags - When set, the flags have these meanings: 208 // 209 // hasSideEffects - The instruction has side effects that are not 210 // captured by any operands of the instruction or other flags. 211 // 212 // mayHaveSideEffects - Some instances of the instruction can have side 213 // effects. The virtual method "isReallySideEffectFree" is called to 214 // determine this. Load instructions are an example of where this is 215 // useful. In general, loads always have side effects. However, loads from 216 // constant pools don't. Individual back ends make this determination. 217 // 218 // neverHasSideEffects - Set on an instruction with no pattern if it has no 219 // side effects. 220 bit hasSideEffects = 0; 221 bit mayHaveSideEffects = 0; 222 bit neverHasSideEffects = 0; 223 224 InstrItinClass Itinerary = NoItinerary;// Execution steps used for scheduling. 225 226 string Constraints = ""; // OperandConstraint, e.g. $src = $dst. 227 228 /// DisableEncoding - List of operand names (e.g. "$op1,$op2") that should not 229 /// be encoded into the output machineinstr. 230 string DisableEncoding = ""; 231} 232 233/// Predicates - These are extra conditionals which are turned into instruction 234/// selector matching code. Currently each predicate is just a string. 235class Predicate<string cond> { 236 string CondString = cond; 237} 238 239/// NoHonorSignDependentRounding - This predicate is true if support for 240/// sign-dependent-rounding is not enabled. 241def NoHonorSignDependentRounding 242 : Predicate<"!HonorSignDependentRoundingFPMath()">; 243 244class Requires<list<Predicate> preds> { 245 list<Predicate> Predicates = preds; 246} 247 248/// ops definition - This is just a simple marker used to identify the operands 249/// list for an instruction. outs and ins are identical both syntatically and 250/// semantically, they are used to define def operands and use operands to 251/// improve readibility. This should be used like this: 252/// (outs R32:$dst), (ins R32:$src1, R32:$src2) or something similar. 253def ops; 254def outs; 255def ins; 256 257/// variable_ops definition - Mark this instruction as taking a variable number 258/// of operands. 259def variable_ops; 260 261/// ptr_rc definition - Mark this operand as being a pointer value whose 262/// register class is resolved dynamically via a callback to TargetInstrInfo. 263/// FIXME: We should probably change this to a class which contain a list of 264/// flags. But currently we have but one flag. 265def ptr_rc; 266 267/// unknown definition - Mark this operand as being of unknown type, causing 268/// it to be resolved by inference in the context it is used. 269def unknown; 270 271/// Operand Types - These provide the built-in operand types that may be used 272/// by a target. Targets can optionally provide their own operand types as 273/// needed, though this should not be needed for RISC targets. 274class Operand<ValueType ty> { 275 ValueType Type = ty; 276 string PrintMethod = "printOperand"; 277 dag MIOperandInfo = (ops); 278} 279 280def i1imm : Operand<i1>; 281def i8imm : Operand<i8>; 282def i16imm : Operand<i16>; 283def i32imm : Operand<i32>; 284def i64imm : Operand<i64>; 285 286def f32imm : Operand<f32>; 287def f64imm : Operand<f64>; 288 289/// zero_reg definition - Special node to stand for the zero register. 290/// 291def zero_reg; 292 293/// PredicateOperand - This can be used to define a predicate operand for an 294/// instruction. OpTypes specifies the MIOperandInfo for the operand, and 295/// AlwaysVal specifies the value of this predicate when set to "always 296/// execute". 297class PredicateOperand<ValueType ty, dag OpTypes, dag AlwaysVal> 298 : Operand<ty> { 299 let MIOperandInfo = OpTypes; 300 dag DefaultOps = AlwaysVal; 301} 302 303/// OptionalDefOperand - This is used to define a optional definition operand 304/// for an instruction. DefaultOps is the register the operand represents if none 305/// is supplied, e.g. zero_reg. 306class OptionalDefOperand<ValueType ty, dag OpTypes, dag defaultops> 307 : Operand<ty> { 308 let MIOperandInfo = OpTypes; 309 dag DefaultOps = defaultops; 310} 311 312 313// InstrInfo - This class should only be instantiated once to provide parameters 314// which are global to the the target machine. 315// 316class InstrInfo { 317 // If the target wants to associate some target-specific information with each 318 // instruction, it should provide these two lists to indicate how to assemble 319 // the target specific information into the 32 bits available. 320 // 321 list<string> TSFlagsFields = []; 322 list<int> TSFlagsShifts = []; 323 324 // Target can specify its instructions in either big or little-endian formats. 325 // For instance, while both Sparc and PowerPC are big-endian platforms, the 326 // Sparc manual specifies its instructions in the format [31..0] (big), while 327 // PowerPC specifies them using the format [0..31] (little). 328 bit isLittleEndianEncoding = 0; 329 330 // Targets that can support the HasI1 argument on ADDC and ADDE, rather than 331 // Flag, have this bit set. This is transitional and should go away when all 332 // targets have been switched over. 333 bit supportsHasI1 = 0; 334} 335 336// Standard Instructions. 337def PHI : Instruction { 338 let OutOperandList = (ops); 339 let InOperandList = (ops variable_ops); 340 let AsmString = "PHINODE"; 341 let Namespace = "TargetInstrInfo"; 342} 343def INLINEASM : Instruction { 344 let OutOperandList = (ops); 345 let InOperandList = (ops variable_ops); 346 let AsmString = ""; 347 let Namespace = "TargetInstrInfo"; 348} 349def DBG_LABEL : Instruction { 350 let OutOperandList = (ops); 351 let InOperandList = (ops i32imm:$id); 352 let AsmString = ""; 353 let Namespace = "TargetInstrInfo"; 354 let hasCtrlDep = 1; 355} 356def EH_LABEL : Instruction { 357 let OutOperandList = (ops); 358 let InOperandList = (ops i32imm:$id); 359 let AsmString = ""; 360 let Namespace = "TargetInstrInfo"; 361 let hasCtrlDep = 1; 362} 363def GC_LABEL : Instruction { 364 let OutOperandList = (ops); 365 let InOperandList = (ops i32imm:$id); 366 let AsmString = ""; 367 let Namespace = "TargetInstrInfo"; 368 let hasCtrlDep = 1; 369} 370def DECLARE : Instruction { 371 let OutOperandList = (ops); 372 let InOperandList = (ops variable_ops); 373 let AsmString = ""; 374 let Namespace = "TargetInstrInfo"; 375 let hasCtrlDep = 1; 376} 377def EXTRACT_SUBREG : Instruction { 378 let OutOperandList = (ops unknown:$dst); 379 let InOperandList = (ops unknown:$supersrc, i32imm:$subidx); 380 let AsmString = ""; 381 let Namespace = "TargetInstrInfo"; 382 let neverHasSideEffects = 1; 383} 384def INSERT_SUBREG : Instruction { 385 let OutOperandList = (ops unknown:$dst); 386 let InOperandList = (ops unknown:$supersrc, unknown:$subsrc, i32imm:$subidx); 387 let AsmString = ""; 388 let Namespace = "TargetInstrInfo"; 389 let neverHasSideEffects = 1; 390 let Constraints = "$supersrc = $dst"; 391} 392def IMPLICIT_DEF : Instruction { 393 let OutOperandList = (ops unknown:$dst); 394 let InOperandList = (ops); 395 let AsmString = ""; 396 let Namespace = "TargetInstrInfo"; 397 let neverHasSideEffects = 1; 398 let isReMaterializable = 1; 399 let isAsCheapAsAMove = 1; 400} 401def SUBREG_TO_REG : Instruction { 402 let OutOperandList = (ops unknown:$dst); 403 let InOperandList = (ops unknown:$implsrc, unknown:$subsrc, i32imm:$subidx); 404 let AsmString = ""; 405 let Namespace = "TargetInstrInfo"; 406 let neverHasSideEffects = 1; 407} 408def COPY_TO_REGCLASS : Instruction { 409 let OutOperandList = (ops unknown:$dst); 410 let InOperandList = (ops unknown:$src, i32imm:$regclass); 411 let AsmString = ""; 412 let Namespace = "TargetInstrInfo"; 413 let neverHasSideEffects = 1; 414 let isAsCheapAsAMove = 1; 415} 416 417//===----------------------------------------------------------------------===// 418// AsmWriter - This class can be implemented by targets that need to customize 419// the format of the .s file writer. 420// 421// Subtargets can have multiple different asmwriters (e.g. AT&T vs Intel syntax 422// on X86 for example). 423// 424class AsmWriter { 425 // AsmWriterClassName - This specifies the suffix to use for the asmwriter 426 // class. Generated AsmWriter classes are always prefixed with the target 427 // name. 428 string AsmWriterClassName = "AsmPrinter"; 429 430 // InstFormatName - AsmWriters can specify the name of the format string to 431 // print instructions with. 432 string InstFormatName = "AsmString"; 433 434 // Variant - AsmWriters can be of multiple different variants. Variants are 435 // used to support targets that need to emit assembly code in ways that are 436 // mostly the same for different targets, but have minor differences in 437 // syntax. If the asmstring contains {|} characters in them, this integer 438 // will specify which alternative to use. For example "{x|y|z}" with Variant 439 // == 1, will expand to "y". 440 int Variant = 0; 441} 442def DefaultAsmWriter : AsmWriter; 443 444 445//===----------------------------------------------------------------------===// 446// Target - This class contains the "global" target information 447// 448class Target { 449 // InstructionSet - Instruction set description for this target. 450 InstrInfo InstructionSet; 451 452 // AssemblyWriters - The AsmWriter instances available for this target. 453 list<AsmWriter> AssemblyWriters = [DefaultAsmWriter]; 454} 455 456//===----------------------------------------------------------------------===// 457// SubtargetFeature - A characteristic of the chip set. 458// 459class SubtargetFeature<string n, string a, string v, string d, 460 list<SubtargetFeature> i = []> { 461 // Name - Feature name. Used by command line (-mattr=) to determine the 462 // appropriate target chip. 463 // 464 string Name = n; 465 466 // Attribute - Attribute to be set by feature. 467 // 468 string Attribute = a; 469 470 // Value - Value the attribute to be set to by feature. 471 // 472 string Value = v; 473 474 // Desc - Feature description. Used by command line (-mattr=) to display help 475 // information. 476 // 477 string Desc = d; 478 479 // Implies - Features that this feature implies are present. If one of those 480 // features isn't set, then this one shouldn't be set either. 481 // 482 list<SubtargetFeature> Implies = i; 483} 484 485//===----------------------------------------------------------------------===// 486// Processor chip sets - These values represent each of the chip sets supported 487// by the scheduler. Each Processor definition requires corresponding 488// instruction itineraries. 489// 490class Processor<string n, ProcessorItineraries pi, list<SubtargetFeature> f> { 491 // Name - Chip set name. Used by command line (-mcpu=) to determine the 492 // appropriate target chip. 493 // 494 string Name = n; 495 496 // ProcItin - The scheduling information for the target processor. 497 // 498 ProcessorItineraries ProcItin = pi; 499 500 // Features - list of 501 list<SubtargetFeature> Features = f; 502} 503 504//===----------------------------------------------------------------------===// 505// Pull in the common support for calling conventions. 506// 507include "llvm/Target/TargetCallingConv.td" 508 509//===----------------------------------------------------------------------===// 510// Pull in the common support for DAG isel generation. 511// 512include "llvm/Target/TargetSelectionDAG.td" 513