Target.td revision 5b55ff0c1555031c1c85f88d67c3b566750a9319
1//===- Target.td - Target Independent TableGen interface ---*- tablegen -*-===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This file defines the target-independent interfaces which should be 11// implemented by each target which is using a TableGen based code generator. 12// 13//===----------------------------------------------------------------------===// 14 15// Include all information about LLVM intrinsics. 16include "llvm/Intrinsics.td" 17 18//===----------------------------------------------------------------------===// 19// Register file description - These classes are used to fill in the target 20// description classes. 21 22class RegisterClass; // Forward def 23 24// SubRegIndex - Use instances of SubRegIndex to identify subregisters. 25class SubRegIndex { 26 string Namespace = ""; 27} 28 29// Register - You should define one instance of this class for each register 30// in the target machine. String n will become the "name" of the register. 31class Register<string n> { 32 string Namespace = ""; 33 string AsmName = n; 34 35 // SpillSize - If this value is set to a non-zero value, it is the size in 36 // bits of the spill slot required to hold this register. If this value is 37 // set to zero, the information is inferred from any register classes the 38 // register belongs to. 39 int SpillSize = 0; 40 41 // SpillAlignment - This value is used to specify the alignment required for 42 // spilling the register. Like SpillSize, this should only be explicitly 43 // specified if the register is not in a register class. 44 int SpillAlignment = 0; 45 46 // Aliases - A list of registers that this register overlaps with. A read or 47 // modification of this register can potentially read or modify the aliased 48 // registers. 49 list<Register> Aliases = []; 50 51 // SubRegs - A list of registers that are parts of this register. Note these 52 // are "immediate" sub-registers and the registers within the list do not 53 // themselves overlap. e.g. For X86, EAX's SubRegs list contains only [AX], 54 // not [AX, AH, AL]. 55 list<Register> SubRegs = []; 56 57 // SubRegIndices - For each register in SubRegs, specify the SubRegIndex used 58 // to address it. Sub-sub-register indices are automatically inherited from 59 // SubRegs. 60 list<SubRegIndex> SubRegIndices = []; 61 62 // CompositeIndices - Specify subreg indices that don't correspond directly to 63 // a register in SubRegs and are not inherited. The following formats are 64 // supported: 65 // 66 // (a) Identity - Reg:a == Reg 67 // (a b) Alias - Reg:a == Reg:b 68 // (a b,c) Composite - Reg:a == (Reg:b):c 69 // 70 // This can be used to disambiguate a sub-sub-register that exists in more 71 // than one subregister and other weird stuff. 72 list<dag> CompositeIndices = []; 73 74 // DwarfNumbers - Numbers used internally by gcc/gdb to identify the register. 75 // These values can be determined by locating the <target>.h file in the 76 // directory llvmgcc/gcc/config/<target>/ and looking for REGISTER_NAMES. The 77 // order of these names correspond to the enumeration used by gcc. A value of 78 // -1 indicates that the gcc number is undefined and -2 that register number 79 // is invalid for this mode/flavour. 80 list<int> DwarfNumbers = []; 81} 82 83// RegisterWithSubRegs - This can be used to define instances of Register which 84// need to specify sub-registers. 85// List "subregs" specifies which registers are sub-registers to this one. This 86// is used to populate the SubRegs and AliasSet fields of TargetRegisterDesc. 87// This allows the code generator to be careful not to put two values with 88// overlapping live ranges into registers which alias. 89class RegisterWithSubRegs<string n, list<Register> subregs> : Register<n> { 90 let SubRegs = subregs; 91} 92 93// RegisterClass - Now that all of the registers are defined, and aliases 94// between registers are defined, specify which registers belong to which 95// register classes. This also defines the default allocation order of 96// registers by register allocators. 97// 98class RegisterClass<string namespace, list<ValueType> regTypes, int alignment, 99 list<Register> regList> { 100 string Namespace = namespace; 101 102 // RegType - Specify the list ValueType of the registers in this register 103 // class. Note that all registers in a register class must have the same 104 // ValueTypes. This is a list because some targets permit storing different 105 // types in same register, for example vector values with 128-bit total size, 106 // but different count/size of items, like SSE on x86. 107 // 108 list<ValueType> RegTypes = regTypes; 109 110 // Size - Specify the spill size in bits of the registers. A default value of 111 // zero lets tablgen pick an appropriate size. 112 int Size = 0; 113 114 // Alignment - Specify the alignment required of the registers when they are 115 // stored or loaded to memory. 116 // 117 int Alignment = alignment; 118 119 // CopyCost - This value is used to specify the cost of copying a value 120 // between two registers in this register class. The default value is one 121 // meaning it takes a single instruction to perform the copying. A negative 122 // value means copying is extremely expensive or impossible. 123 int CopyCost = 1; 124 125 // MemberList - Specify which registers are in this class. If the 126 // allocation_order_* method are not specified, this also defines the order of 127 // allocation used by the register allocator. 128 // 129 list<Register> MemberList = regList; 130 131 // SubRegClasses - Specify the register class of subregisters as a list of 132 // dags: (RegClass SubRegIndex, SubRegindex, ...) 133 list<dag> SubRegClasses = []; 134 135 // MethodProtos/MethodBodies - These members can be used to insert arbitrary 136 // code into a generated register class. The normal usage of this is to 137 // overload virtual methods. 138 code MethodProtos = [{}]; 139 code MethodBodies = [{}]; 140} 141 142 143//===----------------------------------------------------------------------===// 144// DwarfRegNum - This class provides a mapping of the llvm register enumeration 145// to the register numbering used by gcc and gdb. These values are used by a 146// debug information writer to describe where values may be located during 147// execution. 148class DwarfRegNum<list<int> Numbers> { 149 // DwarfNumbers - Numbers used internally by gcc/gdb to identify the register. 150 // These values can be determined by locating the <target>.h file in the 151 // directory llvmgcc/gcc/config/<target>/ and looking for REGISTER_NAMES. The 152 // order of these names correspond to the enumeration used by gcc. A value of 153 // -1 indicates that the gcc number is undefined and -2 that register number is 154 // invalid for this mode/flavour. 155 list<int> DwarfNumbers = Numbers; 156} 157 158//===----------------------------------------------------------------------===// 159// Pull in the common support for scheduling 160// 161include "llvm/Target/TargetSchedule.td" 162 163class Predicate; // Forward def 164 165//===----------------------------------------------------------------------===// 166// Instruction set description - These classes correspond to the C++ classes in 167// the Target/TargetInstrInfo.h file. 168// 169class Instruction { 170 string Namespace = ""; 171 172 dag OutOperandList; // An dag containing the MI def operand list. 173 dag InOperandList; // An dag containing the MI use operand list. 174 string AsmString = ""; // The .s format to print the instruction with. 175 176 // Pattern - Set to the DAG pattern for this instruction, if we know of one, 177 // otherwise, uninitialized. 178 list<dag> Pattern; 179 180 // The follow state will eventually be inferred automatically from the 181 // instruction pattern. 182 183 list<Register> Uses = []; // Default to using no non-operand registers 184 list<Register> Defs = []; // Default to modifying no non-operand registers 185 186 // Predicates - List of predicates which will be turned into isel matching 187 // code. 188 list<Predicate> Predicates = []; 189 190 // Code size. 191 int CodeSize = 0; 192 193 // Added complexity passed onto matching pattern. 194 int AddedComplexity = 0; 195 196 // These bits capture information about the high-level semantics of the 197 // instruction. 198 bit isReturn = 0; // Is this instruction a return instruction? 199 bit isBranch = 0; // Is this instruction a branch instruction? 200 bit isIndirectBranch = 0; // Is this instruction an indirect branch? 201 bit isBarrier = 0; // Can control flow fall through this instruction? 202 bit isCall = 0; // Is this instruction a call instruction? 203 bit canFoldAsLoad = 0; // Can this be folded as a simple memory operand? 204 bit mayLoad = 0; // Is it possible for this inst to read memory? 205 bit mayStore = 0; // Is it possible for this inst to write memory? 206 bit isConvertibleToThreeAddress = 0; // Can this 2-addr instruction promote? 207 bit isCommutable = 0; // Is this 3 operand instruction commutable? 208 bit isTerminator = 0; // Is this part of the terminator for a basic block? 209 bit isReMaterializable = 0; // Is this instruction re-materializable? 210 bit isPredicable = 0; // Is this instruction predicable? 211 bit hasDelaySlot = 0; // Does this instruction have an delay slot? 212 bit usesCustomInserter = 0; // Pseudo instr needing special help. 213 bit hasCtrlDep = 0; // Does this instruction r/w ctrl-flow chains? 214 bit isNotDuplicable = 0; // Is it unsafe to duplicate this instruction? 215 bit isAsCheapAsAMove = 0; // As cheap (or cheaper) than a move instruction. 216 bit hasExtraSrcRegAllocReq = 0; // Sources have special regalloc requirement? 217 bit hasExtraDefRegAllocReq = 0; // Defs have special regalloc requirement? 218 219 // Side effect flags - When set, the flags have these meanings: 220 // 221 // hasSideEffects - The instruction has side effects that are not 222 // captured by any operands of the instruction or other flags. 223 // 224 // neverHasSideEffects - Set on an instruction with no pattern if it has no 225 // side effects. 226 bit hasSideEffects = 0; 227 bit neverHasSideEffects = 0; 228 229 // Is this instruction a "real" instruction (with a distinct machine 230 // encoding), or is it a pseudo instruction used for codegen modeling 231 // purposes. 232 bit isCodeGenOnly = 0; 233 234 // Is this instruction a pseudo instruction for use by the assembler parser. 235 bit isAsmParserOnly = 0; 236 237 InstrItinClass Itinerary = NoItinerary;// Execution steps used for scheduling. 238 239 string Constraints = ""; // OperandConstraint, e.g. $src = $dst. 240 241 /// DisableEncoding - List of operand names (e.g. "$op1,$op2") that should not 242 /// be encoded into the output machineinstr. 243 string DisableEncoding = ""; 244 245 /// Target-specific flags. This becomes the TSFlags field in TargetInstrDesc. 246 bits<64> TSFlags = 0; 247} 248 249/// Predicates - These are extra conditionals which are turned into instruction 250/// selector matching code. Currently each predicate is just a string. 251class Predicate<string cond> { 252 string CondString = cond; 253} 254 255/// NoHonorSignDependentRounding - This predicate is true if support for 256/// sign-dependent-rounding is not enabled. 257def NoHonorSignDependentRounding 258 : Predicate<"!HonorSignDependentRoundingFPMath()">; 259 260class Requires<list<Predicate> preds> { 261 list<Predicate> Predicates = preds; 262} 263 264/// ops definition - This is just a simple marker used to identify the operands 265/// list for an instruction. outs and ins are identical both syntatically and 266/// semantically, they are used to define def operands and use operands to 267/// improve readibility. This should be used like this: 268/// (outs R32:$dst), (ins R32:$src1, R32:$src2) or something similar. 269def ops; 270def outs; 271def ins; 272 273/// variable_ops definition - Mark this instruction as taking a variable number 274/// of operands. 275def variable_ops; 276 277 278/// PointerLikeRegClass - Values that are designed to have pointer width are 279/// derived from this. TableGen treats the register class as having a symbolic 280/// type that it doesn't know, and resolves the actual regclass to use by using 281/// the TargetRegisterInfo::getPointerRegClass() hook at codegen time. 282class PointerLikeRegClass<int Kind> { 283 int RegClassKind = Kind; 284} 285 286 287/// ptr_rc definition - Mark this operand as being a pointer value whose 288/// register class is resolved dynamically via a callback to TargetInstrInfo. 289/// FIXME: We should probably change this to a class which contain a list of 290/// flags. But currently we have but one flag. 291def ptr_rc : PointerLikeRegClass<0>; 292 293/// unknown definition - Mark this operand as being of unknown type, causing 294/// it to be resolved by inference in the context it is used. 295def unknown; 296 297/// AsmOperandClass - Representation for the kinds of operands which the target 298/// specific parser can create and the assembly matcher may need to distinguish. 299/// 300/// Operand classes are used to define the order in which instructions are 301/// matched, to ensure that the instruction which gets matched for any 302/// particular list of operands is deterministic. 303/// 304/// The target specific parser must be able to classify a parsed operand into a 305/// unique class which does not partially overlap with any other classes. It can 306/// match a subset of some other class, in which case the super class field 307/// should be defined. 308class AsmOperandClass { 309 /// The name to use for this class, which should be usable as an enum value. 310 string Name = ?; 311 312 /// The super classes of this operand. 313 list<AsmOperandClass> SuperClasses = []; 314 315 /// The name of the method on the target specific operand to call to test 316 /// whether the operand is an instance of this class. If not set, this will 317 /// default to "isFoo", where Foo is the AsmOperandClass name. The method 318 /// signature should be: 319 /// bool isFoo() const; 320 string PredicateMethod = ?; 321 322 /// The name of the method on the target specific operand to call to add the 323 /// target specific operand to an MCInst. If not set, this will default to 324 /// "addFooOperands", where Foo is the AsmOperandClass name. The method 325 /// signature should be: 326 /// void addFooOperands(MCInst &Inst, unsigned N) const; 327 string RenderMethod = ?; 328} 329 330def ImmAsmOperand : AsmOperandClass { 331 let Name = "Imm"; 332} 333 334/// Operand Types - These provide the built-in operand types that may be used 335/// by a target. Targets can optionally provide their own operand types as 336/// needed, though this should not be needed for RISC targets. 337class Operand<ValueType ty> { 338 ValueType Type = ty; 339 string PrintMethod = "printOperand"; 340 string AsmOperandLowerMethod = ?; 341 dag MIOperandInfo = (ops); 342 343 // ParserMatchClass - The "match class" that operands of this type fit 344 // in. Match classes are used to define the order in which instructions are 345 // match, to ensure that which instructions gets matched is deterministic. 346 // 347 // The target specific parser must be able to classify an parsed operand into 348 // a unique class, which does not partially overlap with any other classes. It 349 // can match a subset of some other class, in which case the AsmOperandClass 350 // should declare the other operand as one of its super classes. 351 AsmOperandClass ParserMatchClass = ImmAsmOperand; 352} 353 354def i1imm : Operand<i1>; 355def i8imm : Operand<i8>; 356def i16imm : Operand<i16>; 357def i32imm : Operand<i32>; 358def i64imm : Operand<i64>; 359 360def f32imm : Operand<f32>; 361def f64imm : Operand<f64>; 362 363/// zero_reg definition - Special node to stand for the zero register. 364/// 365def zero_reg; 366 367/// PredicateOperand - This can be used to define a predicate operand for an 368/// instruction. OpTypes specifies the MIOperandInfo for the operand, and 369/// AlwaysVal specifies the value of this predicate when set to "always 370/// execute". 371class PredicateOperand<ValueType ty, dag OpTypes, dag AlwaysVal> 372 : Operand<ty> { 373 let MIOperandInfo = OpTypes; 374 dag DefaultOps = AlwaysVal; 375} 376 377/// OptionalDefOperand - This is used to define a optional definition operand 378/// for an instruction. DefaultOps is the register the operand represents if 379/// none is supplied, e.g. zero_reg. 380class OptionalDefOperand<ValueType ty, dag OpTypes, dag defaultops> 381 : Operand<ty> { 382 let MIOperandInfo = OpTypes; 383 dag DefaultOps = defaultops; 384} 385 386 387// InstrInfo - This class should only be instantiated once to provide parameters 388// which are global to the target machine. 389// 390class InstrInfo { 391 // Target can specify its instructions in either big or little-endian formats. 392 // For instance, while both Sparc and PowerPC are big-endian platforms, the 393 // Sparc manual specifies its instructions in the format [31..0] (big), while 394 // PowerPC specifies them using the format [0..31] (little). 395 bit isLittleEndianEncoding = 0; 396} 397 398// Standard Pseudo Instructions. 399// This list must match TargetOpcodes.h and CodeGenTarget.cpp. 400// Only these instructions are allowed in the TargetOpcode namespace. 401let isCodeGenOnly = 1, Namespace = "TargetOpcode" in { 402def PHI : Instruction { 403 let OutOperandList = (outs); 404 let InOperandList = (ins variable_ops); 405 let AsmString = "PHINODE"; 406} 407def INLINEASM : Instruction { 408 let OutOperandList = (outs); 409 let InOperandList = (ins variable_ops); 410 let AsmString = ""; 411} 412def PROLOG_LABEL : Instruction { 413 let OutOperandList = (outs); 414 let InOperandList = (ins i32imm:$id); 415 let AsmString = ""; 416 let hasCtrlDep = 1; 417 let isNotDuplicable = 1; 418} 419def EH_LABEL : Instruction { 420 let OutOperandList = (outs); 421 let InOperandList = (ins i32imm:$id); 422 let AsmString = ""; 423 let hasCtrlDep = 1; 424 let isNotDuplicable = 1; 425} 426def GC_LABEL : Instruction { 427 let OutOperandList = (outs); 428 let InOperandList = (ins i32imm:$id); 429 let AsmString = ""; 430 let hasCtrlDep = 1; 431 let isNotDuplicable = 1; 432} 433def KILL : Instruction { 434 let OutOperandList = (outs); 435 let InOperandList = (ins variable_ops); 436 let AsmString = ""; 437 let neverHasSideEffects = 1; 438} 439def EXTRACT_SUBREG : Instruction { 440 let OutOperandList = (outs unknown:$dst); 441 let InOperandList = (ins unknown:$supersrc, i32imm:$subidx); 442 let AsmString = ""; 443 let neverHasSideEffects = 1; 444} 445def INSERT_SUBREG : Instruction { 446 let OutOperandList = (outs unknown:$dst); 447 let InOperandList = (ins unknown:$supersrc, unknown:$subsrc, i32imm:$subidx); 448 let AsmString = ""; 449 let neverHasSideEffects = 1; 450 let Constraints = "$supersrc = $dst"; 451} 452def IMPLICIT_DEF : Instruction { 453 let OutOperandList = (outs unknown:$dst); 454 let InOperandList = (ins); 455 let AsmString = ""; 456 let neverHasSideEffects = 1; 457 let isReMaterializable = 1; 458 let isAsCheapAsAMove = 1; 459} 460def SUBREG_TO_REG : Instruction { 461 let OutOperandList = (outs unknown:$dst); 462 let InOperandList = (ins unknown:$implsrc, unknown:$subsrc, i32imm:$subidx); 463 let AsmString = ""; 464 let neverHasSideEffects = 1; 465} 466def COPY_TO_REGCLASS : Instruction { 467 let OutOperandList = (outs unknown:$dst); 468 let InOperandList = (ins unknown:$src, i32imm:$regclass); 469 let AsmString = ""; 470 let neverHasSideEffects = 1; 471 let isAsCheapAsAMove = 1; 472} 473def DBG_VALUE : Instruction { 474 let OutOperandList = (outs); 475 let InOperandList = (ins variable_ops); 476 let AsmString = "DBG_VALUE"; 477 let isAsCheapAsAMove = 1; 478} 479def REG_SEQUENCE : Instruction { 480 let OutOperandList = (outs unknown:$dst); 481 let InOperandList = (ins variable_ops); 482 let AsmString = ""; 483 let neverHasSideEffects = 1; 484 let isAsCheapAsAMove = 1; 485} 486def COPY : Instruction { 487 let OutOperandList = (outs unknown:$dst); 488 let InOperandList = (ins unknown:$src); 489 let AsmString = ""; 490 let neverHasSideEffects = 1; 491 let isAsCheapAsAMove = 1; 492} 493} 494 495//===----------------------------------------------------------------------===// 496// AsmParser - This class can be implemented by targets that wish to implement 497// .s file parsing. 498// 499// Subtargets can have multiple different assembly parsers (e.g. AT&T vs Intel 500// syntax on X86 for example). 501// 502class AsmParser { 503 // AsmParserClassName - This specifies the suffix to use for the asmparser 504 // class. Generated AsmParser classes are always prefixed with the target 505 // name. 506 string AsmParserClassName = "AsmParser"; 507 508 // AsmParserInstCleanup - If non-empty, this is the name of a custom function on the 509 // AsmParser class to call on every matched instruction. This can be used to 510 // perform target specific instruction post-processing. 511 string AsmParserInstCleanup = ""; 512 513 // MatchInstructionName - The name of the instruction matching function to 514 // generate. 515 string MatchInstructionName = "MatchInstruction"; 516 517 // Variant - AsmParsers can be of multiple different variants. Variants are 518 // used to support targets that need to parser multiple formats for the 519 // assembly language. 520 int Variant = 0; 521 522 // CommentDelimiter - If given, the delimiter string used to recognize 523 // comments which are hard coded in the .td assembler strings for individual 524 // instructions. 525 string CommentDelimiter = ""; 526 527 // RegisterPrefix - If given, the token prefix which indicates a register 528 // token. This is used by the matcher to automatically recognize hard coded 529 // register tokens as constrained registers, instead of tokens, for the 530 // purposes of matching. 531 string RegisterPrefix = ""; 532} 533def DefaultAsmParser : AsmParser; 534 535 536//===----------------------------------------------------------------------===// 537// AsmWriter - This class can be implemented by targets that need to customize 538// the format of the .s file writer. 539// 540// Subtargets can have multiple different asmwriters (e.g. AT&T vs Intel syntax 541// on X86 for example). 542// 543class AsmWriter { 544 // AsmWriterClassName - This specifies the suffix to use for the asmwriter 545 // class. Generated AsmWriter classes are always prefixed with the target 546 // name. 547 string AsmWriterClassName = "AsmPrinter"; 548 549 // InstFormatName - AsmWriters can specify the name of the format string to 550 // print instructions with. 551 string InstFormatName = "AsmString"; 552 553 // Variant - AsmWriters can be of multiple different variants. Variants are 554 // used to support targets that need to emit assembly code in ways that are 555 // mostly the same for different targets, but have minor differences in 556 // syntax. If the asmstring contains {|} characters in them, this integer 557 // will specify which alternative to use. For example "{x|y|z}" with Variant 558 // == 1, will expand to "y". 559 int Variant = 0; 560 561 562 // FirstOperandColumn/OperandSpacing - If the assembler syntax uses a columnar 563 // layout, the asmwriter can actually generate output in this columns (in 564 // verbose-asm mode). These two values indicate the width of the first column 565 // (the "opcode" area) and the width to reserve for subsequent operands. When 566 // verbose asm mode is enabled, operands will be indented to respect this. 567 int FirstOperandColumn = -1; 568 569 // OperandSpacing - Space between operand columns. 570 int OperandSpacing = -1; 571} 572def DefaultAsmWriter : AsmWriter; 573 574 575//===----------------------------------------------------------------------===// 576// Target - This class contains the "global" target information 577// 578class Target { 579 // InstructionSet - Instruction set description for this target. 580 InstrInfo InstructionSet; 581 582 // AssemblyParsers - The AsmParser instances available for this target. 583 list<AsmParser> AssemblyParsers = [DefaultAsmParser]; 584 585 // AssemblyWriters - The AsmWriter instances available for this target. 586 list<AsmWriter> AssemblyWriters = [DefaultAsmWriter]; 587} 588 589//===----------------------------------------------------------------------===// 590// SubtargetFeature - A characteristic of the chip set. 591// 592class SubtargetFeature<string n, string a, string v, string d, 593 list<SubtargetFeature> i = []> { 594 // Name - Feature name. Used by command line (-mattr=) to determine the 595 // appropriate target chip. 596 // 597 string Name = n; 598 599 // Attribute - Attribute to be set by feature. 600 // 601 string Attribute = a; 602 603 // Value - Value the attribute to be set to by feature. 604 // 605 string Value = v; 606 607 // Desc - Feature description. Used by command line (-mattr=) to display help 608 // information. 609 // 610 string Desc = d; 611 612 // Implies - Features that this feature implies are present. If one of those 613 // features isn't set, then this one shouldn't be set either. 614 // 615 list<SubtargetFeature> Implies = i; 616} 617 618//===----------------------------------------------------------------------===// 619// Processor chip sets - These values represent each of the chip sets supported 620// by the scheduler. Each Processor definition requires corresponding 621// instruction itineraries. 622// 623class Processor<string n, ProcessorItineraries pi, list<SubtargetFeature> f> { 624 // Name - Chip set name. Used by command line (-mcpu=) to determine the 625 // appropriate target chip. 626 // 627 string Name = n; 628 629 // ProcItin - The scheduling information for the target processor. 630 // 631 ProcessorItineraries ProcItin = pi; 632 633 // Features - list of 634 list<SubtargetFeature> Features = f; 635} 636 637//===----------------------------------------------------------------------===// 638// Pull in the common support for calling conventions. 639// 640include "llvm/Target/TargetCallingConv.td" 641 642//===----------------------------------------------------------------------===// 643// Pull in the common support for DAG isel generation. 644// 645include "llvm/Target/TargetSelectionDAG.td" 646