Target.td revision 7a067cc6e0b980b186696c13fe847929fbc0d373
1//===- Target.td - Target Independent TableGen interface ---*- tablegen -*-===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This file defines the target-independent interfaces which should be 11// implemented by each target which is using a TableGen based code generator. 12// 13//===----------------------------------------------------------------------===// 14 15// Include all information about LLVM intrinsics. 16include "llvm/Intrinsics.td" 17 18//===----------------------------------------------------------------------===// 19// Register file description - These classes are used to fill in the target 20// description classes. 21 22class RegisterClass; // Forward def 23 24// SubRegIndex - Use instances of SubRegIndex to identify subregisters. 25class SubRegIndex { 26 string Namespace = ""; 27} 28 29// Register - You should define one instance of this class for each register 30// in the target machine. String n will become the "name" of the register. 31class Register<string n> { 32 string Namespace = ""; 33 string AsmName = n; 34 35 // Aliases - A list of registers that this register overlaps with. A read or 36 // modification of this register can potentially read or modify the aliased 37 // registers. 38 list<Register> Aliases = []; 39 40 // SubRegs - A list of registers that are parts of this register. Note these 41 // are "immediate" sub-registers and the registers within the list do not 42 // themselves overlap. e.g. For X86, EAX's SubRegs list contains only [AX], 43 // not [AX, AH, AL]. 44 list<Register> SubRegs = []; 45 46 // SubRegIndices - For each register in SubRegs, specify the SubRegIndex used 47 // to address it. Sub-sub-register indices are automatically inherited from 48 // SubRegs. 49 list<SubRegIndex> SubRegIndices = []; 50 51 // CompositeIndices - Specify subreg indices that don't correspond directly to 52 // a register in SubRegs and are not inherited. The following formats are 53 // supported: 54 // 55 // (a) Identity - Reg:a == Reg 56 // (a b) Alias - Reg:a == Reg:b 57 // (a b,c) Composite - Reg:a == (Reg:b):c 58 // 59 // This can be used to disambiguate a sub-sub-register that exists in more 60 // than one subregister and other weird stuff. 61 list<dag> CompositeIndices = []; 62 63 // DwarfNumbers - Numbers used internally by gcc/gdb to identify the register. 64 // These values can be determined by locating the <target>.h file in the 65 // directory llvmgcc/gcc/config/<target>/ and looking for REGISTER_NAMES. The 66 // order of these names correspond to the enumeration used by gcc. A value of 67 // -1 indicates that the gcc number is undefined and -2 that register number 68 // is invalid for this mode/flavour. 69 list<int> DwarfNumbers = []; 70 71 // CostPerUse - Additional cost of instructions using this register compared 72 // to other registers in its class. The register allocator will try to 73 // minimize the number of instructions using a register with a CostPerUse. 74 // This is used by the x86-64 and ARM Thumb targets where some registers 75 // require larger instruction encodings. 76 int CostPerUse = 0; 77} 78 79// RegisterWithSubRegs - This can be used to define instances of Register which 80// need to specify sub-registers. 81// List "subregs" specifies which registers are sub-registers to this one. This 82// is used to populate the SubRegs and AliasSet fields of TargetRegisterDesc. 83// This allows the code generator to be careful not to put two values with 84// overlapping live ranges into registers which alias. 85class RegisterWithSubRegs<string n, list<Register> subregs> : Register<n> { 86 let SubRegs = subregs; 87} 88 89// RegisterClass - Now that all of the registers are defined, and aliases 90// between registers are defined, specify which registers belong to which 91// register classes. This also defines the default allocation order of 92// registers by register allocators. 93// 94class RegisterClass<string namespace, list<ValueType> regTypes, int alignment, 95 list<Register> regList> { 96 string Namespace = namespace; 97 98 // RegType - Specify the list ValueType of the registers in this register 99 // class. Note that all registers in a register class must have the same 100 // ValueTypes. This is a list because some targets permit storing different 101 // types in same register, for example vector values with 128-bit total size, 102 // but different count/size of items, like SSE on x86. 103 // 104 list<ValueType> RegTypes = regTypes; 105 106 // Size - Specify the spill size in bits of the registers. A default value of 107 // zero lets tablgen pick an appropriate size. 108 int Size = 0; 109 110 // Alignment - Specify the alignment required of the registers when they are 111 // stored or loaded to memory. 112 // 113 int Alignment = alignment; 114 115 // CopyCost - This value is used to specify the cost of copying a value 116 // between two registers in this register class. The default value is one 117 // meaning it takes a single instruction to perform the copying. A negative 118 // value means copying is extremely expensive or impossible. 119 int CopyCost = 1; 120 121 // MemberList - Specify which registers are in this class. If the 122 // allocation_order_* method are not specified, this also defines the order of 123 // allocation used by the register allocator. 124 // 125 list<Register> MemberList = regList; 126 127 // SubRegClasses - Specify the register class of subregisters as a list of 128 // dags: (RegClass SubRegIndex, SubRegindex, ...) 129 list<dag> SubRegClasses = []; 130 131 // MethodProtos/MethodBodies - These members can be used to insert arbitrary 132 // code into a generated register class. The normal usage of this is to 133 // overload virtual methods. 134 code MethodProtos = [{}]; 135 code MethodBodies = [{}]; 136} 137 138 139//===----------------------------------------------------------------------===// 140// DwarfRegNum - This class provides a mapping of the llvm register enumeration 141// to the register numbering used by gcc and gdb. These values are used by a 142// debug information writer to describe where values may be located during 143// execution. 144class DwarfRegNum<list<int> Numbers> { 145 // DwarfNumbers - Numbers used internally by gcc/gdb to identify the register. 146 // These values can be determined by locating the <target>.h file in the 147 // directory llvmgcc/gcc/config/<target>/ and looking for REGISTER_NAMES. The 148 // order of these names correspond to the enumeration used by gcc. A value of 149 // -1 indicates that the gcc number is undefined and -2 that register number 150 // is invalid for this mode/flavour. 151 list<int> DwarfNumbers = Numbers; 152} 153 154// DwarfRegAlias - This class declares that a given register uses the same dwarf 155// numbers as another one. This is useful for making it clear that the two 156// registers do have the same number. It also lets us build a mapping 157// from dwarf register number to llvm register. 158class DwarfRegAlias<Register reg> { 159 Register DwarfAlias = reg; 160} 161 162//===----------------------------------------------------------------------===// 163// Pull in the common support for scheduling 164// 165include "llvm/Target/TargetSchedule.td" 166 167class Predicate; // Forward def 168 169//===----------------------------------------------------------------------===// 170// Instruction set description - These classes correspond to the C++ classes in 171// the Target/TargetInstrInfo.h file. 172// 173class Instruction { 174 string Namespace = ""; 175 176 dag OutOperandList; // An dag containing the MI def operand list. 177 dag InOperandList; // An dag containing the MI use operand list. 178 string AsmString = ""; // The .s format to print the instruction with. 179 180 // Pattern - Set to the DAG pattern for this instruction, if we know of one, 181 // otherwise, uninitialized. 182 list<dag> Pattern; 183 184 // The follow state will eventually be inferred automatically from the 185 // instruction pattern. 186 187 list<Register> Uses = []; // Default to using no non-operand registers 188 list<Register> Defs = []; // Default to modifying no non-operand registers 189 190 // Predicates - List of predicates which will be turned into isel matching 191 // code. 192 list<Predicate> Predicates = []; 193 194 // Code size. 195 int CodeSize = 0; 196 197 // Added complexity passed onto matching pattern. 198 int AddedComplexity = 0; 199 200 // These bits capture information about the high-level semantics of the 201 // instruction. 202 bit isReturn = 0; // Is this instruction a return instruction? 203 bit isBranch = 0; // Is this instruction a branch instruction? 204 bit isIndirectBranch = 0; // Is this instruction an indirect branch? 205 bit isCompare = 0; // Is this instruction a comparison instruction? 206 bit isMoveImm = 0; // Is this instruction a move immediate instruction? 207 bit isBitcast = 0; // Is this instruction a bitcast instruction? 208 bit isBarrier = 0; // Can control flow fall through this instruction? 209 bit isCall = 0; // Is this instruction a call instruction? 210 bit canFoldAsLoad = 0; // Can this be folded as a simple memory operand? 211 bit mayLoad = 0; // Is it possible for this inst to read memory? 212 bit mayStore = 0; // Is it possible for this inst to write memory? 213 bit isConvertibleToThreeAddress = 0; // Can this 2-addr instruction promote? 214 bit isCommutable = 0; // Is this 3 operand instruction commutable? 215 bit isTerminator = 0; // Is this part of the terminator for a basic block? 216 bit isReMaterializable = 0; // Is this instruction re-materializable? 217 bit isPredicable = 0; // Is this instruction predicable? 218 bit hasDelaySlot = 0; // Does this instruction have an delay slot? 219 bit usesCustomInserter = 0; // Pseudo instr needing special help. 220 bit hasCtrlDep = 0; // Does this instruction r/w ctrl-flow chains? 221 bit isNotDuplicable = 0; // Is it unsafe to duplicate this instruction? 222 bit isAsCheapAsAMove = 0; // As cheap (or cheaper) than a move instruction. 223 bit hasExtraSrcRegAllocReq = 0; // Sources have special regalloc requirement? 224 bit hasExtraDefRegAllocReq = 0; // Defs have special regalloc requirement? 225 226 // Side effect flags - When set, the flags have these meanings: 227 // 228 // hasSideEffects - The instruction has side effects that are not 229 // captured by any operands of the instruction or other flags. 230 // 231 // neverHasSideEffects - Set on an instruction with no pattern if it has no 232 // side effects. 233 bit hasSideEffects = 0; 234 bit neverHasSideEffects = 0; 235 236 // Is this instruction a "real" instruction (with a distinct machine 237 // encoding), or is it a pseudo instruction used for codegen modeling 238 // purposes. 239 bit isCodeGenOnly = 0; 240 241 // Is this instruction a pseudo instruction for use by the assembler parser. 242 bit isAsmParserOnly = 0; 243 244 InstrItinClass Itinerary = NoItinerary;// Execution steps used for scheduling. 245 246 string Constraints = ""; // OperandConstraint, e.g. $src = $dst. 247 248 /// DisableEncoding - List of operand names (e.g. "$op1,$op2") that should not 249 /// be encoded into the output machineinstr. 250 string DisableEncoding = ""; 251 252 string PostEncoderMethod = ""; 253 string DecoderMethod = ""; 254 255 /// Target-specific flags. This becomes the TSFlags field in TargetInstrDesc. 256 bits<64> TSFlags = 0; 257 258 ///@name Assembler Parser Support 259 ///@{ 260 261 string AsmMatchConverter = ""; 262 263 ///@} 264} 265 266/// Predicates - These are extra conditionals which are turned into instruction 267/// selector matching code. Currently each predicate is just a string. 268class Predicate<string cond> { 269 string CondString = cond; 270 271 /// AssemblerMatcherPredicate - If this feature can be used by the assembler 272 /// matcher, this is true. Targets should set this by inheriting their 273 /// feature from the AssemblerPredicate class in addition to Predicate. 274 bit AssemblerMatcherPredicate = 0; 275} 276 277/// NoHonorSignDependentRounding - This predicate is true if support for 278/// sign-dependent-rounding is not enabled. 279def NoHonorSignDependentRounding 280 : Predicate<"!HonorSignDependentRoundingFPMath()">; 281 282class Requires<list<Predicate> preds> { 283 list<Predicate> Predicates = preds; 284} 285 286/// ops definition - This is just a simple marker used to identify the operand 287/// list for an instruction. outs and ins are identical both syntactically and 288/// semanticallyr; they are used to define def operands and use operands to 289/// improve readibility. This should be used like this: 290/// (outs R32:$dst), (ins R32:$src1, R32:$src2) or something similar. 291def ops; 292def outs; 293def ins; 294 295/// variable_ops definition - Mark this instruction as taking a variable number 296/// of operands. 297def variable_ops; 298 299 300/// PointerLikeRegClass - Values that are designed to have pointer width are 301/// derived from this. TableGen treats the register class as having a symbolic 302/// type that it doesn't know, and resolves the actual regclass to use by using 303/// the TargetRegisterInfo::getPointerRegClass() hook at codegen time. 304class PointerLikeRegClass<int Kind> { 305 int RegClassKind = Kind; 306} 307 308 309/// ptr_rc definition - Mark this operand as being a pointer value whose 310/// register class is resolved dynamically via a callback to TargetInstrInfo. 311/// FIXME: We should probably change this to a class which contain a list of 312/// flags. But currently we have but one flag. 313def ptr_rc : PointerLikeRegClass<0>; 314 315/// unknown definition - Mark this operand as being of unknown type, causing 316/// it to be resolved by inference in the context it is used. 317def unknown; 318 319/// AsmOperandClass - Representation for the kinds of operands which the target 320/// specific parser can create and the assembly matcher may need to distinguish. 321/// 322/// Operand classes are used to define the order in which instructions are 323/// matched, to ensure that the instruction which gets matched for any 324/// particular list of operands is deterministic. 325/// 326/// The target specific parser must be able to classify a parsed operand into a 327/// unique class which does not partially overlap with any other classes. It can 328/// match a subset of some other class, in which case the super class field 329/// should be defined. 330class AsmOperandClass { 331 /// The name to use for this class, which should be usable as an enum value. 332 string Name = ?; 333 334 /// The super classes of this operand. 335 list<AsmOperandClass> SuperClasses = []; 336 337 /// The name of the method on the target specific operand to call to test 338 /// whether the operand is an instance of this class. If not set, this will 339 /// default to "isFoo", where Foo is the AsmOperandClass name. The method 340 /// signature should be: 341 /// bool isFoo() const; 342 string PredicateMethod = ?; 343 344 /// The name of the method on the target specific operand to call to add the 345 /// target specific operand to an MCInst. If not set, this will default to 346 /// "addFooOperands", where Foo is the AsmOperandClass name. The method 347 /// signature should be: 348 /// void addFooOperands(MCInst &Inst, unsigned N) const; 349 string RenderMethod = ?; 350 351 /// The name of the method on the target specific operand to call to custom 352 /// handle the operand parsing. This is useful when the operands do not relate 353 /// to immediates or registers and are very instruction specific (as flags to 354 /// set in a processor register, coprocessor number, ...). 355 string ParserMethod = ?; 356} 357 358def ImmAsmOperand : AsmOperandClass { 359 let Name = "Imm"; 360} 361 362/// Operand Types - These provide the built-in operand types that may be used 363/// by a target. Targets can optionally provide their own operand types as 364/// needed, though this should not be needed for RISC targets. 365class Operand<ValueType ty> { 366 ValueType Type = ty; 367 string PrintMethod = "printOperand"; 368 string EncoderMethod = ""; 369 string DecoderMethod = ""; 370 string AsmOperandLowerMethod = ?; 371 dag MIOperandInfo = (ops); 372 373 // ParserMatchClass - The "match class" that operands of this type fit 374 // in. Match classes are used to define the order in which instructions are 375 // match, to ensure that which instructions gets matched is deterministic. 376 // 377 // The target specific parser must be able to classify an parsed operand into 378 // a unique class, which does not partially overlap with any other classes. It 379 // can match a subset of some other class, in which case the AsmOperandClass 380 // should declare the other operand as one of its super classes. 381 AsmOperandClass ParserMatchClass = ImmAsmOperand; 382} 383 384def i1imm : Operand<i1>; 385def i8imm : Operand<i8>; 386def i16imm : Operand<i16>; 387def i32imm : Operand<i32>; 388def i64imm : Operand<i64>; 389 390def f32imm : Operand<f32>; 391def f64imm : Operand<f64>; 392 393/// zero_reg definition - Special node to stand for the zero register. 394/// 395def zero_reg; 396 397/// PredicateOperand - This can be used to define a predicate operand for an 398/// instruction. OpTypes specifies the MIOperandInfo for the operand, and 399/// AlwaysVal specifies the value of this predicate when set to "always 400/// execute". 401class PredicateOperand<ValueType ty, dag OpTypes, dag AlwaysVal> 402 : Operand<ty> { 403 let MIOperandInfo = OpTypes; 404 dag DefaultOps = AlwaysVal; 405} 406 407/// OptionalDefOperand - This is used to define a optional definition operand 408/// for an instruction. DefaultOps is the register the operand represents if 409/// none is supplied, e.g. zero_reg. 410class OptionalDefOperand<ValueType ty, dag OpTypes, dag defaultops> 411 : Operand<ty> { 412 let MIOperandInfo = OpTypes; 413 dag DefaultOps = defaultops; 414} 415 416 417// InstrInfo - This class should only be instantiated once to provide parameters 418// which are global to the target machine. 419// 420class InstrInfo { 421 // Target can specify its instructions in either big or little-endian formats. 422 // For instance, while both Sparc and PowerPC are big-endian platforms, the 423 // Sparc manual specifies its instructions in the format [31..0] (big), while 424 // PowerPC specifies them using the format [0..31] (little). 425 bit isLittleEndianEncoding = 0; 426} 427 428// Standard Pseudo Instructions. 429// This list must match TargetOpcodes.h and CodeGenTarget.cpp. 430// Only these instructions are allowed in the TargetOpcode namespace. 431let isCodeGenOnly = 1, Namespace = "TargetOpcode" in { 432def PHI : Instruction { 433 let OutOperandList = (outs); 434 let InOperandList = (ins variable_ops); 435 let AsmString = "PHINODE"; 436} 437def INLINEASM : Instruction { 438 let OutOperandList = (outs); 439 let InOperandList = (ins variable_ops); 440 let AsmString = ""; 441 let neverHasSideEffects = 1; // Note side effect is encoded in an operand. 442} 443def PROLOG_LABEL : Instruction { 444 let OutOperandList = (outs); 445 let InOperandList = (ins i32imm:$id); 446 let AsmString = ""; 447 let hasCtrlDep = 1; 448 let isNotDuplicable = 1; 449} 450def EH_LABEL : Instruction { 451 let OutOperandList = (outs); 452 let InOperandList = (ins i32imm:$id); 453 let AsmString = ""; 454 let hasCtrlDep = 1; 455 let isNotDuplicable = 1; 456} 457def GC_LABEL : Instruction { 458 let OutOperandList = (outs); 459 let InOperandList = (ins i32imm:$id); 460 let AsmString = ""; 461 let hasCtrlDep = 1; 462 let isNotDuplicable = 1; 463} 464def KILL : Instruction { 465 let OutOperandList = (outs); 466 let InOperandList = (ins variable_ops); 467 let AsmString = ""; 468 let neverHasSideEffects = 1; 469} 470def EXTRACT_SUBREG : Instruction { 471 let OutOperandList = (outs unknown:$dst); 472 let InOperandList = (ins unknown:$supersrc, i32imm:$subidx); 473 let AsmString = ""; 474 let neverHasSideEffects = 1; 475} 476def INSERT_SUBREG : Instruction { 477 let OutOperandList = (outs unknown:$dst); 478 let InOperandList = (ins unknown:$supersrc, unknown:$subsrc, i32imm:$subidx); 479 let AsmString = ""; 480 let neverHasSideEffects = 1; 481 let Constraints = "$supersrc = $dst"; 482} 483def IMPLICIT_DEF : Instruction { 484 let OutOperandList = (outs unknown:$dst); 485 let InOperandList = (ins); 486 let AsmString = ""; 487 let neverHasSideEffects = 1; 488 let isReMaterializable = 1; 489 let isAsCheapAsAMove = 1; 490} 491def SUBREG_TO_REG : Instruction { 492 let OutOperandList = (outs unknown:$dst); 493 let InOperandList = (ins unknown:$implsrc, unknown:$subsrc, i32imm:$subidx); 494 let AsmString = ""; 495 let neverHasSideEffects = 1; 496} 497def COPY_TO_REGCLASS : Instruction { 498 let OutOperandList = (outs unknown:$dst); 499 let InOperandList = (ins unknown:$src, i32imm:$regclass); 500 let AsmString = ""; 501 let neverHasSideEffects = 1; 502 let isAsCheapAsAMove = 1; 503} 504def DBG_VALUE : Instruction { 505 let OutOperandList = (outs); 506 let InOperandList = (ins variable_ops); 507 let AsmString = "DBG_VALUE"; 508 let neverHasSideEffects = 1; 509} 510def REG_SEQUENCE : Instruction { 511 let OutOperandList = (outs unknown:$dst); 512 let InOperandList = (ins variable_ops); 513 let AsmString = ""; 514 let neverHasSideEffects = 1; 515 let isAsCheapAsAMove = 1; 516} 517def COPY : Instruction { 518 let OutOperandList = (outs unknown:$dst); 519 let InOperandList = (ins unknown:$src); 520 let AsmString = ""; 521 let neverHasSideEffects = 1; 522 let isAsCheapAsAMove = 1; 523} 524} 525 526//===----------------------------------------------------------------------===// 527// AsmParser - This class can be implemented by targets that wish to implement 528// .s file parsing. 529// 530// Subtargets can have multiple different assembly parsers (e.g. AT&T vs Intel 531// syntax on X86 for example). 532// 533class AsmParser { 534 // AsmParserClassName - This specifies the suffix to use for the asmparser 535 // class. Generated AsmParser classes are always prefixed with the target 536 // name. 537 string AsmParserClassName = "AsmParser"; 538 539 // AsmParserInstCleanup - If non-empty, this is the name of a custom member 540 // function of the AsmParser class to call on every matched instruction. 541 // This can be used to perform target specific instruction post-processing. 542 string AsmParserInstCleanup = ""; 543 544 // Variant - AsmParsers can be of multiple different variants. Variants are 545 // used to support targets that need to parser multiple formats for the 546 // assembly language. 547 int Variant = 0; 548 549 // CommentDelimiter - If given, the delimiter string used to recognize 550 // comments which are hard coded in the .td assembler strings for individual 551 // instructions. 552 string CommentDelimiter = ""; 553 554 // RegisterPrefix - If given, the token prefix which indicates a register 555 // token. This is used by the matcher to automatically recognize hard coded 556 // register tokens as constrained registers, instead of tokens, for the 557 // purposes of matching. 558 string RegisterPrefix = ""; 559} 560def DefaultAsmParser : AsmParser; 561 562/// AssemblerPredicate - This is a Predicate that can be used when the assembler 563/// matches instructions and aliases. 564class AssemblerPredicate { 565 bit AssemblerMatcherPredicate = 1; 566} 567 568 569 570/// MnemonicAlias - This class allows targets to define assembler mnemonic 571/// aliases. This should be used when all forms of one mnemonic are accepted 572/// with a different mnemonic. For example, X86 allows: 573/// sal %al, 1 -> shl %al, 1 574/// sal %ax, %cl -> shl %ax, %cl 575/// sal %eax, %cl -> shl %eax, %cl 576/// etc. Though "sal" is accepted with many forms, all of them are directly 577/// translated to a shl, so it can be handled with (in the case of X86, it 578/// actually has one for each suffix as well): 579/// def : MnemonicAlias<"sal", "shl">; 580/// 581/// Mnemonic aliases are mapped before any other translation in the match phase, 582/// and do allow Requires predicates, e.g.: 583/// 584/// def : MnemonicAlias<"pushf", "pushfq">, Requires<[In64BitMode]>; 585/// def : MnemonicAlias<"pushf", "pushfl">, Requires<[In32BitMode]>; 586/// 587class MnemonicAlias<string From, string To> { 588 string FromMnemonic = From; 589 string ToMnemonic = To; 590 591 // Predicates - Predicates that must be true for this remapping to happen. 592 list<Predicate> Predicates = []; 593} 594 595/// InstAlias - This defines an alternate assembly syntax that is allowed to 596/// match an instruction that has a different (more canonical) assembly 597/// representation. 598class InstAlias<string Asm, dag Result, bit Emit = 0b1> { 599 string AsmString = Asm; // The .s format to match the instruction with. 600 dag ResultInst = Result; // The MCInst to generate. 601 bit EmitAlias = Emit; // Emit the alias instead of what's aliased. 602 603 // Predicates - Predicates that must be true for this to match. 604 list<Predicate> Predicates = []; 605} 606 607//===----------------------------------------------------------------------===// 608// AsmWriter - This class can be implemented by targets that need to customize 609// the format of the .s file writer. 610// 611// Subtargets can have multiple different asmwriters (e.g. AT&T vs Intel syntax 612// on X86 for example). 613// 614class AsmWriter { 615 // AsmWriterClassName - This specifies the suffix to use for the asmwriter 616 // class. Generated AsmWriter classes are always prefixed with the target 617 // name. 618 string AsmWriterClassName = "AsmPrinter"; 619 620 // Variant - AsmWriters can be of multiple different variants. Variants are 621 // used to support targets that need to emit assembly code in ways that are 622 // mostly the same for different targets, but have minor differences in 623 // syntax. If the asmstring contains {|} characters in them, this integer 624 // will specify which alternative to use. For example "{x|y|z}" with Variant 625 // == 1, will expand to "y". 626 int Variant = 0; 627 628 629 // FirstOperandColumn/OperandSpacing - If the assembler syntax uses a columnar 630 // layout, the asmwriter can actually generate output in this columns (in 631 // verbose-asm mode). These two values indicate the width of the first column 632 // (the "opcode" area) and the width to reserve for subsequent operands. When 633 // verbose asm mode is enabled, operands will be indented to respect this. 634 int FirstOperandColumn = -1; 635 636 // OperandSpacing - Space between operand columns. 637 int OperandSpacing = -1; 638 639 // isMCAsmWriter - Is this assembly writer for an MC emitter? This controls 640 // generation of the printInstruction() method. For MC printers, it takes 641 // an MCInstr* operand, otherwise it takes a MachineInstr*. 642 bit isMCAsmWriter = 0; 643} 644def DefaultAsmWriter : AsmWriter; 645 646 647//===----------------------------------------------------------------------===// 648// Target - This class contains the "global" target information 649// 650class Target { 651 // InstructionSet - Instruction set description for this target. 652 InstrInfo InstructionSet; 653 654 // AssemblyParsers - The AsmParser instances available for this target. 655 list<AsmParser> AssemblyParsers = [DefaultAsmParser]; 656 657 // AssemblyWriters - The AsmWriter instances available for this target. 658 list<AsmWriter> AssemblyWriters = [DefaultAsmWriter]; 659} 660 661//===----------------------------------------------------------------------===// 662// SubtargetFeature - A characteristic of the chip set. 663// 664class SubtargetFeature<string n, string a, string v, string d, 665 list<SubtargetFeature> i = []> { 666 // Name - Feature name. Used by command line (-mattr=) to determine the 667 // appropriate target chip. 668 // 669 string Name = n; 670 671 // Attribute - Attribute to be set by feature. 672 // 673 string Attribute = a; 674 675 // Value - Value the attribute to be set to by feature. 676 // 677 string Value = v; 678 679 // Desc - Feature description. Used by command line (-mattr=) to display help 680 // information. 681 // 682 string Desc = d; 683 684 // Implies - Features that this feature implies are present. If one of those 685 // features isn't set, then this one shouldn't be set either. 686 // 687 list<SubtargetFeature> Implies = i; 688} 689 690//===----------------------------------------------------------------------===// 691// Processor chip sets - These values represent each of the chip sets supported 692// by the scheduler. Each Processor definition requires corresponding 693// instruction itineraries. 694// 695class Processor<string n, ProcessorItineraries pi, list<SubtargetFeature> f> { 696 // Name - Chip set name. Used by command line (-mcpu=) to determine the 697 // appropriate target chip. 698 // 699 string Name = n; 700 701 // ProcItin - The scheduling information for the target processor. 702 // 703 ProcessorItineraries ProcItin = pi; 704 705 // Features - list of 706 list<SubtargetFeature> Features = f; 707} 708 709//===----------------------------------------------------------------------===// 710// Pull in the common support for calling conventions. 711// 712include "llvm/Target/TargetCallingConv.td" 713 714//===----------------------------------------------------------------------===// 715// Pull in the common support for DAG isel generation. 716// 717include "llvm/Target/TargetSelectionDAG.td" 718