Target.td revision c1f10fd5b9a780d1c42dca7143d7a8acd9bd9377
1//===- Target.td - Target Independent TableGen interface ---*- tablegen -*-===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This file defines the target-independent interfaces which should be 11// implemented by each target which is using a TableGen based code generator. 12// 13//===----------------------------------------------------------------------===// 14 15// Include all information about LLVM intrinsics. 16include "llvm/Intrinsics.td" 17 18//===----------------------------------------------------------------------===// 19// Register file description - These classes are used to fill in the target 20// description classes. 21 22class RegisterClass; // Forward def 23 24// SubRegIndex - Use instances of SubRegIndex to identify subregisters. 25class SubRegIndex<list<SubRegIndex> comps = []> { 26 string Namespace = ""; 27 28 // ComposedOf - A list of two SubRegIndex instances, [A, B]. 29 // This indicates that this SubRegIndex is the result of composing A and B. 30 list<SubRegIndex> ComposedOf = comps; 31 32 // CoveringSubRegIndices - A list of two or more sub-register indexes that 33 // cover this sub-register. 34 // 35 // This field should normally be left blank as TableGen can infer it. 36 // 37 // TableGen automatically detects sub-registers that straddle the registers 38 // in the SubRegs field of a Register definition. For example: 39 // 40 // Q0 = dsub_0 -> D0, dsub_1 -> D1 41 // Q1 = dsub_0 -> D2, dsub_1 -> D3 42 // D1_D2 = dsub_0 -> D1, dsub_1 -> D2 43 // QQ0 = qsub_0 -> Q0, qsub_1 -> Q1 44 // 45 // TableGen will infer that D1_D2 is a sub-register of QQ0. It will be given 46 // the synthetic index dsub_1_dsub_2 unless some SubRegIndex is defined with 47 // CoveringSubRegIndices = [dsub_1, dsub_2]. 48 list<SubRegIndex> CoveringSubRegIndices = []; 49} 50 51// RegAltNameIndex - The alternate name set to use for register operands of 52// this register class when printing. 53class RegAltNameIndex { 54 string Namespace = ""; 55} 56def NoRegAltName : RegAltNameIndex; 57 58// Register - You should define one instance of this class for each register 59// in the target machine. String n will become the "name" of the register. 60class Register<string n, list<string> altNames = []> { 61 string Namespace = ""; 62 string AsmName = n; 63 list<string> AltNames = altNames; 64 65 // Aliases - A list of registers that this register overlaps with. A read or 66 // modification of this register can potentially read or modify the aliased 67 // registers. 68 list<Register> Aliases = []; 69 70 // SubRegs - A list of registers that are parts of this register. Note these 71 // are "immediate" sub-registers and the registers within the list do not 72 // themselves overlap. e.g. For X86, EAX's SubRegs list contains only [AX], 73 // not [AX, AH, AL]. 74 list<Register> SubRegs = []; 75 76 // SubRegIndices - For each register in SubRegs, specify the SubRegIndex used 77 // to address it. Sub-sub-register indices are automatically inherited from 78 // SubRegs. 79 list<SubRegIndex> SubRegIndices = []; 80 81 // RegAltNameIndices - The alternate name indices which are valid for this 82 // register. 83 list<RegAltNameIndex> RegAltNameIndices = []; 84 85 // DwarfNumbers - Numbers used internally by gcc/gdb to identify the register. 86 // These values can be determined by locating the <target>.h file in the 87 // directory llvmgcc/gcc/config/<target>/ and looking for REGISTER_NAMES. The 88 // order of these names correspond to the enumeration used by gcc. A value of 89 // -1 indicates that the gcc number is undefined and -2 that register number 90 // is invalid for this mode/flavour. 91 list<int> DwarfNumbers = []; 92 93 // CostPerUse - Additional cost of instructions using this register compared 94 // to other registers in its class. The register allocator will try to 95 // minimize the number of instructions using a register with a CostPerUse. 96 // This is used by the x86-64 and ARM Thumb targets where some registers 97 // require larger instruction encodings. 98 int CostPerUse = 0; 99 100 // CoveredBySubRegs - When this bit is set, the value of this register is 101 // completely determined by the value of its sub-registers. For example, the 102 // x86 register AX is covered by its sub-registers AL and AH, but EAX is not 103 // covered by its sub-register AX. 104 bit CoveredBySubRegs = 0; 105 106 // HWEncoding - The target specific hardware encoding for this register. 107 bits<16> HWEncoding = 0; 108} 109 110// RegisterWithSubRegs - This can be used to define instances of Register which 111// need to specify sub-registers. 112// List "subregs" specifies which registers are sub-registers to this one. This 113// is used to populate the SubRegs and AliasSet fields of TargetRegisterDesc. 114// This allows the code generator to be careful not to put two values with 115// overlapping live ranges into registers which alias. 116class RegisterWithSubRegs<string n, list<Register> subregs> : Register<n> { 117 let SubRegs = subregs; 118} 119 120// DAGOperand - An empty base class that unifies RegisterClass's and other forms 121// of Operand's that are legal as type qualifiers in DAG patterns. This should 122// only ever be used for defining multiclasses that are polymorphic over both 123// RegisterClass's and other Operand's. 124class DAGOperand { } 125 126// RegisterClass - Now that all of the registers are defined, and aliases 127// between registers are defined, specify which registers belong to which 128// register classes. This also defines the default allocation order of 129// registers by register allocators. 130// 131class RegisterClass<string namespace, list<ValueType> regTypes, int alignment, 132 dag regList, RegAltNameIndex idx = NoRegAltName> 133 : DAGOperand { 134 string Namespace = namespace; 135 136 // RegType - Specify the list ValueType of the registers in this register 137 // class. Note that all registers in a register class must have the same 138 // ValueTypes. This is a list because some targets permit storing different 139 // types in same register, for example vector values with 128-bit total size, 140 // but different count/size of items, like SSE on x86. 141 // 142 list<ValueType> RegTypes = regTypes; 143 144 // Size - Specify the spill size in bits of the registers. A default value of 145 // zero lets tablgen pick an appropriate size. 146 int Size = 0; 147 148 // Alignment - Specify the alignment required of the registers when they are 149 // stored or loaded to memory. 150 // 151 int Alignment = alignment; 152 153 // CopyCost - This value is used to specify the cost of copying a value 154 // between two registers in this register class. The default value is one 155 // meaning it takes a single instruction to perform the copying. A negative 156 // value means copying is extremely expensive or impossible. 157 int CopyCost = 1; 158 159 // MemberList - Specify which registers are in this class. If the 160 // allocation_order_* method are not specified, this also defines the order of 161 // allocation used by the register allocator. 162 // 163 dag MemberList = regList; 164 165 // AltNameIndex - The alternate register name to use when printing operands 166 // of this register class. Every register in the register class must have 167 // a valid alternate name for the given index. 168 RegAltNameIndex altNameIndex = idx; 169 170 // isAllocatable - Specify that the register class can be used for virtual 171 // registers and register allocation. Some register classes are only used to 172 // model instruction operand constraints, and should have isAllocatable = 0. 173 bit isAllocatable = 1; 174 175 // AltOrders - List of alternative allocation orders. The default order is 176 // MemberList itself, and that is good enough for most targets since the 177 // register allocators automatically remove reserved registers and move 178 // callee-saved registers to the end. 179 list<dag> AltOrders = []; 180 181 // AltOrderSelect - The body of a function that selects the allocation order 182 // to use in a given machine function. The code will be inserted in a 183 // function like this: 184 // 185 // static inline unsigned f(const MachineFunction &MF) { ... } 186 // 187 // The function should return 0 to select the default order defined by 188 // MemberList, 1 to select the first AltOrders entry and so on. 189 code AltOrderSelect = [{}]; 190} 191 192// The memberList in a RegisterClass is a dag of set operations. TableGen 193// evaluates these set operations and expand them into register lists. These 194// are the most common operation, see test/TableGen/SetTheory.td for more 195// examples of what is possible: 196// 197// (add R0, R1, R2) - Set Union. Each argument can be an individual register, a 198// register class, or a sub-expression. This is also the way to simply list 199// registers. 200// 201// (sub GPR, SP) - Set difference. Subtract the last arguments from the first. 202// 203// (and GPR, CSR) - Set intersection. All registers from the first set that are 204// also in the second set. 205// 206// (sequence "R%u", 0, 15) -> [R0, R1, ..., R15]. Generate a sequence of 207// numbered registers. Takes an optional 4th operand which is a stride to use 208// when generating the sequence. 209// 210// (shl GPR, 4) - Remove the first N elements. 211// 212// (trunc GPR, 4) - Truncate after the first N elements. 213// 214// (rotl GPR, 1) - Rotate N places to the left. 215// 216// (rotr GPR, 1) - Rotate N places to the right. 217// 218// (decimate GPR, 2) - Pick every N'th element, starting with the first. 219// 220// (interleave A, B, ...) - Interleave the elements from each argument list. 221// 222// All of these operators work on ordered sets, not lists. That means 223// duplicates are removed from sub-expressions. 224 225// Set operators. The rest is defined in TargetSelectionDAG.td. 226def sequence; 227def decimate; 228def interleave; 229 230// RegisterTuples - Automatically generate super-registers by forming tuples of 231// sub-registers. This is useful for modeling register sequence constraints 232// with pseudo-registers that are larger than the architectural registers. 233// 234// The sub-register lists are zipped together: 235// 236// def EvenOdd : RegisterTuples<[sube, subo], [(add R0, R2), (add R1, R3)]>; 237// 238// Generates the same registers as: 239// 240// let SubRegIndices = [sube, subo] in { 241// def R0_R1 : RegisterWithSubRegs<"", [R0, R1]>; 242// def R2_R3 : RegisterWithSubRegs<"", [R2, R3]>; 243// } 244// 245// The generated pseudo-registers inherit super-classes and fields from their 246// first sub-register. Most fields from the Register class are inferred, and 247// the AsmName and Dwarf numbers are cleared. 248// 249// RegisterTuples instances can be used in other set operations to form 250// register classes and so on. This is the only way of using the generated 251// registers. 252class RegisterTuples<list<SubRegIndex> Indices, list<dag> Regs> { 253 // SubRegs - N lists of registers to be zipped up. Super-registers are 254 // synthesized from the first element of each SubRegs list, the second 255 // element and so on. 256 list<dag> SubRegs = Regs; 257 258 // SubRegIndices - N SubRegIndex instances. This provides the names of the 259 // sub-registers in the synthesized super-registers. 260 list<SubRegIndex> SubRegIndices = Indices; 261} 262 263 264//===----------------------------------------------------------------------===// 265// DwarfRegNum - This class provides a mapping of the llvm register enumeration 266// to the register numbering used by gcc and gdb. These values are used by a 267// debug information writer to describe where values may be located during 268// execution. 269class DwarfRegNum<list<int> Numbers> { 270 // DwarfNumbers - Numbers used internally by gcc/gdb to identify the register. 271 // These values can be determined by locating the <target>.h file in the 272 // directory llvmgcc/gcc/config/<target>/ and looking for REGISTER_NAMES. The 273 // order of these names correspond to the enumeration used by gcc. A value of 274 // -1 indicates that the gcc number is undefined and -2 that register number 275 // is invalid for this mode/flavour. 276 list<int> DwarfNumbers = Numbers; 277} 278 279// DwarfRegAlias - This class declares that a given register uses the same dwarf 280// numbers as another one. This is useful for making it clear that the two 281// registers do have the same number. It also lets us build a mapping 282// from dwarf register number to llvm register. 283class DwarfRegAlias<Register reg> { 284 Register DwarfAlias = reg; 285} 286 287//===----------------------------------------------------------------------===// 288// Pull in the common support for scheduling 289// 290include "llvm/Target/TargetSchedule.td" 291 292class Predicate; // Forward def 293 294//===----------------------------------------------------------------------===// 295// Instruction set description - These classes correspond to the C++ classes in 296// the Target/TargetInstrInfo.h file. 297// 298class Instruction { 299 string Namespace = ""; 300 301 dag OutOperandList; // An dag containing the MI def operand list. 302 dag InOperandList; // An dag containing the MI use operand list. 303 string AsmString = ""; // The .s format to print the instruction with. 304 305 // Pattern - Set to the DAG pattern for this instruction, if we know of one, 306 // otherwise, uninitialized. 307 list<dag> Pattern; 308 309 // The follow state will eventually be inferred automatically from the 310 // instruction pattern. 311 312 list<Register> Uses = []; // Default to using no non-operand registers 313 list<Register> Defs = []; // Default to modifying no non-operand registers 314 315 // Predicates - List of predicates which will be turned into isel matching 316 // code. 317 list<Predicate> Predicates = []; 318 319 // Size - Size of encoded instruction, or zero if the size cannot be determined 320 // from the opcode. 321 int Size = 0; 322 323 // DecoderNamespace - The "namespace" in which this instruction exists, on 324 // targets like ARM which multiple ISA namespaces exist. 325 string DecoderNamespace = ""; 326 327 // Code size, for instruction selection. 328 // FIXME: What does this actually mean? 329 int CodeSize = 0; 330 331 // Added complexity passed onto matching pattern. 332 int AddedComplexity = 0; 333 334 // These bits capture information about the high-level semantics of the 335 // instruction. 336 bit isReturn = 0; // Is this instruction a return instruction? 337 bit isBranch = 0; // Is this instruction a branch instruction? 338 bit isIndirectBranch = 0; // Is this instruction an indirect branch? 339 bit isCompare = 0; // Is this instruction a comparison instruction? 340 bit isMoveImm = 0; // Is this instruction a move immediate instruction? 341 bit isBitcast = 0; // Is this instruction a bitcast instruction? 342 bit isSelect = 0; // Is this instruction a select instruction? 343 bit isBarrier = 0; // Can control flow fall through this instruction? 344 bit isCall = 0; // Is this instruction a call instruction? 345 bit canFoldAsLoad = 0; // Can this be folded as a simple memory operand? 346 bit mayLoad = ?; // Is it possible for this inst to read memory? 347 bit mayStore = ?; // Is it possible for this inst to write memory? 348 bit isConvertibleToThreeAddress = 0; // Can this 2-addr instruction promote? 349 bit isCommutable = 0; // Is this 3 operand instruction commutable? 350 bit isTerminator = 0; // Is this part of the terminator for a basic block? 351 bit isReMaterializable = 0; // Is this instruction re-materializable? 352 bit isPredicable = 0; // Is this instruction predicable? 353 bit hasDelaySlot = 0; // Does this instruction have an delay slot? 354 bit usesCustomInserter = 0; // Pseudo instr needing special help. 355 bit hasPostISelHook = 0; // To be *adjusted* after isel by target hook. 356 bit hasCtrlDep = 0; // Does this instruction r/w ctrl-flow chains? 357 bit isNotDuplicable = 0; // Is it unsafe to duplicate this instruction? 358 bit isAsCheapAsAMove = 0; // As cheap (or cheaper) than a move instruction. 359 bit hasExtraSrcRegAllocReq = 0; // Sources have special regalloc requirement? 360 bit hasExtraDefRegAllocReq = 0; // Defs have special regalloc requirement? 361 bit isPseudo = 0; // Is this instruction a pseudo-instruction? 362 // If so, won't have encoding information for 363 // the [MC]CodeEmitter stuff. 364 365 // Side effect flags - When set, the flags have these meanings: 366 // 367 // hasSideEffects - The instruction has side effects that are not 368 // captured by any operands of the instruction or other flags. 369 // 370 // neverHasSideEffects - Set on an instruction with no pattern if it has no 371 // side effects. 372 bit hasSideEffects = ?; 373 bit neverHasSideEffects = 0; 374 375 // Is this instruction a "real" instruction (with a distinct machine 376 // encoding), or is it a pseudo instruction used for codegen modeling 377 // purposes. 378 // FIXME: For now this is distinct from isPseudo, above, as code-gen-only 379 // instructions can (and often do) still have encoding information 380 // associated with them. Once we've migrated all of them over to true 381 // pseudo-instructions that are lowered to real instructions prior to 382 // the printer/emitter, we can remove this attribute and just use isPseudo. 383 // 384 // The intended use is: 385 // isPseudo: Does not have encoding information and should be expanded, 386 // at the latest, during lowering to MCInst. 387 // 388 // isCodeGenOnly: Does have encoding information and can go through to the 389 // CodeEmitter unchanged, but duplicates a canonical instruction 390 // definition's encoding and should be ignored when constructing the 391 // assembler match tables. 392 bit isCodeGenOnly = 0; 393 394 // Is this instruction a pseudo instruction for use by the assembler parser. 395 bit isAsmParserOnly = 0; 396 397 InstrItinClass Itinerary = NoItinerary;// Execution steps used for scheduling. 398 399 string Constraints = ""; // OperandConstraint, e.g. $src = $dst. 400 401 /// DisableEncoding - List of operand names (e.g. "$op1,$op2") that should not 402 /// be encoded into the output machineinstr. 403 string DisableEncoding = ""; 404 405 string PostEncoderMethod = ""; 406 string DecoderMethod = ""; 407 408 /// Target-specific flags. This becomes the TSFlags field in TargetInstrDesc. 409 bits<64> TSFlags = 0; 410 411 ///@name Assembler Parser Support 412 ///@{ 413 414 string AsmMatchConverter = ""; 415 416 /// TwoOperandAliasConstraint - Enable TableGen to auto-generate a 417 /// two-operand matcher inst-alias for a three operand instruction. 418 /// For example, the arm instruction "add r3, r3, r5" can be written 419 /// as "add r3, r5". The constraint is of the same form as a tied-operand 420 /// constraint. For example, "$Rn = $Rd". 421 string TwoOperandAliasConstraint = ""; 422 423 ///@} 424} 425 426/// PseudoInstExpansion - Expansion information for a pseudo-instruction. 427/// Which instruction it expands to and how the operands map from the 428/// pseudo. 429class PseudoInstExpansion<dag Result> { 430 dag ResultInst = Result; // The instruction to generate. 431 bit isPseudo = 1; 432} 433 434/// Predicates - These are extra conditionals which are turned into instruction 435/// selector matching code. Currently each predicate is just a string. 436class Predicate<string cond> { 437 string CondString = cond; 438 439 /// AssemblerMatcherPredicate - If this feature can be used by the assembler 440 /// matcher, this is true. Targets should set this by inheriting their 441 /// feature from the AssemblerPredicate class in addition to Predicate. 442 bit AssemblerMatcherPredicate = 0; 443 444 /// AssemblerCondString - Name of the subtarget feature being tested used 445 /// as alternative condition string used for assembler matcher. 446 /// e.g. "ModeThumb" is translated to "(Bits & ModeThumb) != 0". 447 /// "!ModeThumb" is translated to "(Bits & ModeThumb) == 0". 448 /// It can also list multiple features separated by ",". 449 /// e.g. "ModeThumb,FeatureThumb2" is translated to 450 /// "(Bits & ModeThumb) != 0 && (Bits & FeatureThumb2) != 0". 451 string AssemblerCondString = ""; 452 453 /// PredicateName - User-level name to use for the predicate. Mainly for use 454 /// in diagnostics such as missing feature errors in the asm matcher. 455 string PredicateName = ""; 456} 457 458/// NoHonorSignDependentRounding - This predicate is true if support for 459/// sign-dependent-rounding is not enabled. 460def NoHonorSignDependentRounding 461 : Predicate<"!TM.Options.HonorSignDependentRoundingFPMath()">; 462 463class Requires<list<Predicate> preds> { 464 list<Predicate> Predicates = preds; 465} 466 467/// ops definition - This is just a simple marker used to identify the operand 468/// list for an instruction. outs and ins are identical both syntactically and 469/// semanticallyr; they are used to define def operands and use operands to 470/// improve readibility. This should be used like this: 471/// (outs R32:$dst), (ins R32:$src1, R32:$src2) or something similar. 472def ops; 473def outs; 474def ins; 475 476/// variable_ops definition - Mark this instruction as taking a variable number 477/// of operands. 478def variable_ops; 479 480 481/// PointerLikeRegClass - Values that are designed to have pointer width are 482/// derived from this. TableGen treats the register class as having a symbolic 483/// type that it doesn't know, and resolves the actual regclass to use by using 484/// the TargetRegisterInfo::getPointerRegClass() hook at codegen time. 485class PointerLikeRegClass<int Kind> { 486 int RegClassKind = Kind; 487} 488 489 490/// ptr_rc definition - Mark this operand as being a pointer value whose 491/// register class is resolved dynamically via a callback to TargetInstrInfo. 492/// FIXME: We should probably change this to a class which contain a list of 493/// flags. But currently we have but one flag. 494def ptr_rc : PointerLikeRegClass<0>; 495 496/// unknown definition - Mark this operand as being of unknown type, causing 497/// it to be resolved by inference in the context it is used. 498def unknown; 499 500/// AsmOperandClass - Representation for the kinds of operands which the target 501/// specific parser can create and the assembly matcher may need to distinguish. 502/// 503/// Operand classes are used to define the order in which instructions are 504/// matched, to ensure that the instruction which gets matched for any 505/// particular list of operands is deterministic. 506/// 507/// The target specific parser must be able to classify a parsed operand into a 508/// unique class which does not partially overlap with any other classes. It can 509/// match a subset of some other class, in which case the super class field 510/// should be defined. 511class AsmOperandClass { 512 /// The name to use for this class, which should be usable as an enum value. 513 string Name = ?; 514 515 /// The super classes of this operand. 516 list<AsmOperandClass> SuperClasses = []; 517 518 /// The name of the method on the target specific operand to call to test 519 /// whether the operand is an instance of this class. If not set, this will 520 /// default to "isFoo", where Foo is the AsmOperandClass name. The method 521 /// signature should be: 522 /// bool isFoo() const; 523 string PredicateMethod = ?; 524 525 /// The name of the method on the target specific operand to call to add the 526 /// target specific operand to an MCInst. If not set, this will default to 527 /// "addFooOperands", where Foo is the AsmOperandClass name. The method 528 /// signature should be: 529 /// void addFooOperands(MCInst &Inst, unsigned N) const; 530 string RenderMethod = ?; 531 532 /// The name of the method on the target specific operand to call to custom 533 /// handle the operand parsing. This is useful when the operands do not relate 534 /// to immediates or registers and are very instruction specific (as flags to 535 /// set in a processor register, coprocessor number, ...). 536 string ParserMethod = ?; 537 538 // The diagnostic type to present when referencing this operand in a 539 // match failure error message. By default, use a generic "invalid operand" 540 // diagnostic. The target AsmParser maps these codes to text. 541 string DiagnosticType = ""; 542} 543 544def ImmAsmOperand : AsmOperandClass { 545 let Name = "Imm"; 546} 547 548/// Operand Types - These provide the built-in operand types that may be used 549/// by a target. Targets can optionally provide their own operand types as 550/// needed, though this should not be needed for RISC targets. 551class Operand<ValueType ty> : DAGOperand { 552 ValueType Type = ty; 553 string PrintMethod = "printOperand"; 554 string EncoderMethod = ""; 555 string DecoderMethod = ""; 556 string AsmOperandLowerMethod = ?; 557 string OperandType = "OPERAND_UNKNOWN"; 558 dag MIOperandInfo = (ops); 559 560 // ParserMatchClass - The "match class" that operands of this type fit 561 // in. Match classes are used to define the order in which instructions are 562 // match, to ensure that which instructions gets matched is deterministic. 563 // 564 // The target specific parser must be able to classify an parsed operand into 565 // a unique class, which does not partially overlap with any other classes. It 566 // can match a subset of some other class, in which case the AsmOperandClass 567 // should declare the other operand as one of its super classes. 568 AsmOperandClass ParserMatchClass = ImmAsmOperand; 569} 570 571class RegisterOperand<RegisterClass regclass, string pm = "printOperand"> 572 : DAGOperand { 573 // RegClass - The register class of the operand. 574 RegisterClass RegClass = regclass; 575 // PrintMethod - The target method to call to print register operands of 576 // this type. The method normally will just use an alt-name index to look 577 // up the name to print. Default to the generic printOperand(). 578 string PrintMethod = pm; 579 // ParserMatchClass - The "match class" that operands of this type fit 580 // in. Match classes are used to define the order in which instructions are 581 // match, to ensure that which instructions gets matched is deterministic. 582 // 583 // The target specific parser must be able to classify an parsed operand into 584 // a unique class, which does not partially overlap with any other classes. It 585 // can match a subset of some other class, in which case the AsmOperandClass 586 // should declare the other operand as one of its super classes. 587 AsmOperandClass ParserMatchClass; 588} 589 590let OperandType = "OPERAND_IMMEDIATE" in { 591def i1imm : Operand<i1>; 592def i8imm : Operand<i8>; 593def i16imm : Operand<i16>; 594def i32imm : Operand<i32>; 595def i64imm : Operand<i64>; 596 597def f32imm : Operand<f32>; 598def f64imm : Operand<f64>; 599} 600 601/// zero_reg definition - Special node to stand for the zero register. 602/// 603def zero_reg; 604 605/// PredicateOperand - This can be used to define a predicate operand for an 606/// instruction. OpTypes specifies the MIOperandInfo for the operand, and 607/// AlwaysVal specifies the value of this predicate when set to "always 608/// execute". 609class PredicateOperand<ValueType ty, dag OpTypes, dag AlwaysVal> 610 : Operand<ty> { 611 let MIOperandInfo = OpTypes; 612 dag DefaultOps = AlwaysVal; 613} 614 615/// OptionalDefOperand - This is used to define a optional definition operand 616/// for an instruction. DefaultOps is the register the operand represents if 617/// none is supplied, e.g. zero_reg. 618class OptionalDefOperand<ValueType ty, dag OpTypes, dag defaultops> 619 : Operand<ty> { 620 let MIOperandInfo = OpTypes; 621 dag DefaultOps = defaultops; 622} 623 624 625// InstrInfo - This class should only be instantiated once to provide parameters 626// which are global to the target machine. 627// 628class InstrInfo { 629 // Target can specify its instructions in either big or little-endian formats. 630 // For instance, while both Sparc and PowerPC are big-endian platforms, the 631 // Sparc manual specifies its instructions in the format [31..0] (big), while 632 // PowerPC specifies them using the format [0..31] (little). 633 bit isLittleEndianEncoding = 0; 634 635 // The instruction properties mayLoad, mayStore, and hasSideEffects are unset 636 // by default, and TableGen will infer their value from the instruction 637 // pattern when possible. 638 // 639 // Normally, TableGen will issue an error it it can't infer the value of a 640 // property that hasn't been set explicitly. When guessInstructionProperties 641 // is set, it will guess a safe value instead. 642 // 643 // This option is a temporary migration help. It will go away. 644 bit guessInstructionProperties = 1; 645} 646 647// Standard Pseudo Instructions. 648// This list must match TargetOpcodes.h and CodeGenTarget.cpp. 649// Only these instructions are allowed in the TargetOpcode namespace. 650let isCodeGenOnly = 1, isPseudo = 1, Namespace = "TargetOpcode" in { 651def PHI : Instruction { 652 let OutOperandList = (outs); 653 let InOperandList = (ins variable_ops); 654 let AsmString = "PHINODE"; 655} 656def INLINEASM : Instruction { 657 let OutOperandList = (outs); 658 let InOperandList = (ins variable_ops); 659 let AsmString = ""; 660 let neverHasSideEffects = 1; // Note side effect is encoded in an operand. 661} 662def PROLOG_LABEL : Instruction { 663 let OutOperandList = (outs); 664 let InOperandList = (ins i32imm:$id); 665 let AsmString = ""; 666 let hasCtrlDep = 1; 667 let isNotDuplicable = 1; 668} 669def EH_LABEL : Instruction { 670 let OutOperandList = (outs); 671 let InOperandList = (ins i32imm:$id); 672 let AsmString = ""; 673 let hasCtrlDep = 1; 674 let isNotDuplicable = 1; 675} 676def GC_LABEL : Instruction { 677 let OutOperandList = (outs); 678 let InOperandList = (ins i32imm:$id); 679 let AsmString = ""; 680 let hasCtrlDep = 1; 681 let isNotDuplicable = 1; 682} 683def KILL : Instruction { 684 let OutOperandList = (outs); 685 let InOperandList = (ins variable_ops); 686 let AsmString = ""; 687 let neverHasSideEffects = 1; 688} 689def EXTRACT_SUBREG : Instruction { 690 let OutOperandList = (outs unknown:$dst); 691 let InOperandList = (ins unknown:$supersrc, i32imm:$subidx); 692 let AsmString = ""; 693 let neverHasSideEffects = 1; 694} 695def INSERT_SUBREG : Instruction { 696 let OutOperandList = (outs unknown:$dst); 697 let InOperandList = (ins unknown:$supersrc, unknown:$subsrc, i32imm:$subidx); 698 let AsmString = ""; 699 let neverHasSideEffects = 1; 700 let Constraints = "$supersrc = $dst"; 701} 702def IMPLICIT_DEF : Instruction { 703 let OutOperandList = (outs unknown:$dst); 704 let InOperandList = (ins); 705 let AsmString = ""; 706 let neverHasSideEffects = 1; 707 let isReMaterializable = 1; 708 let isAsCheapAsAMove = 1; 709} 710def SUBREG_TO_REG : Instruction { 711 let OutOperandList = (outs unknown:$dst); 712 let InOperandList = (ins unknown:$implsrc, unknown:$subsrc, i32imm:$subidx); 713 let AsmString = ""; 714 let neverHasSideEffects = 1; 715} 716def COPY_TO_REGCLASS : Instruction { 717 let OutOperandList = (outs unknown:$dst); 718 let InOperandList = (ins unknown:$src, i32imm:$regclass); 719 let AsmString = ""; 720 let neverHasSideEffects = 1; 721 let isAsCheapAsAMove = 1; 722} 723def DBG_VALUE : Instruction { 724 let OutOperandList = (outs); 725 let InOperandList = (ins variable_ops); 726 let AsmString = "DBG_VALUE"; 727 let neverHasSideEffects = 1; 728} 729def REG_SEQUENCE : Instruction { 730 let OutOperandList = (outs unknown:$dst); 731 let InOperandList = (ins variable_ops); 732 let AsmString = ""; 733 let neverHasSideEffects = 1; 734 let isAsCheapAsAMove = 1; 735} 736def COPY : Instruction { 737 let OutOperandList = (outs unknown:$dst); 738 let InOperandList = (ins unknown:$src); 739 let AsmString = ""; 740 let neverHasSideEffects = 1; 741 let isAsCheapAsAMove = 1; 742} 743def BUNDLE : Instruction { 744 let OutOperandList = (outs); 745 let InOperandList = (ins variable_ops); 746 let AsmString = "BUNDLE"; 747} 748} 749 750//===----------------------------------------------------------------------===// 751// AsmParser - This class can be implemented by targets that wish to implement 752// .s file parsing. 753// 754// Subtargets can have multiple different assembly parsers (e.g. AT&T vs Intel 755// syntax on X86 for example). 756// 757class AsmParser { 758 // AsmParserClassName - This specifies the suffix to use for the asmparser 759 // class. Generated AsmParser classes are always prefixed with the target 760 // name. 761 string AsmParserClassName = "AsmParser"; 762 763 // AsmParserInstCleanup - If non-empty, this is the name of a custom member 764 // function of the AsmParser class to call on every matched instruction. 765 // This can be used to perform target specific instruction post-processing. 766 string AsmParserInstCleanup = ""; 767 768 //ShouldEmitMatchRegisterName - Set to false if the target needs a hand 769 //written register name matcher 770 bit ShouldEmitMatchRegisterName = 1; 771} 772def DefaultAsmParser : AsmParser; 773 774//===----------------------------------------------------------------------===// 775// AsmParserVariant - Subtargets can have multiple different assembly parsers 776// (e.g. AT&T vs Intel syntax on X86 for example). This class can be 777// implemented by targets to describe such variants. 778// 779class AsmParserVariant { 780 // Variant - AsmParsers can be of multiple different variants. Variants are 781 // used to support targets that need to parser multiple formats for the 782 // assembly language. 783 int Variant = 0; 784 785 // CommentDelimiter - If given, the delimiter string used to recognize 786 // comments which are hard coded in the .td assembler strings for individual 787 // instructions. 788 string CommentDelimiter = ""; 789 790 // RegisterPrefix - If given, the token prefix which indicates a register 791 // token. This is used by the matcher to automatically recognize hard coded 792 // register tokens as constrained registers, instead of tokens, for the 793 // purposes of matching. 794 string RegisterPrefix = ""; 795} 796def DefaultAsmParserVariant : AsmParserVariant; 797 798/// AssemblerPredicate - This is a Predicate that can be used when the assembler 799/// matches instructions and aliases. 800class AssemblerPredicate<string cond, string name = ""> { 801 bit AssemblerMatcherPredicate = 1; 802 string AssemblerCondString = cond; 803 string PredicateName = name; 804} 805 806/// TokenAlias - This class allows targets to define assembler token 807/// operand aliases. That is, a token literal operand which is equivalent 808/// to another, canonical, token literal. For example, ARM allows: 809/// vmov.u32 s4, #0 -> vmov.i32, #0 810/// 'u32' is a more specific designator for the 32-bit integer type specifier 811/// and is legal for any instruction which accepts 'i32' as a datatype suffix. 812/// def : TokenAlias<".u32", ".i32">; 813/// 814/// This works by marking the match class of 'From' as a subclass of the 815/// match class of 'To'. 816class TokenAlias<string From, string To> { 817 string FromToken = From; 818 string ToToken = To; 819} 820 821/// MnemonicAlias - This class allows targets to define assembler mnemonic 822/// aliases. This should be used when all forms of one mnemonic are accepted 823/// with a different mnemonic. For example, X86 allows: 824/// sal %al, 1 -> shl %al, 1 825/// sal %ax, %cl -> shl %ax, %cl 826/// sal %eax, %cl -> shl %eax, %cl 827/// etc. Though "sal" is accepted with many forms, all of them are directly 828/// translated to a shl, so it can be handled with (in the case of X86, it 829/// actually has one for each suffix as well): 830/// def : MnemonicAlias<"sal", "shl">; 831/// 832/// Mnemonic aliases are mapped before any other translation in the match phase, 833/// and do allow Requires predicates, e.g.: 834/// 835/// def : MnemonicAlias<"pushf", "pushfq">, Requires<[In64BitMode]>; 836/// def : MnemonicAlias<"pushf", "pushfl">, Requires<[In32BitMode]>; 837/// 838class MnemonicAlias<string From, string To> { 839 string FromMnemonic = From; 840 string ToMnemonic = To; 841 842 // Predicates - Predicates that must be true for this remapping to happen. 843 list<Predicate> Predicates = []; 844} 845 846/// InstAlias - This defines an alternate assembly syntax that is allowed to 847/// match an instruction that has a different (more canonical) assembly 848/// representation. 849class InstAlias<string Asm, dag Result, bit Emit = 0b1> { 850 string AsmString = Asm; // The .s format to match the instruction with. 851 dag ResultInst = Result; // The MCInst to generate. 852 bit EmitAlias = Emit; // Emit the alias instead of what's aliased. 853 854 // Predicates - Predicates that must be true for this to match. 855 list<Predicate> Predicates = []; 856} 857 858//===----------------------------------------------------------------------===// 859// AsmWriter - This class can be implemented by targets that need to customize 860// the format of the .s file writer. 861// 862// Subtargets can have multiple different asmwriters (e.g. AT&T vs Intel syntax 863// on X86 for example). 864// 865class AsmWriter { 866 // AsmWriterClassName - This specifies the suffix to use for the asmwriter 867 // class. Generated AsmWriter classes are always prefixed with the target 868 // name. 869 string AsmWriterClassName = "AsmPrinter"; 870 871 // Variant - AsmWriters can be of multiple different variants. Variants are 872 // used to support targets that need to emit assembly code in ways that are 873 // mostly the same for different targets, but have minor differences in 874 // syntax. If the asmstring contains {|} characters in them, this integer 875 // will specify which alternative to use. For example "{x|y|z}" with Variant 876 // == 1, will expand to "y". 877 int Variant = 0; 878 879 880 // FirstOperandColumn/OperandSpacing - If the assembler syntax uses a columnar 881 // layout, the asmwriter can actually generate output in this columns (in 882 // verbose-asm mode). These two values indicate the width of the first column 883 // (the "opcode" area) and the width to reserve for subsequent operands. When 884 // verbose asm mode is enabled, operands will be indented to respect this. 885 int FirstOperandColumn = -1; 886 887 // OperandSpacing - Space between operand columns. 888 int OperandSpacing = -1; 889 890 // isMCAsmWriter - Is this assembly writer for an MC emitter? This controls 891 // generation of the printInstruction() method. For MC printers, it takes 892 // an MCInstr* operand, otherwise it takes a MachineInstr*. 893 bit isMCAsmWriter = 0; 894} 895def DefaultAsmWriter : AsmWriter; 896 897 898//===----------------------------------------------------------------------===// 899// Target - This class contains the "global" target information 900// 901class Target { 902 // InstructionSet - Instruction set description for this target. 903 InstrInfo InstructionSet; 904 905 // AssemblyParsers - The AsmParser instances available for this target. 906 list<AsmParser> AssemblyParsers = [DefaultAsmParser]; 907 908 /// AssemblyParserVariants - The AsmParserVariant instances available for 909 /// this target. 910 list<AsmParserVariant> AssemblyParserVariants = [DefaultAsmParserVariant]; 911 912 // AssemblyWriters - The AsmWriter instances available for this target. 913 list<AsmWriter> AssemblyWriters = [DefaultAsmWriter]; 914} 915 916//===----------------------------------------------------------------------===// 917// SubtargetFeature - A characteristic of the chip set. 918// 919class SubtargetFeature<string n, string a, string v, string d, 920 list<SubtargetFeature> i = []> { 921 // Name - Feature name. Used by command line (-mattr=) to determine the 922 // appropriate target chip. 923 // 924 string Name = n; 925 926 // Attribute - Attribute to be set by feature. 927 // 928 string Attribute = a; 929 930 // Value - Value the attribute to be set to by feature. 931 // 932 string Value = v; 933 934 // Desc - Feature description. Used by command line (-mattr=) to display help 935 // information. 936 // 937 string Desc = d; 938 939 // Implies - Features that this feature implies are present. If one of those 940 // features isn't set, then this one shouldn't be set either. 941 // 942 list<SubtargetFeature> Implies = i; 943} 944 945//===----------------------------------------------------------------------===// 946// Processor chip sets - These values represent each of the chip sets supported 947// by the scheduler. Each Processor definition requires corresponding 948// instruction itineraries. 949// 950class Processor<string n, ProcessorItineraries pi, list<SubtargetFeature> f> { 951 // Name - Chip set name. Used by command line (-mcpu=) to determine the 952 // appropriate target chip. 953 // 954 string Name = n; 955 956 // SchedModel - The machine model for scheduling and instruction cost. 957 // 958 SchedMachineModel SchedModel = NoSchedModel; 959 960 // ProcItin - The scheduling information for the target processor. 961 // 962 ProcessorItineraries ProcItin = pi; 963 964 // Features - list of 965 list<SubtargetFeature> Features = f; 966} 967 968// ProcessorModel allows subtargets to specify the more general 969// SchedMachineModel instead if a ProcessorItinerary. Subtargets will 970// gradually move to this newer form. 971class ProcessorModel<string n, SchedMachineModel m, list<SubtargetFeature> f> 972 : Processor<n, NoItineraries, f> { 973 let SchedModel = m; 974} 975 976//===----------------------------------------------------------------------===// 977// Pull in the common support for calling conventions. 978// 979include "llvm/Target/TargetCallingConv.td" 980 981//===----------------------------------------------------------------------===// 982// Pull in the common support for DAG isel generation. 983// 984include "llvm/Target/TargetSelectionDAG.td" 985