Target.td revision cf12067ae08dc7911c860070eaf2830dc1dc4ff7
1//===- Target.td - Target Independent TableGen interface ---*- tablegen -*-===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This file defines the target-independent interfaces which should be 11// implemented by each target which is using a TableGen based code generator. 12// 13//===----------------------------------------------------------------------===// 14 15// Include all information about LLVM intrinsics. 16include "llvm/Intrinsics.td" 17 18//===----------------------------------------------------------------------===// 19// Register file description - These classes are used to fill in the target 20// description classes. 21 22class RegisterClass; // Forward def 23 24// SubRegIndex - Use instances of SubRegIndex to identify subregisters. 25class SubRegIndex { 26 string Namespace = ""; 27} 28 29// Register - You should define one instance of this class for each register 30// in the target machine. String n will become the "name" of the register. 31class Register<string n> { 32 string Namespace = ""; 33 string AsmName = n; 34 35 // SpillSize - If this value is set to a non-zero value, it is the size in 36 // bits of the spill slot required to hold this register. If this value is 37 // set to zero, the information is inferred from any register classes the 38 // register belongs to. 39 int SpillSize = 0; 40 41 // SpillAlignment - This value is used to specify the alignment required for 42 // spilling the register. Like SpillSize, this should only be explicitly 43 // specified if the register is not in a register class. 44 int SpillAlignment = 0; 45 46 // Aliases - A list of registers that this register overlaps with. A read or 47 // modification of this register can potentially read or modify the aliased 48 // registers. 49 list<Register> Aliases = []; 50 51 // SubRegs - A list of registers that are parts of this register. Note these 52 // are "immediate" sub-registers and the registers within the list do not 53 // themselves overlap. e.g. For X86, EAX's SubRegs list contains only [AX], 54 // not [AX, AH, AL]. 55 list<Register> SubRegs = []; 56 57 // SubRegIndices - For each register in SubRegs, specify the SubRegIndex used 58 // to address it. Sub-sub-register indices are automatically inherited from 59 // SubRegs. 60 list<SubRegIndex> SubRegIndices = []; 61 62 // CompositeIndices - Specify subreg indices that don't correspond directly to 63 // a register in SubRegs and are not inherited. The following formats are 64 // supported: 65 // 66 // (a) Identity - Reg:a == Reg 67 // (a b) Alias - Reg:a == Reg:b 68 // (a b,c) Composite - Reg:a == (Reg:b):c 69 // 70 // This can be used to disambiguate a sub-sub-register that exists in more 71 // than one subregister and other weird stuff. 72 list<dag> CompositeIndices = []; 73 74 // DwarfNumbers - Numbers used internally by gcc/gdb to identify the register. 75 // These values can be determined by locating the <target>.h file in the 76 // directory llvmgcc/gcc/config/<target>/ and looking for REGISTER_NAMES. The 77 // order of these names correspond to the enumeration used by gcc. A value of 78 // -1 indicates that the gcc number is undefined and -2 that register number 79 // is invalid for this mode/flavour. 80 list<int> DwarfNumbers = []; 81} 82 83// RegisterWithSubRegs - This can be used to define instances of Register which 84// need to specify sub-registers. 85// List "subregs" specifies which registers are sub-registers to this one. This 86// is used to populate the SubRegs and AliasSet fields of TargetRegisterDesc. 87// This allows the code generator to be careful not to put two values with 88// overlapping live ranges into registers which alias. 89class RegisterWithSubRegs<string n, list<Register> subregs> : Register<n> { 90 let SubRegs = subregs; 91} 92 93// RegisterClass - Now that all of the registers are defined, and aliases 94// between registers are defined, specify which registers belong to which 95// register classes. This also defines the default allocation order of 96// registers by register allocators. 97// 98class RegisterClass<string namespace, list<ValueType> regTypes, int alignment, 99 list<Register> regList> { 100 string Namespace = namespace; 101 102 // RegType - Specify the list ValueType of the registers in this register 103 // class. Note that all registers in a register class must have the same 104 // ValueTypes. This is a list because some targets permit storing different 105 // types in same register, for example vector values with 128-bit total size, 106 // but different count/size of items, like SSE on x86. 107 // 108 list<ValueType> RegTypes = regTypes; 109 110 // Size - Specify the spill size in bits of the registers. A default value of 111 // zero lets tablgen pick an appropriate size. 112 int Size = 0; 113 114 // Alignment - Specify the alignment required of the registers when they are 115 // stored or loaded to memory. 116 // 117 int Alignment = alignment; 118 119 // CopyCost - This value is used to specify the cost of copying a value 120 // between two registers in this register class. The default value is one 121 // meaning it takes a single instruction to perform the copying. A negative 122 // value means copying is extremely expensive or impossible. 123 int CopyCost = 1; 124 125 // MemberList - Specify which registers are in this class. If the 126 // allocation_order_* method are not specified, this also defines the order of 127 // allocation used by the register allocator. 128 // 129 list<Register> MemberList = regList; 130 131 // SubRegClasses - Specify the register class of subregisters as a list of 132 // dags: (RegClass SubRegIndex, SubRegindex, ...) 133 list<dag> SubRegClasses = []; 134 135 // MethodProtos/MethodBodies - These members can be used to insert arbitrary 136 // code into a generated register class. The normal usage of this is to 137 // overload virtual methods. 138 code MethodProtos = [{}]; 139 code MethodBodies = [{}]; 140} 141 142 143//===----------------------------------------------------------------------===// 144// DwarfRegNum - This class provides a mapping of the llvm register enumeration 145// to the register numbering used by gcc and gdb. These values are used by a 146// debug information writer to describe where values may be located during 147// execution. 148class DwarfRegNum<list<int> Numbers> { 149 // DwarfNumbers - Numbers used internally by gcc/gdb to identify the register. 150 // These values can be determined by locating the <target>.h file in the 151 // directory llvmgcc/gcc/config/<target>/ and looking for REGISTER_NAMES. The 152 // order of these names correspond to the enumeration used by gcc. A value of 153 // -1 indicates that the gcc number is undefined and -2 that register number 154 // is invalid for this mode/flavour. 155 list<int> DwarfNumbers = Numbers; 156} 157 158//===----------------------------------------------------------------------===// 159// Pull in the common support for scheduling 160// 161include "llvm/Target/TargetSchedule.td" 162 163class Predicate; // Forward def 164 165//===----------------------------------------------------------------------===// 166// Instruction set description - These classes correspond to the C++ classes in 167// the Target/TargetInstrInfo.h file. 168// 169class Instruction { 170 string Namespace = ""; 171 172 dag OutOperandList; // An dag containing the MI def operand list. 173 dag InOperandList; // An dag containing the MI use operand list. 174 string AsmString = ""; // The .s format to print the instruction with. 175 176 // Pattern - Set to the DAG pattern for this instruction, if we know of one, 177 // otherwise, uninitialized. 178 list<dag> Pattern; 179 180 // The follow state will eventually be inferred automatically from the 181 // instruction pattern. 182 183 list<Register> Uses = []; // Default to using no non-operand registers 184 list<Register> Defs = []; // Default to modifying no non-operand registers 185 186 // Predicates - List of predicates which will be turned into isel matching 187 // code. 188 list<Predicate> Predicates = []; 189 190 // Code size. 191 int CodeSize = 0; 192 193 // Added complexity passed onto matching pattern. 194 int AddedComplexity = 0; 195 196 // These bits capture information about the high-level semantics of the 197 // instruction. 198 bit isReturn = 0; // Is this instruction a return instruction? 199 bit isBranch = 0; // Is this instruction a branch instruction? 200 bit isIndirectBranch = 0; // Is this instruction an indirect branch? 201 bit isCompare = 0; // Is this instruction a comparison instruction? 202 bit isMoveImm = 0; // Is this instruction a move immediate instruction? 203 bit isBarrier = 0; // Can control flow fall through this instruction? 204 bit isCall = 0; // Is this instruction a call instruction? 205 bit canFoldAsLoad = 0; // Can this be folded as a simple memory operand? 206 bit mayLoad = 0; // Is it possible for this inst to read memory? 207 bit mayStore = 0; // Is it possible for this inst to write memory? 208 bit isConvertibleToThreeAddress = 0; // Can this 2-addr instruction promote? 209 bit isCommutable = 0; // Is this 3 operand instruction commutable? 210 bit isTerminator = 0; // Is this part of the terminator for a basic block? 211 bit isReMaterializable = 0; // Is this instruction re-materializable? 212 bit isPredicable = 0; // Is this instruction predicable? 213 bit hasDelaySlot = 0; // Does this instruction have an delay slot? 214 bit usesCustomInserter = 0; // Pseudo instr needing special help. 215 bit hasCtrlDep = 0; // Does this instruction r/w ctrl-flow chains? 216 bit isNotDuplicable = 0; // Is it unsafe to duplicate this instruction? 217 bit isAsCheapAsAMove = 0; // As cheap (or cheaper) than a move instruction. 218 bit hasExtraSrcRegAllocReq = 0; // Sources have special regalloc requirement? 219 bit hasExtraDefRegAllocReq = 0; // Defs have special regalloc requirement? 220 221 // Side effect flags - When set, the flags have these meanings: 222 // 223 // hasSideEffects - The instruction has side effects that are not 224 // captured by any operands of the instruction or other flags. 225 // 226 // neverHasSideEffects - Set on an instruction with no pattern if it has no 227 // side effects. 228 bit hasSideEffects = 0; 229 bit neverHasSideEffects = 0; 230 231 // Is this instruction a "real" instruction (with a distinct machine 232 // encoding), or is it a pseudo instruction used for codegen modeling 233 // purposes. 234 bit isCodeGenOnly = 0; 235 236 // Is this instruction a pseudo instruction for use by the assembler parser. 237 bit isAsmParserOnly = 0; 238 239 InstrItinClass Itinerary = NoItinerary;// Execution steps used for scheduling. 240 241 string Constraints = ""; // OperandConstraint, e.g. $src = $dst. 242 243 /// DisableEncoding - List of operand names (e.g. "$op1,$op2") that should not 244 /// be encoded into the output machineinstr. 245 string DisableEncoding = ""; 246 247 string PostEncoderMethod = ""; 248 249 /// Target-specific flags. This becomes the TSFlags field in TargetInstrDesc. 250 bits<64> TSFlags = 0; 251 252 ///@name Assembler Parser Support 253 ///@{ 254 255 string AsmMatchConverter = ""; 256 257 ///@} 258} 259 260/// Predicates - These are extra conditionals which are turned into instruction 261/// selector matching code. Currently each predicate is just a string. 262class Predicate<string cond> { 263 string CondString = cond; 264 265 /// AssemblerMatcherPredicate - If this feature can be used by the assembler 266 /// matcher, this is true. Targets should set this by inheriting their 267 /// feature from the AssemblerPredicate class in addition to Predicate. 268 bit AssemblerMatcherPredicate = 0; 269} 270 271/// NoHonorSignDependentRounding - This predicate is true if support for 272/// sign-dependent-rounding is not enabled. 273def NoHonorSignDependentRounding 274 : Predicate<"!HonorSignDependentRoundingFPMath()">; 275 276class Requires<list<Predicate> preds> { 277 list<Predicate> Predicates = preds; 278} 279 280/// ops definition - This is just a simple marker used to identify the operand 281/// list for an instruction. outs and ins are identical both syntactically and 282/// semanticallyr; they are used to define def operands and use operands to 283/// improve readibility. This should be used like this: 284/// (outs R32:$dst), (ins R32:$src1, R32:$src2) or something similar. 285def ops; 286def outs; 287def ins; 288 289/// variable_ops definition - Mark this instruction as taking a variable number 290/// of operands. 291def variable_ops; 292 293 294/// PointerLikeRegClass - Values that are designed to have pointer width are 295/// derived from this. TableGen treats the register class as having a symbolic 296/// type that it doesn't know, and resolves the actual regclass to use by using 297/// the TargetRegisterInfo::getPointerRegClass() hook at codegen time. 298class PointerLikeRegClass<int Kind> { 299 int RegClassKind = Kind; 300} 301 302 303/// ptr_rc definition - Mark this operand as being a pointer value whose 304/// register class is resolved dynamically via a callback to TargetInstrInfo. 305/// FIXME: We should probably change this to a class which contain a list of 306/// flags. But currently we have but one flag. 307def ptr_rc : PointerLikeRegClass<0>; 308 309/// unknown definition - Mark this operand as being of unknown type, causing 310/// it to be resolved by inference in the context it is used. 311def unknown; 312 313/// AsmOperandClass - Representation for the kinds of operands which the target 314/// specific parser can create and the assembly matcher may need to distinguish. 315/// 316/// Operand classes are used to define the order in which instructions are 317/// matched, to ensure that the instruction which gets matched for any 318/// particular list of operands is deterministic. 319/// 320/// The target specific parser must be able to classify a parsed operand into a 321/// unique class which does not partially overlap with any other classes. It can 322/// match a subset of some other class, in which case the super class field 323/// should be defined. 324class AsmOperandClass { 325 /// The name to use for this class, which should be usable as an enum value. 326 string Name = ?; 327 328 /// The super classes of this operand. 329 list<AsmOperandClass> SuperClasses = []; 330 331 /// The name of the method on the target specific operand to call to test 332 /// whether the operand is an instance of this class. If not set, this will 333 /// default to "isFoo", where Foo is the AsmOperandClass name. The method 334 /// signature should be: 335 /// bool isFoo() const; 336 string PredicateMethod = ?; 337 338 /// The name of the method on the target specific operand to call to add the 339 /// target specific operand to an MCInst. If not set, this will default to 340 /// "addFooOperands", where Foo is the AsmOperandClass name. The method 341 /// signature should be: 342 /// void addFooOperands(MCInst &Inst, unsigned N) const; 343 string RenderMethod = ?; 344} 345 346def ImmAsmOperand : AsmOperandClass { 347 let Name = "Imm"; 348} 349 350/// Operand Types - These provide the built-in operand types that may be used 351/// by a target. Targets can optionally provide their own operand types as 352/// needed, though this should not be needed for RISC targets. 353class Operand<ValueType ty> { 354 ValueType Type = ty; 355 string PrintMethod = "printOperand"; 356 string EncoderMethod = ""; 357 string AsmOperandLowerMethod = ?; 358 dag MIOperandInfo = (ops); 359 360 // ParserMatchClass - The "match class" that operands of this type fit 361 // in. Match classes are used to define the order in which instructions are 362 // match, to ensure that which instructions gets matched is deterministic. 363 // 364 // The target specific parser must be able to classify an parsed operand into 365 // a unique class, which does not partially overlap with any other classes. It 366 // can match a subset of some other class, in which case the AsmOperandClass 367 // should declare the other operand as one of its super classes. 368 AsmOperandClass ParserMatchClass = ImmAsmOperand; 369} 370 371def i1imm : Operand<i1>; 372def i8imm : Operand<i8>; 373def i16imm : Operand<i16>; 374def i32imm : Operand<i32>; 375def i64imm : Operand<i64>; 376 377def f32imm : Operand<f32>; 378def f64imm : Operand<f64>; 379 380/// zero_reg definition - Special node to stand for the zero register. 381/// 382def zero_reg; 383 384/// PredicateOperand - This can be used to define a predicate operand for an 385/// instruction. OpTypes specifies the MIOperandInfo for the operand, and 386/// AlwaysVal specifies the value of this predicate when set to "always 387/// execute". 388class PredicateOperand<ValueType ty, dag OpTypes, dag AlwaysVal> 389 : Operand<ty> { 390 let MIOperandInfo = OpTypes; 391 dag DefaultOps = AlwaysVal; 392} 393 394/// OptionalDefOperand - This is used to define a optional definition operand 395/// for an instruction. DefaultOps is the register the operand represents if 396/// none is supplied, e.g. zero_reg. 397class OptionalDefOperand<ValueType ty, dag OpTypes, dag defaultops> 398 : Operand<ty> { 399 let MIOperandInfo = OpTypes; 400 dag DefaultOps = defaultops; 401} 402 403 404// InstrInfo - This class should only be instantiated once to provide parameters 405// which are global to the target machine. 406// 407class InstrInfo { 408 // Target can specify its instructions in either big or little-endian formats. 409 // For instance, while both Sparc and PowerPC are big-endian platforms, the 410 // Sparc manual specifies its instructions in the format [31..0] (big), while 411 // PowerPC specifies them using the format [0..31] (little). 412 bit isLittleEndianEncoding = 0; 413} 414 415// Standard Pseudo Instructions. 416// This list must match TargetOpcodes.h and CodeGenTarget.cpp. 417// Only these instructions are allowed in the TargetOpcode namespace. 418let isCodeGenOnly = 1, Namespace = "TargetOpcode" in { 419def PHI : Instruction { 420 let OutOperandList = (outs); 421 let InOperandList = (ins variable_ops); 422 let AsmString = "PHINODE"; 423} 424def INLINEASM : Instruction { 425 let OutOperandList = (outs); 426 let InOperandList = (ins variable_ops); 427 let AsmString = ""; 428 let neverHasSideEffects = 1; // Note side effect is encoded in an operand. 429} 430def PROLOG_LABEL : Instruction { 431 let OutOperandList = (outs); 432 let InOperandList = (ins i32imm:$id); 433 let AsmString = ""; 434 let hasCtrlDep = 1; 435 let isNotDuplicable = 1; 436} 437def EH_LABEL : Instruction { 438 let OutOperandList = (outs); 439 let InOperandList = (ins i32imm:$id); 440 let AsmString = ""; 441 let hasCtrlDep = 1; 442 let isNotDuplicable = 1; 443} 444def GC_LABEL : Instruction { 445 let OutOperandList = (outs); 446 let InOperandList = (ins i32imm:$id); 447 let AsmString = ""; 448 let hasCtrlDep = 1; 449 let isNotDuplicable = 1; 450} 451def KILL : Instruction { 452 let OutOperandList = (outs); 453 let InOperandList = (ins variable_ops); 454 let AsmString = ""; 455 let neverHasSideEffects = 1; 456} 457def EXTRACT_SUBREG : Instruction { 458 let OutOperandList = (outs unknown:$dst); 459 let InOperandList = (ins unknown:$supersrc, i32imm:$subidx); 460 let AsmString = ""; 461 let neverHasSideEffects = 1; 462} 463def INSERT_SUBREG : Instruction { 464 let OutOperandList = (outs unknown:$dst); 465 let InOperandList = (ins unknown:$supersrc, unknown:$subsrc, i32imm:$subidx); 466 let AsmString = ""; 467 let neverHasSideEffects = 1; 468 let Constraints = "$supersrc = $dst"; 469} 470def IMPLICIT_DEF : Instruction { 471 let OutOperandList = (outs unknown:$dst); 472 let InOperandList = (ins); 473 let AsmString = ""; 474 let neverHasSideEffects = 1; 475 let isReMaterializable = 1; 476 let isAsCheapAsAMove = 1; 477} 478def SUBREG_TO_REG : Instruction { 479 let OutOperandList = (outs unknown:$dst); 480 let InOperandList = (ins unknown:$implsrc, unknown:$subsrc, i32imm:$subidx); 481 let AsmString = ""; 482 let neverHasSideEffects = 1; 483} 484def COPY_TO_REGCLASS : Instruction { 485 let OutOperandList = (outs unknown:$dst); 486 let InOperandList = (ins unknown:$src, i32imm:$regclass); 487 let AsmString = ""; 488 let neverHasSideEffects = 1; 489 let isAsCheapAsAMove = 1; 490} 491def DBG_VALUE : Instruction { 492 let OutOperandList = (outs); 493 let InOperandList = (ins variable_ops); 494 let AsmString = "DBG_VALUE"; 495 let neverHasSideEffects = 1; 496} 497def REG_SEQUENCE : Instruction { 498 let OutOperandList = (outs unknown:$dst); 499 let InOperandList = (ins variable_ops); 500 let AsmString = ""; 501 let neverHasSideEffects = 1; 502 let isAsCheapAsAMove = 1; 503} 504def COPY : Instruction { 505 let OutOperandList = (outs unknown:$dst); 506 let InOperandList = (ins unknown:$src); 507 let AsmString = ""; 508 let neverHasSideEffects = 1; 509 let isAsCheapAsAMove = 1; 510} 511} 512 513//===----------------------------------------------------------------------===// 514// AsmParser - This class can be implemented by targets that wish to implement 515// .s file parsing. 516// 517// Subtargets can have multiple different assembly parsers (e.g. AT&T vs Intel 518// syntax on X86 for example). 519// 520class AsmParser { 521 // AsmParserClassName - This specifies the suffix to use for the asmparser 522 // class. Generated AsmParser classes are always prefixed with the target 523 // name. 524 string AsmParserClassName = "AsmParser"; 525 526 // AsmParserInstCleanup - If non-empty, this is the name of a custom member 527 // function of the AsmParser class to call on every matched instruction. 528 // This can be used to perform target specific instruction post-processing. 529 string AsmParserInstCleanup = ""; 530 531 // Variant - AsmParsers can be of multiple different variants. Variants are 532 // used to support targets that need to parser multiple formats for the 533 // assembly language. 534 int Variant = 0; 535 536 // CommentDelimiter - If given, the delimiter string used to recognize 537 // comments which are hard coded in the .td assembler strings for individual 538 // instructions. 539 string CommentDelimiter = ""; 540 541 // RegisterPrefix - If given, the token prefix which indicates a register 542 // token. This is used by the matcher to automatically recognize hard coded 543 // register tokens as constrained registers, instead of tokens, for the 544 // purposes of matching. 545 string RegisterPrefix = ""; 546} 547def DefaultAsmParser : AsmParser; 548 549/// AssemblerPredicate - This is a Predicate that can be used when the assembler 550/// matches instructions and aliases. 551class AssemblerPredicate { 552 bit AssemblerMatcherPredicate = 1; 553} 554 555 556 557/// MnemonicAlias - This class allows targets to define assembler mnemonic 558/// aliases. This should be used when all forms of one mnemonic are accepted 559/// with a different mnemonic. For example, X86 allows: 560/// sal %al, 1 -> shl %al, 1 561/// sal %ax, %cl -> shl %ax, %cl 562/// sal %eax, %cl -> shl %eax, %cl 563/// etc. Though "sal" is accepted with many forms, all of them are directly 564/// translated to a shl, so it can be handled with (in the case of X86, it 565/// actually has one for each suffix as well): 566/// def : MnemonicAlias<"sal", "shl">; 567/// 568/// Mnemonic aliases are mapped before any other translation in the match phase, 569/// and do allow Requires predicates, e.g.: 570/// 571/// def : MnemonicAlias<"pushf", "pushfq">, Requires<[In64BitMode]>; 572/// def : MnemonicAlias<"pushf", "pushfl">, Requires<[In32BitMode]>; 573/// 574class MnemonicAlias<string From, string To> { 575 string FromMnemonic = From; 576 string ToMnemonic = To; 577 578 // Predicates - Predicates that must be true for this remapping to happen. 579 list<Predicate> Predicates = []; 580} 581 582/// InstAlias - This defines an alternate assembly syntax that is allowed to 583/// match an instruction that has a different (more canonical) assembly 584/// representation. 585class InstAlias<string Asm, dag Result> { 586 string AsmString = Asm; // The .s format to match the instruction with. 587 dag ResultInst = Result; // The MCInst to generate. 588 589 // Predicates - Predicates that must be true for this to match. 590 list<Predicate> Predicates = []; 591} 592 593//===----------------------------------------------------------------------===// 594// AsmWriter - This class can be implemented by targets that need to customize 595// the format of the .s file writer. 596// 597// Subtargets can have multiple different asmwriters (e.g. AT&T vs Intel syntax 598// on X86 for example). 599// 600class AsmWriter { 601 // AsmWriterClassName - This specifies the suffix to use for the asmwriter 602 // class. Generated AsmWriter classes are always prefixed with the target 603 // name. 604 string AsmWriterClassName = "AsmPrinter"; 605 606 // Variant - AsmWriters can be of multiple different variants. Variants are 607 // used to support targets that need to emit assembly code in ways that are 608 // mostly the same for different targets, but have minor differences in 609 // syntax. If the asmstring contains {|} characters in them, this integer 610 // will specify which alternative to use. For example "{x|y|z}" with Variant 611 // == 1, will expand to "y". 612 int Variant = 0; 613 614 615 // FirstOperandColumn/OperandSpacing - If the assembler syntax uses a columnar 616 // layout, the asmwriter can actually generate output in this columns (in 617 // verbose-asm mode). These two values indicate the width of the first column 618 // (the "opcode" area) and the width to reserve for subsequent operands. When 619 // verbose asm mode is enabled, operands will be indented to respect this. 620 int FirstOperandColumn = -1; 621 622 // OperandSpacing - Space between operand columns. 623 int OperandSpacing = -1; 624 625 // isMCAsmWriter - Is this assembly writer for an MC emitter? This controls 626 // generation of the printInstruction() method. For MC printers, it takes 627 // an MCInstr* operand, otherwise it takes a MachineInstr*. 628 bit isMCAsmWriter = 0; 629} 630def DefaultAsmWriter : AsmWriter; 631 632 633//===----------------------------------------------------------------------===// 634// Target - This class contains the "global" target information 635// 636class Target { 637 // InstructionSet - Instruction set description for this target. 638 InstrInfo InstructionSet; 639 640 // AssemblyParsers - The AsmParser instances available for this target. 641 list<AsmParser> AssemblyParsers = [DefaultAsmParser]; 642 643 // AssemblyWriters - The AsmWriter instances available for this target. 644 list<AsmWriter> AssemblyWriters = [DefaultAsmWriter]; 645} 646 647//===----------------------------------------------------------------------===// 648// SubtargetFeature - A characteristic of the chip set. 649// 650class SubtargetFeature<string n, string a, string v, string d, 651 list<SubtargetFeature> i = []> { 652 // Name - Feature name. Used by command line (-mattr=) to determine the 653 // appropriate target chip. 654 // 655 string Name = n; 656 657 // Attribute - Attribute to be set by feature. 658 // 659 string Attribute = a; 660 661 // Value - Value the attribute to be set to by feature. 662 // 663 string Value = v; 664 665 // Desc - Feature description. Used by command line (-mattr=) to display help 666 // information. 667 // 668 string Desc = d; 669 670 // Implies - Features that this feature implies are present. If one of those 671 // features isn't set, then this one shouldn't be set either. 672 // 673 list<SubtargetFeature> Implies = i; 674} 675 676//===----------------------------------------------------------------------===// 677// Processor chip sets - These values represent each of the chip sets supported 678// by the scheduler. Each Processor definition requires corresponding 679// instruction itineraries. 680// 681class Processor<string n, ProcessorItineraries pi, list<SubtargetFeature> f> { 682 // Name - Chip set name. Used by command line (-mcpu=) to determine the 683 // appropriate target chip. 684 // 685 string Name = n; 686 687 // ProcItin - The scheduling information for the target processor. 688 // 689 ProcessorItineraries ProcItin = pi; 690 691 // Features - list of 692 list<SubtargetFeature> Features = f; 693} 694 695//===----------------------------------------------------------------------===// 696// Pull in the common support for calling conventions. 697// 698include "llvm/Target/TargetCallingConv.td" 699 700//===----------------------------------------------------------------------===// 701// Pull in the common support for DAG isel generation. 702// 703include "llvm/Target/TargetSelectionDAG.td" 704