Target.td revision ea761868b5e4c0166721daf259f86c3816b44f42
1//===- Target.td - Target Independent TableGen interface ---*- tablegen -*-===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This file defines the target-independent interfaces which should be 11// implemented by each target which is using a TableGen based code generator. 12// 13//===----------------------------------------------------------------------===// 14 15// Include all information about LLVM intrinsics. 16include "llvm/Intrinsics.td" 17 18//===----------------------------------------------------------------------===// 19// Register file description - These classes are used to fill in the target 20// description classes. 21 22class RegisterClass; // Forward def 23 24// Register - You should define one instance of this class for each register 25// in the target machine. String n will become the "name" of the register. 26class Register<string n> { 27 string Namespace = ""; 28 string AsmName = n; 29 30 // SpillSize - If this value is set to a non-zero value, it is the size in 31 // bits of the spill slot required to hold this register. If this value is 32 // set to zero, the information is inferred from any register classes the 33 // register belongs to. 34 int SpillSize = 0; 35 36 // SpillAlignment - This value is used to specify the alignment required for 37 // spilling the register. Like SpillSize, this should only be explicitly 38 // specified if the register is not in a register class. 39 int SpillAlignment = 0; 40 41 // Aliases - A list of registers that this register overlaps with. A read or 42 // modification of this register can potentially read or modify the aliased 43 // registers. 44 list<Register> Aliases = []; 45 46 // SubRegs - A list of registers that are parts of this register. Note these 47 // are "immediate" sub-registers and the registers within the list do not 48 // themselves overlap. e.g. For X86, EAX's SubRegs list contains only [AX], 49 // not [AX, AH, AL]. 50 list<Register> SubRegs = []; 51 52 // DwarfNumbers - Numbers used internally by gcc/gdb to identify the register. 53 // These values can be determined by locating the <target>.h file in the 54 // directory llvmgcc/gcc/config/<target>/ and looking for REGISTER_NAMES. The 55 // order of these names correspond to the enumeration used by gcc. A value of 56 // -1 indicates that the gcc number is undefined and -2 that register number 57 // is invalid for this mode/flavour. 58 list<int> DwarfNumbers = []; 59} 60 61// RegisterWithSubRegs - This can be used to define instances of Register which 62// need to specify sub-registers. 63// List "subregs" specifies which registers are sub-registers to this one. This 64// is used to populate the SubRegs and AliasSet fields of TargetRegisterDesc. 65// This allows the code generator to be careful not to put two values with 66// overlapping live ranges into registers which alias. 67class RegisterWithSubRegs<string n, list<Register> subregs> : Register<n> { 68 let SubRegs = subregs; 69} 70 71// SubRegSet - This can be used to define a specific mapping of registers to 72// indices, for use as named subregs of a particular physical register. Each 73// register in 'subregs' becomes an addressable subregister at index 'n' of the 74// corresponding register in 'regs'. 75class SubRegSet<int n, list<Register> regs, list<Register> subregs> { 76 int index = n; 77 78 list<Register> From = regs; 79 list<Register> To = subregs; 80} 81 82// RegisterClass - Now that all of the registers are defined, and aliases 83// between registers are defined, specify which registers belong to which 84// register classes. This also defines the default allocation order of 85// registers by register allocators. 86// 87class RegisterClass<string namespace, list<ValueType> regTypes, int alignment, 88 list<Register> regList> { 89 string Namespace = namespace; 90 91 // RegType - Specify the list ValueType of the registers in this register 92 // class. Note that all registers in a register class must have the same 93 // ValueTypes. This is a list because some targets permit storing different 94 // types in same register, for example vector values with 128-bit total size, 95 // but different count/size of items, like SSE on x86. 96 // 97 list<ValueType> RegTypes = regTypes; 98 99 // Size - Specify the spill size in bits of the registers. A default value of 100 // zero lets tablgen pick an appropriate size. 101 int Size = 0; 102 103 // Alignment - Specify the alignment required of the registers when they are 104 // stored or loaded to memory. 105 // 106 int Alignment = alignment; 107 108 // CopyCost - This value is used to specify the cost of copying a value 109 // between two registers in this register class. The default value is one 110 // meaning it takes a single instruction to perform the copying. A negative 111 // value means copying is extremely expensive or impossible. 112 int CopyCost = 1; 113 114 // MemberList - Specify which registers are in this class. If the 115 // allocation_order_* method are not specified, this also defines the order of 116 // allocation used by the register allocator. 117 // 118 list<Register> MemberList = regList; 119 120 // SubClassList - Specify which register classes correspond to subregisters 121 // of this class. The order should be by subregister set index. 122 list<RegisterClass> SubRegClassList = []; 123 124 // MethodProtos/MethodBodies - These members can be used to insert arbitrary 125 // code into a generated register class. The normal usage of this is to 126 // overload virtual methods. 127 code MethodProtos = [{}]; 128 code MethodBodies = [{}]; 129} 130 131 132//===----------------------------------------------------------------------===// 133// DwarfRegNum - This class provides a mapping of the llvm register enumeration 134// to the register numbering used by gcc and gdb. These values are used by a 135// debug information writer to describe where values may be located during 136// execution. 137class DwarfRegNum<list<int> Numbers> { 138 // DwarfNumbers - Numbers used internally by gcc/gdb to identify the register. 139 // These values can be determined by locating the <target>.h file in the 140 // directory llvmgcc/gcc/config/<target>/ and looking for REGISTER_NAMES. The 141 // order of these names correspond to the enumeration used by gcc. A value of 142 // -1 indicates that the gcc number is undefined and -2 that register number is 143 // invalid for this mode/flavour. 144 list<int> DwarfNumbers = Numbers; 145} 146 147//===----------------------------------------------------------------------===// 148// Pull in the common support for scheduling 149// 150include "llvm/Target/TargetSchedule.td" 151 152class Predicate; // Forward def 153 154//===----------------------------------------------------------------------===// 155// Instruction set description - These classes correspond to the C++ classes in 156// the Target/TargetInstrInfo.h file. 157// 158class Instruction { 159 string Namespace = ""; 160 161 dag OutOperandList; // An dag containing the MI def operand list. 162 dag InOperandList; // An dag containing the MI use operand list. 163 string AsmString = ""; // The .s format to print the instruction with. 164 165 // Pattern - Set to the DAG pattern for this instruction, if we know of one, 166 // otherwise, uninitialized. 167 list<dag> Pattern; 168 169 // The follow state will eventually be inferred automatically from the 170 // instruction pattern. 171 172 list<Register> Uses = []; // Default to using no non-operand registers 173 list<Register> Defs = []; // Default to modifying no non-operand registers 174 175 // Predicates - List of predicates which will be turned into isel matching 176 // code. 177 list<Predicate> Predicates = []; 178 179 // Code size. 180 int CodeSize = 0; 181 182 // Added complexity passed onto matching pattern. 183 int AddedComplexity = 0; 184 185 // These bits capture information about the high-level semantics of the 186 // instruction. 187 bit isReturn = 0; // Is this instruction a return instruction? 188 bit isBranch = 0; // Is this instruction a branch instruction? 189 bit isIndirectBranch = 0; // Is this instruction an indirect branch? 190 bit isBarrier = 0; // Can control flow fall through this instruction? 191 bit isCall = 0; // Is this instruction a call instruction? 192 bit canFoldAsLoad = 0; // Can this be folded as a simple memory operand? 193 bit mayLoad = 0; // Is it possible for this inst to read memory? 194 bit mayStore = 0; // Is it possible for this inst to write memory? 195 bit isTwoAddress = 0; // Is this a two address instruction? 196 bit isConvertibleToThreeAddress = 0; // Can this 2-addr instruction promote? 197 bit isCommutable = 0; // Is this 3 operand instruction commutable? 198 bit isTerminator = 0; // Is this part of the terminator for a basic block? 199 bit isReMaterializable = 0; // Is this instruction re-materializable? 200 bit isPredicable = 0; // Is this instruction predicable? 201 bit hasDelaySlot = 0; // Does this instruction have an delay slot? 202 bit usesCustomInserter = 0; // Pseudo instr needing special help. 203 bit hasCtrlDep = 0; // Does this instruction r/w ctrl-flow chains? 204 bit isNotDuplicable = 0; // Is it unsafe to duplicate this instruction? 205 bit isAsCheapAsAMove = 0; // As cheap (or cheaper) than a move instruction. 206 bit hasExtraSrcRegAllocReq = 0; // Sources have special regalloc requirement? 207 bit hasExtraDefRegAllocReq = 0; // Defs have special regalloc requirement? 208 209 // Side effect flags - When set, the flags have these meanings: 210 // 211 // hasSideEffects - The instruction has side effects that are not 212 // captured by any operands of the instruction or other flags. 213 // 214 // neverHasSideEffects - Set on an instruction with no pattern if it has no 215 // side effects. 216 bit hasSideEffects = 0; 217 bit neverHasSideEffects = 0; 218 219 // Is this instruction a "real" instruction (with a distinct machine 220 // encoding), or is it a pseudo instruction used for codegen modeling 221 // purposes. 222 bit isCodeGenOnly = 0; 223 224 InstrItinClass Itinerary = NoItinerary;// Execution steps used for scheduling. 225 226 string Constraints = ""; // OperandConstraint, e.g. $src = $dst. 227 228 /// DisableEncoding - List of operand names (e.g. "$op1,$op2") that should not 229 /// be encoded into the output machineinstr. 230 string DisableEncoding = ""; 231 232 /// Target-specific flags. This becomes the TSFlags field in TargetInstrDesc. 233 bits<32> TSFlags = 0; 234} 235 236/// Predicates - These are extra conditionals which are turned into instruction 237/// selector matching code. Currently each predicate is just a string. 238class Predicate<string cond> { 239 string CondString = cond; 240} 241 242/// NoHonorSignDependentRounding - This predicate is true if support for 243/// sign-dependent-rounding is not enabled. 244def NoHonorSignDependentRounding 245 : Predicate<"!HonorSignDependentRoundingFPMath()">; 246 247class Requires<list<Predicate> preds> { 248 list<Predicate> Predicates = preds; 249} 250 251/// ops definition - This is just a simple marker used to identify the operands 252/// list for an instruction. outs and ins are identical both syntatically and 253/// semantically, they are used to define def operands and use operands to 254/// improve readibility. This should be used like this: 255/// (outs R32:$dst), (ins R32:$src1, R32:$src2) or something similar. 256def ops; 257def outs; 258def ins; 259 260/// variable_ops definition - Mark this instruction as taking a variable number 261/// of operands. 262def variable_ops; 263 264 265/// PointerLikeRegClass - Values that are designed to have pointer width are 266/// derived from this. TableGen treats the register class as having a symbolic 267/// type that it doesn't know, and resolves the actual regclass to use by using 268/// the TargetRegisterInfo::getPointerRegClass() hook at codegen time. 269class PointerLikeRegClass<int Kind> { 270 int RegClassKind = Kind; 271} 272 273 274/// ptr_rc definition - Mark this operand as being a pointer value whose 275/// register class is resolved dynamically via a callback to TargetInstrInfo. 276/// FIXME: We should probably change this to a class which contain a list of 277/// flags. But currently we have but one flag. 278def ptr_rc : PointerLikeRegClass<0>; 279 280/// unknown definition - Mark this operand as being of unknown type, causing 281/// it to be resolved by inference in the context it is used. 282def unknown; 283 284/// AsmOperandClass - Representation for the kinds of operands which the target 285/// specific parser can create and the assembly matcher may need to distinguish. 286/// 287/// Operand classes are used to define the order in which instructions are 288/// matched, to ensure that the instruction which gets matched for any 289/// particular list of operands is deterministic. 290/// 291/// The target specific parser must be able to classify a parsed operand into a 292/// unique class which does not partially overlap with any other classes. It can 293/// match a subset of some other class, in which case the super class field 294/// should be defined. 295class AsmOperandClass { 296 /// The name to use for this class, which should be usable as an enum value. 297 string Name = ?; 298 299 /// The super class of this operand. 300 AsmOperandClass SuperClass = ?; 301 302 /// The name of the method on the target specific operand to call to test 303 /// whether the operand is an instance of this class. If not set, this will 304 /// default to "isFoo", where Foo is the AsmOperandClass name. The method 305 /// signature should be: 306 /// bool isFoo() const; 307 string PredicateMethod = ?; 308 309 /// The name of the method on the target specific operand to call to add the 310 /// target specific operand to an MCInst. If not set, this will default to 311 /// "addFooOperands", where Foo is the AsmOperandClass name. The method 312 /// signature should be: 313 /// void addFooOperands(MCInst &Inst, unsigned N) const; 314 string RenderMethod = ?; 315} 316 317def ImmAsmOperand : AsmOperandClass { 318 let Name = "Imm"; 319} 320 321/// Operand Types - These provide the built-in operand types that may be used 322/// by a target. Targets can optionally provide their own operand types as 323/// needed, though this should not be needed for RISC targets. 324class Operand<ValueType ty> { 325 ValueType Type = ty; 326 string PrintMethod = "printOperand"; 327 string AsmOperandLowerMethod = ?; 328 dag MIOperandInfo = (ops); 329 330 // ParserMatchClass - The "match class" that operands of this type fit 331 // in. Match classes are used to define the order in which instructions are 332 // match, to ensure that which instructions gets matched is deterministic. 333 // 334 // The target specific parser must be able to classify an parsed operand 335 // into a unique class, which does not partially overlap with any other 336 // classes. It can match a subset of some other class, in which case 337 // ParserMatchSuperClass should be set to the name of that class. 338 AsmOperandClass ParserMatchClass = ImmAsmOperand; 339} 340 341def i1imm : Operand<i1>; 342def i8imm : Operand<i8>; 343def i16imm : Operand<i16>; 344def i32imm : Operand<i32>; 345def i64imm : Operand<i64>; 346 347def f32imm : Operand<f32>; 348def f64imm : Operand<f64>; 349 350/// zero_reg definition - Special node to stand for the zero register. 351/// 352def zero_reg; 353 354/// PredicateOperand - This can be used to define a predicate operand for an 355/// instruction. OpTypes specifies the MIOperandInfo for the operand, and 356/// AlwaysVal specifies the value of this predicate when set to "always 357/// execute". 358class PredicateOperand<ValueType ty, dag OpTypes, dag AlwaysVal> 359 : Operand<ty> { 360 let MIOperandInfo = OpTypes; 361 dag DefaultOps = AlwaysVal; 362} 363 364/// OptionalDefOperand - This is used to define a optional definition operand 365/// for an instruction. DefaultOps is the register the operand represents if 366/// none is supplied, e.g. zero_reg. 367class OptionalDefOperand<ValueType ty, dag OpTypes, dag defaultops> 368 : Operand<ty> { 369 let MIOperandInfo = OpTypes; 370 dag DefaultOps = defaultops; 371} 372 373 374// InstrInfo - This class should only be instantiated once to provide parameters 375// which are global to the target machine. 376// 377class InstrInfo { 378 // Target can specify its instructions in either big or little-endian formats. 379 // For instance, while both Sparc and PowerPC are big-endian platforms, the 380 // Sparc manual specifies its instructions in the format [31..0] (big), while 381 // PowerPC specifies them using the format [0..31] (little). 382 bit isLittleEndianEncoding = 0; 383} 384 385// Standard Pseudo Instructions. 386let isCodeGenOnly = 1 in { 387def PHI : Instruction { 388 let OutOperandList = (outs); 389 let InOperandList = (ins variable_ops); 390 let AsmString = "PHINODE"; 391 let Namespace = "TargetOpcode"; 392} 393def INLINEASM : Instruction { 394 let OutOperandList = (outs); 395 let InOperandList = (ins variable_ops); 396 let AsmString = ""; 397 let Namespace = "TargetOpcode"; 398} 399def DBG_LABEL : Instruction { 400 let OutOperandList = (outs); 401 let InOperandList = (ins i32imm:$id); 402 let AsmString = ""; 403 let Namespace = "TargetOpcode"; 404 let hasCtrlDep = 1; 405 let isNotDuplicable = 1; 406} 407def EH_LABEL : Instruction { 408 let OutOperandList = (outs); 409 let InOperandList = (ins i32imm:$id); 410 let AsmString = ""; 411 let Namespace = "TargetOpcode"; 412 let hasCtrlDep = 1; 413 let isNotDuplicable = 1; 414} 415def GC_LABEL : Instruction { 416 let OutOperandList = (outs); 417 let InOperandList = (ins i32imm:$id); 418 let AsmString = ""; 419 let Namespace = "TargetOpcode"; 420 let hasCtrlDep = 1; 421 let isNotDuplicable = 1; 422} 423def KILL : Instruction { 424 let OutOperandList = (outs); 425 let InOperandList = (ins variable_ops); 426 let AsmString = ""; 427 let Namespace = "TargetOpcode"; 428 let neverHasSideEffects = 1; 429} 430def EXTRACT_SUBREG : Instruction { 431 let OutOperandList = (outs unknown:$dst); 432 let InOperandList = (ins unknown:$supersrc, i32imm:$subidx); 433 let AsmString = ""; 434 let Namespace = "TargetOpcode"; 435 let neverHasSideEffects = 1; 436} 437def INSERT_SUBREG : Instruction { 438 let OutOperandList = (outs unknown:$dst); 439 let InOperandList = (ins unknown:$supersrc, unknown:$subsrc, i32imm:$subidx); 440 let AsmString = ""; 441 let Namespace = "TargetOpcode"; 442 let neverHasSideEffects = 1; 443 let Constraints = "$supersrc = $dst"; 444} 445def IMPLICIT_DEF : Instruction { 446 let OutOperandList = (outs unknown:$dst); 447 let InOperandList = (ins); 448 let AsmString = ""; 449 let Namespace = "TargetOpcode"; 450 let neverHasSideEffects = 1; 451 let isReMaterializable = 1; 452 let isAsCheapAsAMove = 1; 453} 454def SUBREG_TO_REG : Instruction { 455 let OutOperandList = (outs unknown:$dst); 456 let InOperandList = (ins unknown:$implsrc, unknown:$subsrc, i32imm:$subidx); 457 let AsmString = ""; 458 let Namespace = "TargetOpcode"; 459 let neverHasSideEffects = 1; 460} 461def COPY_TO_REGCLASS : Instruction { 462 let OutOperandList = (outs unknown:$dst); 463 let InOperandList = (ins unknown:$src, i32imm:$regclass); 464 let AsmString = ""; 465 let Namespace = "TargetOpcode"; 466 let neverHasSideEffects = 1; 467 let isAsCheapAsAMove = 1; 468} 469def DBG_VALUE : Instruction { 470 let OutOperandList = (outs); 471 let InOperandList = (ins variable_ops); 472 let AsmString = "DBG_VALUE"; 473 let Namespace = "TargetOpcode"; 474 let isAsCheapAsAMove = 1; 475} 476} 477 478//===----------------------------------------------------------------------===// 479// AsmParser - This class can be implemented by targets that wish to implement 480// .s file parsing. 481// 482// Subtargets can have multiple different assembly parsers (e.g. AT&T vs Intel 483// syntax on X86 for example). 484// 485class AsmParser { 486 // AsmParserClassName - This specifies the suffix to use for the asmparser 487 // class. Generated AsmParser classes are always prefixed with the target 488 // name. 489 string AsmParserClassName = "AsmParser"; 490 491 // AsmParserInstCleanup - If non-empty, this is the name of a custom function on the 492 // AsmParser class to call on every matched instruction. This can be used to 493 // perform target specific instruction post-processing. 494 string AsmParserInstCleanup = ""; 495 496 // Variant - AsmParsers can be of multiple different variants. Variants are 497 // used to support targets that need to parser multiple formats for the 498 // assembly language. 499 int Variant = 0; 500 501 // CommentDelimiter - If given, the delimiter string used to recognize 502 // comments which are hard coded in the .td assembler strings for individual 503 // instructions. 504 string CommentDelimiter = ""; 505 506 // RegisterPrefix - If given, the token prefix which indicates a register 507 // token. This is used by the matcher to automatically recognize hard coded 508 // register tokens as constrained registers, instead of tokens, for the 509 // purposes of matching. 510 string RegisterPrefix = ""; 511} 512def DefaultAsmParser : AsmParser; 513 514 515//===----------------------------------------------------------------------===// 516// AsmWriter - This class can be implemented by targets that need to customize 517// the format of the .s file writer. 518// 519// Subtargets can have multiple different asmwriters (e.g. AT&T vs Intel syntax 520// on X86 for example). 521// 522class AsmWriter { 523 // AsmWriterClassName - This specifies the suffix to use for the asmwriter 524 // class. Generated AsmWriter classes are always prefixed with the target 525 // name. 526 string AsmWriterClassName = "AsmPrinter"; 527 528 // InstFormatName - AsmWriters can specify the name of the format string to 529 // print instructions with. 530 string InstFormatName = "AsmString"; 531 532 // Variant - AsmWriters can be of multiple different variants. Variants are 533 // used to support targets that need to emit assembly code in ways that are 534 // mostly the same for different targets, but have minor differences in 535 // syntax. If the asmstring contains {|} characters in them, this integer 536 // will specify which alternative to use. For example "{x|y|z}" with Variant 537 // == 1, will expand to "y". 538 int Variant = 0; 539 540 541 // FirstOperandColumn/OperandSpacing - If the assembler syntax uses a columnar 542 // layout, the asmwriter can actually generate output in this columns (in 543 // verbose-asm mode). These two values indicate the width of the first column 544 // (the "opcode" area) and the width to reserve for subsequent operands. When 545 // verbose asm mode is enabled, operands will be indented to respect this. 546 int FirstOperandColumn = -1; 547 548 // OperandSpacing - Space between operand columns. 549 int OperandSpacing = -1; 550} 551def DefaultAsmWriter : AsmWriter; 552 553 554//===----------------------------------------------------------------------===// 555// Target - This class contains the "global" target information 556// 557class Target { 558 // InstructionSet - Instruction set description for this target. 559 InstrInfo InstructionSet; 560 561 // AssemblyParsers - The AsmParser instances available for this target. 562 list<AsmParser> AssemblyParsers = [DefaultAsmParser]; 563 564 // AssemblyWriters - The AsmWriter instances available for this target. 565 list<AsmWriter> AssemblyWriters = [DefaultAsmWriter]; 566} 567 568//===----------------------------------------------------------------------===// 569// SubtargetFeature - A characteristic of the chip set. 570// 571class SubtargetFeature<string n, string a, string v, string d, 572 list<SubtargetFeature> i = []> { 573 // Name - Feature name. Used by command line (-mattr=) to determine the 574 // appropriate target chip. 575 // 576 string Name = n; 577 578 // Attribute - Attribute to be set by feature. 579 // 580 string Attribute = a; 581 582 // Value - Value the attribute to be set to by feature. 583 // 584 string Value = v; 585 586 // Desc - Feature description. Used by command line (-mattr=) to display help 587 // information. 588 // 589 string Desc = d; 590 591 // Implies - Features that this feature implies are present. If one of those 592 // features isn't set, then this one shouldn't be set either. 593 // 594 list<SubtargetFeature> Implies = i; 595} 596 597//===----------------------------------------------------------------------===// 598// Processor chip sets - These values represent each of the chip sets supported 599// by the scheduler. Each Processor definition requires corresponding 600// instruction itineraries. 601// 602class Processor<string n, ProcessorItineraries pi, list<SubtargetFeature> f> { 603 // Name - Chip set name. Used by command line (-mcpu=) to determine the 604 // appropriate target chip. 605 // 606 string Name = n; 607 608 // ProcItin - The scheduling information for the target processor. 609 // 610 ProcessorItineraries ProcItin = pi; 611 612 // Features - list of 613 list<SubtargetFeature> Features = f; 614} 615 616//===----------------------------------------------------------------------===// 617// Pull in the common support for calling conventions. 618// 619include "llvm/Target/TargetCallingConv.td" 620 621//===----------------------------------------------------------------------===// 622// Pull in the common support for DAG isel generation. 623// 624include "llvm/Target/TargetSelectionDAG.td" 625