Target.td revision eef965f04bab483a7d2fd46a7d51559197eda5cf
1//===- Target.td - Target Independent TableGen interface ---*- tablegen -*-===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This file defines the target-independent interfaces which should be 11// implemented by each target which is using a TableGen based code generator. 12// 13//===----------------------------------------------------------------------===// 14 15// Include all information about LLVM intrinsics. 16include "llvm/Intrinsics.td" 17 18//===----------------------------------------------------------------------===// 19// Register file description - These classes are used to fill in the target 20// description classes. 21 22class RegisterClass; // Forward def 23 24// SubRegIndex - Use instances of SubRegIndex to identify subregisters. 25class SubRegIndex { 26 string Namespace = ""; 27} 28 29// Register - You should define one instance of this class for each register 30// in the target machine. String n will become the "name" of the register. 31class Register<string n> { 32 string Namespace = ""; 33 string AsmName = n; 34 35 // SpillSize - If this value is set to a non-zero value, it is the size in 36 // bits of the spill slot required to hold this register. If this value is 37 // set to zero, the information is inferred from any register classes the 38 // register belongs to. 39 int SpillSize = 0; 40 41 // SpillAlignment - This value is used to specify the alignment required for 42 // spilling the register. Like SpillSize, this should only be explicitly 43 // specified if the register is not in a register class. 44 int SpillAlignment = 0; 45 46 // Aliases - A list of registers that this register overlaps with. A read or 47 // modification of this register can potentially read or modify the aliased 48 // registers. 49 list<Register> Aliases = []; 50 51 // SubRegs - A list of registers that are parts of this register. Note these 52 // are "immediate" sub-registers and the registers within the list do not 53 // themselves overlap. e.g. For X86, EAX's SubRegs list contains only [AX], 54 // not [AX, AH, AL]. 55 list<Register> SubRegs = []; 56 57 // SubRegIndices - For each register in SubRegs, specify the SubRegIndex used 58 // to address it. Sub-sub-register indices are automatically inherited from 59 // SubRegs. 60 list<SubRegIndex> SubRegIndices = []; 61 62 // CompositeIndices - Specify subreg indices that don't correspond directly to 63 // a register in SubRegs and are not inherited. The following formats are 64 // supported: 65 // 66 // (a) Identity - Reg:a == Reg 67 // (a b) Alias - Reg:a == Reg:b 68 // (a b,c) Composite - Reg:a == (Reg:b):c 69 // 70 // This can be used to disambiguate a sub-sub-register that exists in more 71 // than one subregister and other weird stuff. 72 list<dag> CompositeIndices = []; 73 74 // DwarfNumbers - Numbers used internally by gcc/gdb to identify the register. 75 // These values can be determined by locating the <target>.h file in the 76 // directory llvmgcc/gcc/config/<target>/ and looking for REGISTER_NAMES. The 77 // order of these names correspond to the enumeration used by gcc. A value of 78 // -1 indicates that the gcc number is undefined and -2 that register number 79 // is invalid for this mode/flavour. 80 list<int> DwarfNumbers = []; 81} 82 83// RegisterWithSubRegs - This can be used to define instances of Register which 84// need to specify sub-registers. 85// List "subregs" specifies which registers are sub-registers to this one. This 86// is used to populate the SubRegs and AliasSet fields of TargetRegisterDesc. 87// This allows the code generator to be careful not to put two values with 88// overlapping live ranges into registers which alias. 89class RegisterWithSubRegs<string n, list<Register> subregs> : Register<n> { 90 let SubRegs = subregs; 91} 92 93// RegisterClass - Now that all of the registers are defined, and aliases 94// between registers are defined, specify which registers belong to which 95// register classes. This also defines the default allocation order of 96// registers by register allocators. 97// 98class RegisterClass<string namespace, list<ValueType> regTypes, int alignment, 99 list<Register> regList> { 100 string Namespace = namespace; 101 102 // RegType - Specify the list ValueType of the registers in this register 103 // class. Note that all registers in a register class must have the same 104 // ValueTypes. This is a list because some targets permit storing different 105 // types in same register, for example vector values with 128-bit total size, 106 // but different count/size of items, like SSE on x86. 107 // 108 list<ValueType> RegTypes = regTypes; 109 110 // Size - Specify the spill size in bits of the registers. A default value of 111 // zero lets tablgen pick an appropriate size. 112 int Size = 0; 113 114 // Alignment - Specify the alignment required of the registers when they are 115 // stored or loaded to memory. 116 // 117 int Alignment = alignment; 118 119 // CopyCost - This value is used to specify the cost of copying a value 120 // between two registers in this register class. The default value is one 121 // meaning it takes a single instruction to perform the copying. A negative 122 // value means copying is extremely expensive or impossible. 123 int CopyCost = 1; 124 125 // MemberList - Specify which registers are in this class. If the 126 // allocation_order_* method are not specified, this also defines the order of 127 // allocation used by the register allocator. 128 // 129 list<Register> MemberList = regList; 130 131 // SubRegClasses - Specify the register class of subregisters as a list of 132 // dags: (RegClass SubRegIndex, SubRegindex, ...) 133 list<dag> SubRegClasses = []; 134 135 // MethodProtos/MethodBodies - These members can be used to insert arbitrary 136 // code into a generated register class. The normal usage of this is to 137 // overload virtual methods. 138 code MethodProtos = [{}]; 139 code MethodBodies = [{}]; 140} 141 142 143//===----------------------------------------------------------------------===// 144// DwarfRegNum - This class provides a mapping of the llvm register enumeration 145// to the register numbering used by gcc and gdb. These values are used by a 146// debug information writer to describe where values may be located during 147// execution. 148class DwarfRegNum<list<int> Numbers> { 149 // DwarfNumbers - Numbers used internally by gcc/gdb to identify the register. 150 // These values can be determined by locating the <target>.h file in the 151 // directory llvmgcc/gcc/config/<target>/ and looking for REGISTER_NAMES. The 152 // order of these names correspond to the enumeration used by gcc. A value of 153 // -1 indicates that the gcc number is undefined and -2 that register number 154 // is invalid for this mode/flavour. 155 list<int> DwarfNumbers = Numbers; 156} 157 158//===----------------------------------------------------------------------===// 159// Pull in the common support for scheduling 160// 161include "llvm/Target/TargetSchedule.td" 162 163class Predicate; // Forward def 164 165//===----------------------------------------------------------------------===// 166// Instruction set description - These classes correspond to the C++ classes in 167// the Target/TargetInstrInfo.h file. 168// 169class Instruction { 170 string Namespace = ""; 171 172 dag OutOperandList; // An dag containing the MI def operand list. 173 dag InOperandList; // An dag containing the MI use operand list. 174 string AsmString = ""; // The .s format to print the instruction with. 175 176 // Pattern - Set to the DAG pattern for this instruction, if we know of one, 177 // otherwise, uninitialized. 178 list<dag> Pattern; 179 180 // The follow state will eventually be inferred automatically from the 181 // instruction pattern. 182 183 list<Register> Uses = []; // Default to using no non-operand registers 184 list<Register> Defs = []; // Default to modifying no non-operand registers 185 186 // Predicates - List of predicates which will be turned into isel matching 187 // code. 188 list<Predicate> Predicates = []; 189 190 // Code size. 191 int CodeSize = 0; 192 193 // Added complexity passed onto matching pattern. 194 int AddedComplexity = 0; 195 196 // These bits capture information about the high-level semantics of the 197 // instruction. 198 bit isReturn = 0; // Is this instruction a return instruction? 199 bit isBranch = 0; // Is this instruction a branch instruction? 200 bit isIndirectBranch = 0; // Is this instruction an indirect branch? 201 bit isCompare = 0; // Is this instruction a comparison instruction? 202 bit isMoveImm = 0; // Is this instruction a move immediate instruction? 203 bit isBitcast = 0; // Is this instruction a bitcast instruction? 204 bit isBarrier = 0; // Can control flow fall through this instruction? 205 bit isCall = 0; // Is this instruction a call instruction? 206 bit canFoldAsLoad = 0; // Can this be folded as a simple memory operand? 207 bit mayLoad = 0; // Is it possible for this inst to read memory? 208 bit mayStore = 0; // Is it possible for this inst to write memory? 209 bit isConvertibleToThreeAddress = 0; // Can this 2-addr instruction promote? 210 bit isCommutable = 0; // Is this 3 operand instruction commutable? 211 bit isTerminator = 0; // Is this part of the terminator for a basic block? 212 bit isReMaterializable = 0; // Is this instruction re-materializable? 213 bit isPredicable = 0; // Is this instruction predicable? 214 bit hasDelaySlot = 0; // Does this instruction have an delay slot? 215 bit usesCustomInserter = 0; // Pseudo instr needing special help. 216 bit hasCtrlDep = 0; // Does this instruction r/w ctrl-flow chains? 217 bit isNotDuplicable = 0; // Is it unsafe to duplicate this instruction? 218 bit isAsCheapAsAMove = 0; // As cheap (or cheaper) than a move instruction. 219 bit hasExtraSrcRegAllocReq = 0; // Sources have special regalloc requirement? 220 bit hasExtraDefRegAllocReq = 0; // Defs have special regalloc requirement? 221 222 // Side effect flags - When set, the flags have these meanings: 223 // 224 // hasSideEffects - The instruction has side effects that are not 225 // captured by any operands of the instruction or other flags. 226 // 227 // neverHasSideEffects - Set on an instruction with no pattern if it has no 228 // side effects. 229 bit hasSideEffects = 0; 230 bit neverHasSideEffects = 0; 231 232 // Is this instruction a "real" instruction (with a distinct machine 233 // encoding), or is it a pseudo instruction used for codegen modeling 234 // purposes. 235 bit isCodeGenOnly = 0; 236 237 // Is this instruction a pseudo instruction for use by the assembler parser. 238 bit isAsmParserOnly = 0; 239 240 InstrItinClass Itinerary = NoItinerary;// Execution steps used for scheduling. 241 242 string Constraints = ""; // OperandConstraint, e.g. $src = $dst. 243 244 /// DisableEncoding - List of operand names (e.g. "$op1,$op2") that should not 245 /// be encoded into the output machineinstr. 246 string DisableEncoding = ""; 247 248 string PostEncoderMethod = ""; 249 string DecoderMethod = ""; 250 251 /// Target-specific flags. This becomes the TSFlags field in TargetInstrDesc. 252 bits<64> TSFlags = 0; 253 254 ///@name Assembler Parser Support 255 ///@{ 256 257 string AsmMatchConverter = ""; 258 259 ///@} 260} 261 262/// Predicates - These are extra conditionals which are turned into instruction 263/// selector matching code. Currently each predicate is just a string. 264class Predicate<string cond> { 265 string CondString = cond; 266 267 /// AssemblerMatcherPredicate - If this feature can be used by the assembler 268 /// matcher, this is true. Targets should set this by inheriting their 269 /// feature from the AssemblerPredicate class in addition to Predicate. 270 bit AssemblerMatcherPredicate = 0; 271} 272 273/// NoHonorSignDependentRounding - This predicate is true if support for 274/// sign-dependent-rounding is not enabled. 275def NoHonorSignDependentRounding 276 : Predicate<"!HonorSignDependentRoundingFPMath()">; 277 278class Requires<list<Predicate> preds> { 279 list<Predicate> Predicates = preds; 280} 281 282/// ops definition - This is just a simple marker used to identify the operand 283/// list for an instruction. outs and ins are identical both syntactically and 284/// semanticallyr; they are used to define def operands and use operands to 285/// improve readibility. This should be used like this: 286/// (outs R32:$dst), (ins R32:$src1, R32:$src2) or something similar. 287def ops; 288def outs; 289def ins; 290 291/// variable_ops definition - Mark this instruction as taking a variable number 292/// of operands. 293def variable_ops; 294 295 296/// PointerLikeRegClass - Values that are designed to have pointer width are 297/// derived from this. TableGen treats the register class as having a symbolic 298/// type that it doesn't know, and resolves the actual regclass to use by using 299/// the TargetRegisterInfo::getPointerRegClass() hook at codegen time. 300class PointerLikeRegClass<int Kind> { 301 int RegClassKind = Kind; 302} 303 304 305/// ptr_rc definition - Mark this operand as being a pointer value whose 306/// register class is resolved dynamically via a callback to TargetInstrInfo. 307/// FIXME: We should probably change this to a class which contain a list of 308/// flags. But currently we have but one flag. 309def ptr_rc : PointerLikeRegClass<0>; 310 311/// unknown definition - Mark this operand as being of unknown type, causing 312/// it to be resolved by inference in the context it is used. 313def unknown; 314 315/// AsmOperandClass - Representation for the kinds of operands which the target 316/// specific parser can create and the assembly matcher may need to distinguish. 317/// 318/// Operand classes are used to define the order in which instructions are 319/// matched, to ensure that the instruction which gets matched for any 320/// particular list of operands is deterministic. 321/// 322/// The target specific parser must be able to classify a parsed operand into a 323/// unique class which does not partially overlap with any other classes. It can 324/// match a subset of some other class, in which case the super class field 325/// should be defined. 326class AsmOperandClass { 327 /// The name to use for this class, which should be usable as an enum value. 328 string Name = ?; 329 330 /// The super classes of this operand. 331 list<AsmOperandClass> SuperClasses = []; 332 333 /// The name of the method on the target specific operand to call to test 334 /// whether the operand is an instance of this class. If not set, this will 335 /// default to "isFoo", where Foo is the AsmOperandClass name. The method 336 /// signature should be: 337 /// bool isFoo() const; 338 string PredicateMethod = ?; 339 340 /// The name of the method on the target specific operand to call to add the 341 /// target specific operand to an MCInst. If not set, this will default to 342 /// "addFooOperands", where Foo is the AsmOperandClass name. The method 343 /// signature should be: 344 /// void addFooOperands(MCInst &Inst, unsigned N) const; 345 string RenderMethod = ?; 346 347 /// The name of the method on the target specific operand to call to custom 348 /// handle the operand parsing. This is useful when the operands do not relate 349 /// to immediates or registers and are very instruction specific (as flags to 350 /// set in a processor register, coprocessor number, ...). 351 string ParserMethod = ?; 352} 353 354def ImmAsmOperand : AsmOperandClass { 355 let Name = "Imm"; 356} 357 358/// Operand Types - These provide the built-in operand types that may be used 359/// by a target. Targets can optionally provide their own operand types as 360/// needed, though this should not be needed for RISC targets. 361class Operand<ValueType ty> { 362 ValueType Type = ty; 363 string PrintMethod = "printOperand"; 364 string EncoderMethod = ""; 365 string DecoderMethod = ""; 366 string AsmOperandLowerMethod = ?; 367 dag MIOperandInfo = (ops); 368 369 // ParserMatchClass - The "match class" that operands of this type fit 370 // in. Match classes are used to define the order in which instructions are 371 // match, to ensure that which instructions gets matched is deterministic. 372 // 373 // The target specific parser must be able to classify an parsed operand into 374 // a unique class, which does not partially overlap with any other classes. It 375 // can match a subset of some other class, in which case the AsmOperandClass 376 // should declare the other operand as one of its super classes. 377 AsmOperandClass ParserMatchClass = ImmAsmOperand; 378} 379 380def i1imm : Operand<i1>; 381def i8imm : Operand<i8>; 382def i16imm : Operand<i16>; 383def i32imm : Operand<i32>; 384def i64imm : Operand<i64>; 385 386def f32imm : Operand<f32>; 387def f64imm : Operand<f64>; 388 389/// zero_reg definition - Special node to stand for the zero register. 390/// 391def zero_reg; 392 393/// PredicateOperand - This can be used to define a predicate operand for an 394/// instruction. OpTypes specifies the MIOperandInfo for the operand, and 395/// AlwaysVal specifies the value of this predicate when set to "always 396/// execute". 397class PredicateOperand<ValueType ty, dag OpTypes, dag AlwaysVal> 398 : Operand<ty> { 399 let MIOperandInfo = OpTypes; 400 dag DefaultOps = AlwaysVal; 401} 402 403/// OptionalDefOperand - This is used to define a optional definition operand 404/// for an instruction. DefaultOps is the register the operand represents if 405/// none is supplied, e.g. zero_reg. 406class OptionalDefOperand<ValueType ty, dag OpTypes, dag defaultops> 407 : Operand<ty> { 408 let MIOperandInfo = OpTypes; 409 dag DefaultOps = defaultops; 410} 411 412 413// InstrInfo - This class should only be instantiated once to provide parameters 414// which are global to the target machine. 415// 416class InstrInfo { 417 // Target can specify its instructions in either big or little-endian formats. 418 // For instance, while both Sparc and PowerPC are big-endian platforms, the 419 // Sparc manual specifies its instructions in the format [31..0] (big), while 420 // PowerPC specifies them using the format [0..31] (little). 421 bit isLittleEndianEncoding = 0; 422} 423 424// Standard Pseudo Instructions. 425// This list must match TargetOpcodes.h and CodeGenTarget.cpp. 426// Only these instructions are allowed in the TargetOpcode namespace. 427let isCodeGenOnly = 1, Namespace = "TargetOpcode" in { 428def PHI : Instruction { 429 let OutOperandList = (outs); 430 let InOperandList = (ins variable_ops); 431 let AsmString = "PHINODE"; 432} 433def INLINEASM : Instruction { 434 let OutOperandList = (outs); 435 let InOperandList = (ins variable_ops); 436 let AsmString = ""; 437 let neverHasSideEffects = 1; // Note side effect is encoded in an operand. 438} 439def PROLOG_LABEL : Instruction { 440 let OutOperandList = (outs); 441 let InOperandList = (ins i32imm:$id); 442 let AsmString = ""; 443 let hasCtrlDep = 1; 444 let isNotDuplicable = 1; 445} 446def EH_LABEL : Instruction { 447 let OutOperandList = (outs); 448 let InOperandList = (ins i32imm:$id); 449 let AsmString = ""; 450 let hasCtrlDep = 1; 451 let isNotDuplicable = 1; 452} 453def GC_LABEL : Instruction { 454 let OutOperandList = (outs); 455 let InOperandList = (ins i32imm:$id); 456 let AsmString = ""; 457 let hasCtrlDep = 1; 458 let isNotDuplicable = 1; 459} 460def KILL : Instruction { 461 let OutOperandList = (outs); 462 let InOperandList = (ins variable_ops); 463 let AsmString = ""; 464 let neverHasSideEffects = 1; 465} 466def EXTRACT_SUBREG : Instruction { 467 let OutOperandList = (outs unknown:$dst); 468 let InOperandList = (ins unknown:$supersrc, i32imm:$subidx); 469 let AsmString = ""; 470 let neverHasSideEffects = 1; 471} 472def INSERT_SUBREG : Instruction { 473 let OutOperandList = (outs unknown:$dst); 474 let InOperandList = (ins unknown:$supersrc, unknown:$subsrc, i32imm:$subidx); 475 let AsmString = ""; 476 let neverHasSideEffects = 1; 477 let Constraints = "$supersrc = $dst"; 478} 479def IMPLICIT_DEF : Instruction { 480 let OutOperandList = (outs unknown:$dst); 481 let InOperandList = (ins); 482 let AsmString = ""; 483 let neverHasSideEffects = 1; 484 let isReMaterializable = 1; 485 let isAsCheapAsAMove = 1; 486} 487def SUBREG_TO_REG : Instruction { 488 let OutOperandList = (outs unknown:$dst); 489 let InOperandList = (ins unknown:$implsrc, unknown:$subsrc, i32imm:$subidx); 490 let AsmString = ""; 491 let neverHasSideEffects = 1; 492} 493def COPY_TO_REGCLASS : Instruction { 494 let OutOperandList = (outs unknown:$dst); 495 let InOperandList = (ins unknown:$src, i32imm:$regclass); 496 let AsmString = ""; 497 let neverHasSideEffects = 1; 498 let isAsCheapAsAMove = 1; 499} 500def DBG_VALUE : Instruction { 501 let OutOperandList = (outs); 502 let InOperandList = (ins variable_ops); 503 let AsmString = "DBG_VALUE"; 504 let neverHasSideEffects = 1; 505} 506def REG_SEQUENCE : Instruction { 507 let OutOperandList = (outs unknown:$dst); 508 let InOperandList = (ins variable_ops); 509 let AsmString = ""; 510 let neverHasSideEffects = 1; 511 let isAsCheapAsAMove = 1; 512} 513def COPY : Instruction { 514 let OutOperandList = (outs unknown:$dst); 515 let InOperandList = (ins unknown:$src); 516 let AsmString = ""; 517 let neverHasSideEffects = 1; 518 let isAsCheapAsAMove = 1; 519} 520} 521 522//===----------------------------------------------------------------------===// 523// AsmParser - This class can be implemented by targets that wish to implement 524// .s file parsing. 525// 526// Subtargets can have multiple different assembly parsers (e.g. AT&T vs Intel 527// syntax on X86 for example). 528// 529class AsmParser { 530 // AsmParserClassName - This specifies the suffix to use for the asmparser 531 // class. Generated AsmParser classes are always prefixed with the target 532 // name. 533 string AsmParserClassName = "AsmParser"; 534 535 // AsmParserInstCleanup - If non-empty, this is the name of a custom member 536 // function of the AsmParser class to call on every matched instruction. 537 // This can be used to perform target specific instruction post-processing. 538 string AsmParserInstCleanup = ""; 539 540 // Variant - AsmParsers can be of multiple different variants. Variants are 541 // used to support targets that need to parser multiple formats for the 542 // assembly language. 543 int Variant = 0; 544 545 // CommentDelimiter - If given, the delimiter string used to recognize 546 // comments which are hard coded in the .td assembler strings for individual 547 // instructions. 548 string CommentDelimiter = ""; 549 550 // RegisterPrefix - If given, the token prefix which indicates a register 551 // token. This is used by the matcher to automatically recognize hard coded 552 // register tokens as constrained registers, instead of tokens, for the 553 // purposes of matching. 554 string RegisterPrefix = ""; 555} 556def DefaultAsmParser : AsmParser; 557 558/// AssemblerPredicate - This is a Predicate that can be used when the assembler 559/// matches instructions and aliases. 560class AssemblerPredicate { 561 bit AssemblerMatcherPredicate = 1; 562} 563 564 565 566/// MnemonicAlias - This class allows targets to define assembler mnemonic 567/// aliases. This should be used when all forms of one mnemonic are accepted 568/// with a different mnemonic. For example, X86 allows: 569/// sal %al, 1 -> shl %al, 1 570/// sal %ax, %cl -> shl %ax, %cl 571/// sal %eax, %cl -> shl %eax, %cl 572/// etc. Though "sal" is accepted with many forms, all of them are directly 573/// translated to a shl, so it can be handled with (in the case of X86, it 574/// actually has one for each suffix as well): 575/// def : MnemonicAlias<"sal", "shl">; 576/// 577/// Mnemonic aliases are mapped before any other translation in the match phase, 578/// and do allow Requires predicates, e.g.: 579/// 580/// def : MnemonicAlias<"pushf", "pushfq">, Requires<[In64BitMode]>; 581/// def : MnemonicAlias<"pushf", "pushfl">, Requires<[In32BitMode]>; 582/// 583class MnemonicAlias<string From, string To> { 584 string FromMnemonic = From; 585 string ToMnemonic = To; 586 587 // Predicates - Predicates that must be true for this remapping to happen. 588 list<Predicate> Predicates = []; 589} 590 591/// InstAlias - This defines an alternate assembly syntax that is allowed to 592/// match an instruction that has a different (more canonical) assembly 593/// representation. 594class InstAlias<string Asm, dag Result, bit Emit = 0b1> { 595 string AsmString = Asm; // The .s format to match the instruction with. 596 dag ResultInst = Result; // The MCInst to generate. 597 bit EmitAlias = Emit; // Emit the alias instead of what's aliased. 598 599 // Predicates - Predicates that must be true for this to match. 600 list<Predicate> Predicates = []; 601} 602 603//===----------------------------------------------------------------------===// 604// AsmWriter - This class can be implemented by targets that need to customize 605// the format of the .s file writer. 606// 607// Subtargets can have multiple different asmwriters (e.g. AT&T vs Intel syntax 608// on X86 for example). 609// 610class AsmWriter { 611 // AsmWriterClassName - This specifies the suffix to use for the asmwriter 612 // class. Generated AsmWriter classes are always prefixed with the target 613 // name. 614 string AsmWriterClassName = "AsmPrinter"; 615 616 // Variant - AsmWriters can be of multiple different variants. Variants are 617 // used to support targets that need to emit assembly code in ways that are 618 // mostly the same for different targets, but have minor differences in 619 // syntax. If the asmstring contains {|} characters in them, this integer 620 // will specify which alternative to use. For example "{x|y|z}" with Variant 621 // == 1, will expand to "y". 622 int Variant = 0; 623 624 625 // FirstOperandColumn/OperandSpacing - If the assembler syntax uses a columnar 626 // layout, the asmwriter can actually generate output in this columns (in 627 // verbose-asm mode). These two values indicate the width of the first column 628 // (the "opcode" area) and the width to reserve for subsequent operands. When 629 // verbose asm mode is enabled, operands will be indented to respect this. 630 int FirstOperandColumn = -1; 631 632 // OperandSpacing - Space between operand columns. 633 int OperandSpacing = -1; 634 635 // isMCAsmWriter - Is this assembly writer for an MC emitter? This controls 636 // generation of the printInstruction() method. For MC printers, it takes 637 // an MCInstr* operand, otherwise it takes a MachineInstr*. 638 bit isMCAsmWriter = 0; 639} 640def DefaultAsmWriter : AsmWriter; 641 642 643//===----------------------------------------------------------------------===// 644// Target - This class contains the "global" target information 645// 646class Target { 647 // InstructionSet - Instruction set description for this target. 648 InstrInfo InstructionSet; 649 650 // AssemblyParsers - The AsmParser instances available for this target. 651 list<AsmParser> AssemblyParsers = [DefaultAsmParser]; 652 653 // AssemblyWriters - The AsmWriter instances available for this target. 654 list<AsmWriter> AssemblyWriters = [DefaultAsmWriter]; 655} 656 657//===----------------------------------------------------------------------===// 658// SubtargetFeature - A characteristic of the chip set. 659// 660class SubtargetFeature<string n, string a, string v, string d, 661 list<SubtargetFeature> i = []> { 662 // Name - Feature name. Used by command line (-mattr=) to determine the 663 // appropriate target chip. 664 // 665 string Name = n; 666 667 // Attribute - Attribute to be set by feature. 668 // 669 string Attribute = a; 670 671 // Value - Value the attribute to be set to by feature. 672 // 673 string Value = v; 674 675 // Desc - Feature description. Used by command line (-mattr=) to display help 676 // information. 677 // 678 string Desc = d; 679 680 // Implies - Features that this feature implies are present. If one of those 681 // features isn't set, then this one shouldn't be set either. 682 // 683 list<SubtargetFeature> Implies = i; 684} 685 686//===----------------------------------------------------------------------===// 687// Processor chip sets - These values represent each of the chip sets supported 688// by the scheduler. Each Processor definition requires corresponding 689// instruction itineraries. 690// 691class Processor<string n, ProcessorItineraries pi, list<SubtargetFeature> f> { 692 // Name - Chip set name. Used by command line (-mcpu=) to determine the 693 // appropriate target chip. 694 // 695 string Name = n; 696 697 // ProcItin - The scheduling information for the target processor. 698 // 699 ProcessorItineraries ProcItin = pi; 700 701 // Features - list of 702 list<SubtargetFeature> Features = f; 703} 704 705//===----------------------------------------------------------------------===// 706// Pull in the common support for calling conventions. 707// 708include "llvm/Target/TargetCallingConv.td" 709 710//===----------------------------------------------------------------------===// 711// Pull in the common support for DAG isel generation. 712// 713include "llvm/Target/TargetSelectionDAG.td" 714