TargetInstrInfo.h revision 08d52071bae2f8cc2e9aa6a451118b83d043813b
1//===-- llvm/Target/TargetInstrInfo.h - Instruction Info --------*- C++ -*-===//
2//
3//                     The LLVM Compiler Infrastructure
4//
5// This file was developed by the LLVM research group and is distributed under
6// the University of Illinois Open Source License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10// This file describes the target machine instructions to the code generator.
11//
12//===----------------------------------------------------------------------===//
13
14#ifndef LLVM_TARGET_TARGETINSTRINFO_H
15#define LLVM_TARGET_TARGETINSTRINFO_H
16
17#include "llvm/CodeGen/MachineBasicBlock.h"
18#include "llvm/CodeGen/MachineFunction.h"
19#include "llvm/Support/DataTypes.h"
20#include <vector>
21#include <cassert>
22
23namespace llvm {
24
25class MachineInstr;
26class TargetMachine;
27class MachineCodeForInstruction;
28class TargetRegisterClass;
29class LiveVariables;
30
31//---------------------------------------------------------------------------
32// Data types used to define information about a single machine instruction
33//---------------------------------------------------------------------------
34
35typedef short MachineOpCode;
36typedef unsigned InstrSchedClass;
37
38//---------------------------------------------------------------------------
39// struct TargetInstrDescriptor:
40//  Predefined information about each machine instruction.
41//  Designed to initialized statically.
42//
43
44const unsigned M_BRANCH_FLAG           = 1 << 0;
45const unsigned M_CALL_FLAG             = 1 << 1;
46const unsigned M_RET_FLAG              = 1 << 2;
47const unsigned M_BARRIER_FLAG          = 1 << 3;
48const unsigned M_DELAY_SLOT_FLAG       = 1 << 4;
49const unsigned M_LOAD_FLAG             = 1 << 5;
50const unsigned M_STORE_FLAG            = 1 << 6;
51
52// M_CONVERTIBLE_TO_3_ADDR - This is a 2-address instruction which can be
53// changed into a 3-address instruction if the first two operands cannot be
54// assigned to the same register.  The target must implement the
55// TargetInstrInfo::convertToThreeAddress method for this instruction.
56const unsigned M_CONVERTIBLE_TO_3_ADDR = 1 << 7;
57
58// This M_COMMUTABLE - is a 2- or 3-address instruction (of the form X = op Y,
59// Z), which produces the same result if Y and Z are exchanged.
60const unsigned M_COMMUTABLE            = 1 << 8;
61
62// M_TERMINATOR_FLAG - Is this instruction part of the terminator for a basic
63// block?  Typically this is things like return and branch instructions.
64// Various passes use this to insert code into the bottom of a basic block, but
65// before control flow occurs.
66const unsigned M_TERMINATOR_FLAG       = 1 << 9;
67
68// M_USES_CUSTOM_DAG_SCHED_INSERTION - Set if this instruction requires custom
69// insertion support when the DAG scheduler is inserting it into a machine basic
70// block.
71const unsigned M_USES_CUSTOM_DAG_SCHED_INSERTION = 1 << 10;
72
73// M_VARIABLE_OPS - Set if this instruction can have a variable number of extra
74// operands in addition to the minimum number operands specified.
75const unsigned M_VARIABLE_OPS = 1 << 11;
76
77// M_PREDICABLE - Set if this instruction has a predicate operand that
78// controls execution. It may be set to 'always'.
79const unsigned M_PREDICABLE = 1 << 12;
80
81// M_REMATERIALIZIBLE - Set if this instruction can be trivally re-materialized
82// at any time, e.g. constant generation, load from constant pool.
83const unsigned M_REMATERIALIZIBLE = 1 << 13;
84
85// M_NOT_DUPLICABLE - Set if this instruction cannot be safely duplicated.
86// (e.g. instructions with unique labels attached).
87const unsigned M_NOT_DUPLICABLE = 1 << 14;
88
89// M_HAS_OPTIONAL_DEF - Set if this instruction has an optional definition, e.g.
90// ARM instructions which can set condition code if 's' bit is set.
91const unsigned M_HAS_OPTIONAL_DEF = 1 << 15;
92
93// Machine operand flags
94// M_LOOK_UP_PTR_REG_CLASS - Set if this operand is a pointer value and it
95// requires a callback to look up its register class.
96const unsigned M_LOOK_UP_PTR_REG_CLASS = 1 << 0;
97
98/// M_PREDICATE_OPERAND - Set if this is one of the operands that made up of the
99/// predicate operand that controls an M_PREDICATED instruction.
100const unsigned M_PREDICATE_OPERAND = 1 << 1;
101
102/// M_OPTIONAL_DEF_OPERAND - Set if this operand is a optional def.
103///
104const unsigned M_OPTIONAL_DEF_OPERAND = 1 << 2;
105
106namespace TOI {
107  // Operand constraints: only "tied_to" for now.
108  enum OperandConstraint {
109    TIED_TO = 0  // Must be allocated the same register as.
110  };
111}
112
113/// TargetOperandInfo - This holds information about one operand of a machine
114/// instruction, indicating the register class for register operands, etc.
115///
116class TargetOperandInfo {
117public:
118  /// RegClass - This specifies the register class enumeration of the operand
119  /// if the operand is a register.  If not, this contains 0.
120  unsigned short RegClass;
121  unsigned short Flags;
122  /// Lower 16 bits are used to specify which constraints are set. The higher 16
123  /// bits are used to specify the value of constraints (4 bits each).
124  unsigned int Constraints;
125  /// Currently no other information.
126};
127
128
129class TargetInstrDescriptor {
130public:
131  MachineOpCode   Opcode;        // The opcode.
132  unsigned short  numOperands;   // Num of args (may be more if variable_ops).
133  const char *    Name;          // Assembly language mnemonic for the opcode.
134  InstrSchedClass schedClass;    // enum  identifying instr sched class
135  unsigned        Flags;         // flags identifying machine instr class
136  unsigned        TSFlags;       // Target Specific Flag values
137  const unsigned *ImplicitUses;  // Registers implicitly read by this instr
138  const unsigned *ImplicitDefs;  // Registers implicitly defined by this instr
139  const TargetOperandInfo *OpInfo; // 'numOperands' entries about operands.
140
141  /// getOperandConstraint - Returns the value of the specific constraint if
142  /// it is set. Returns -1 if it is not set.
143  int getOperandConstraint(unsigned OpNum,
144                           TOI::OperandConstraint Constraint) const {
145    assert((OpNum < numOperands || (Flags & M_VARIABLE_OPS)) &&
146           "Invalid operand # of TargetInstrInfo");
147    if (OpNum < numOperands &&
148        (OpInfo[OpNum].Constraints & (1 << Constraint))) {
149      unsigned Pos = 16 + Constraint * 4;
150      return (int)(OpInfo[OpNum].Constraints >> Pos) & 0xf;
151    }
152    return -1;
153  }
154
155  /// findTiedToSrcOperand - Returns the operand that is tied to the specified
156  /// dest operand. Returns -1 if there isn't one.
157  int findTiedToSrcOperand(unsigned OpNum) const;
158};
159
160
161//---------------------------------------------------------------------------
162///
163/// TargetInstrInfo - Interface to description of machine instructions
164///
165class TargetInstrInfo {
166  const TargetInstrDescriptor* desc;    // raw array to allow static init'n
167  unsigned NumOpcodes;                  // number of entries in the desc array
168  unsigned numRealOpCodes;              // number of non-dummy op codes
169
170  TargetInstrInfo(const TargetInstrInfo &);  // DO NOT IMPLEMENT
171  void operator=(const TargetInstrInfo &);   // DO NOT IMPLEMENT
172public:
173  TargetInstrInfo(const TargetInstrDescriptor *desc, unsigned NumOpcodes);
174  virtual ~TargetInstrInfo();
175
176  // Invariant opcodes: All instruction sets have these as their low opcodes.
177  enum {
178    PHI = 0,
179    INLINEASM = 1,
180    LABEL = 2,
181    EXTRACT_SUBREG = 3,
182    INSERT_SUBREG = 4
183  };
184
185  unsigned getNumOpcodes() const { return NumOpcodes; }
186
187  /// get - Return the machine instruction descriptor that corresponds to the
188  /// specified instruction opcode.
189  ///
190  const TargetInstrDescriptor& get(MachineOpCode Opcode) const {
191    assert((unsigned)Opcode < NumOpcodes);
192    return desc[Opcode];
193  }
194
195  const char *getName(MachineOpCode Opcode) const {
196    return get(Opcode).Name;
197  }
198
199  int getNumOperands(MachineOpCode Opcode) const {
200    return get(Opcode).numOperands;
201  }
202
203  InstrSchedClass getSchedClass(MachineOpCode Opcode) const {
204    return get(Opcode).schedClass;
205  }
206
207  const unsigned *getImplicitUses(MachineOpCode Opcode) const {
208    return get(Opcode).ImplicitUses;
209  }
210
211  const unsigned *getImplicitDefs(MachineOpCode Opcode) const {
212    return get(Opcode).ImplicitDefs;
213  }
214
215
216  //
217  // Query instruction class flags according to the machine-independent
218  // flags listed above.
219  //
220  bool isReturn(MachineOpCode Opcode) const {
221    return get(Opcode).Flags & M_RET_FLAG;
222  }
223
224  bool isCommutableInstr(MachineOpCode Opcode) const {
225    return get(Opcode).Flags & M_COMMUTABLE;
226  }
227  bool isTerminatorInstr(MachineOpCode Opcode) const {
228    return get(Opcode).Flags & M_TERMINATOR_FLAG;
229  }
230
231  bool isBranch(MachineOpCode Opcode) const {
232    return get(Opcode).Flags & M_BRANCH_FLAG;
233  }
234
235  /// isBarrier - Returns true if the specified instruction stops control flow
236  /// from executing the instruction immediately following it.  Examples include
237  /// unconditional branches and return instructions.
238  bool isBarrier(MachineOpCode Opcode) const {
239    return get(Opcode).Flags & M_BARRIER_FLAG;
240  }
241
242  bool isCall(MachineOpCode Opcode) const {
243    return get(Opcode).Flags & M_CALL_FLAG;
244  }
245  bool isLoad(MachineOpCode Opcode) const {
246    return get(Opcode).Flags & M_LOAD_FLAG;
247  }
248  bool isStore(MachineOpCode Opcode) const {
249    return get(Opcode).Flags & M_STORE_FLAG;
250  }
251
252  /// hasDelaySlot - Returns true if the specified instruction has a delay slot
253  /// which must be filled by the code generator.
254  bool hasDelaySlot(MachineOpCode Opcode) const {
255    return get(Opcode).Flags & M_DELAY_SLOT_FLAG;
256  }
257
258  /// usesCustomDAGSchedInsertionHook - Return true if this instruction requires
259  /// custom insertion support when the DAG scheduler is inserting it into a
260  /// machine basic block.
261  bool usesCustomDAGSchedInsertionHook(MachineOpCode Opcode) const {
262    return get(Opcode).Flags & M_USES_CUSTOM_DAG_SCHED_INSERTION;
263  }
264
265  bool hasVariableOperands(MachineOpCode Opcode) const {
266    return get(Opcode).Flags & M_VARIABLE_OPS;
267  }
268
269  bool isPredicable(MachineOpCode Opcode) const {
270    return get(Opcode).Flags & M_PREDICABLE;
271  }
272
273  bool isNotDuplicable(MachineOpCode Opcode) const {
274    return get(Opcode).Flags & M_NOT_DUPLICABLE;
275  }
276
277  bool hasOptionalDef(MachineOpCode Opcode) const {
278    return get(Opcode).Flags & M_HAS_OPTIONAL_DEF;
279  }
280
281  /// isTriviallyReMaterializable - Return true if the instruction is trivially
282  /// rematerializable, meaning it has no side effects and requires no operands
283  /// that aren't always available.
284  bool isTriviallyReMaterializable(MachineInstr *MI) const {
285    return (MI->getInstrDescriptor()->Flags & M_REMATERIALIZIBLE) &&
286           isReallyTriviallyReMaterializable(MI);
287  }
288
289protected:
290  /// isReallyTriviallyReMaterializable - For instructions with opcodes for
291  /// which the M_REMATERIALIZABLE flag is set, this function tests whether the
292  /// instruction itself is actually trivially rematerializable, considering
293  /// its operands.  This is used for targets that have instructions that are
294  /// only trivially rematerializable for specific uses.  This predicate must
295  /// return false if the instruction has any side effects other than
296  /// producing a value, or if it requres any address registers that are not
297  /// always available.
298  virtual bool isReallyTriviallyReMaterializable(MachineInstr *MI) const {
299    return true;
300  }
301
302public:
303  /// getOperandConstraint - Returns the value of the specific constraint if
304  /// it is set. Returns -1 if it is not set.
305  int getOperandConstraint(MachineOpCode Opcode, unsigned OpNum,
306                           TOI::OperandConstraint Constraint) const {
307    return get(Opcode).getOperandConstraint(OpNum, Constraint);
308  }
309
310  /// Return true if the instruction is a register to register move
311  /// and leave the source and dest operands in the passed parameters.
312  virtual bool isMoveInstr(const MachineInstr& MI,
313                           unsigned& sourceReg,
314                           unsigned& destReg) const {
315    return false;
316  }
317
318  /// isLoadFromStackSlot - If the specified machine instruction is a direct
319  /// load from a stack slot, return the virtual or physical register number of
320  /// the destination along with the FrameIndex of the loaded stack slot.  If
321  /// not, return 0.  This predicate must return 0 if the instruction has
322  /// any side effects other than loading from the stack slot.
323  virtual unsigned isLoadFromStackSlot(MachineInstr *MI, int &FrameIndex) const{
324    return 0;
325  }
326
327  /// isStoreToStackSlot - If the specified machine instruction is a direct
328  /// store to a stack slot, return the virtual or physical register number of
329  /// the source reg along with the FrameIndex of the loaded stack slot.  If
330  /// not, return 0.  This predicate must return 0 if the instruction has
331  /// any side effects other than storing to the stack slot.
332  virtual unsigned isStoreToStackSlot(MachineInstr *MI, int &FrameIndex) const {
333    return 0;
334  }
335
336  /// convertToThreeAddress - This method must be implemented by targets that
337  /// set the M_CONVERTIBLE_TO_3_ADDR flag.  When this flag is set, the target
338  /// may be able to convert a two-address instruction into one or more true
339  /// three-address instructions on demand.  This allows the X86 target (for
340  /// example) to convert ADD and SHL instructions into LEA instructions if they
341  /// would require register copies due to two-addressness.
342  ///
343  /// This method returns a null pointer if the transformation cannot be
344  /// performed, otherwise it returns the last new instruction.
345  ///
346  virtual MachineInstr *
347  convertToThreeAddress(MachineFunction::iterator &MFI,
348                   MachineBasicBlock::iterator &MBBI, LiveVariables &LV) const {
349    return 0;
350  }
351
352  /// commuteInstruction - If a target has any instructions that are commutable,
353  /// but require converting to a different instruction or making non-trivial
354  /// changes to commute them, this method can overloaded to do this.  The
355  /// default implementation of this method simply swaps the first two operands
356  /// of MI and returns it.
357  ///
358  /// If a target wants to make more aggressive changes, they can construct and
359  /// return a new machine instruction.  If an instruction cannot commute, it
360  /// can also return null.
361  ///
362  virtual MachineInstr *commuteInstruction(MachineInstr *MI) const;
363
364  /// AnalyzeBranch - Analyze the branching code at the end of MBB, returning
365  /// true if it cannot be understood (e.g. it's a switch dispatch or isn't
366  /// implemented for a target).  Upon success, this returns false and returns
367  /// with the following information in various cases:
368  ///
369  /// 1. If this block ends with no branches (it just falls through to its succ)
370  ///    just return false, leaving TBB/FBB null.
371  /// 2. If this block ends with only an unconditional branch, it sets TBB to be
372  ///    the destination block.
373  /// 3. If this block ends with an conditional branch and it falls through to
374  ///    an successor block, it sets TBB to be the branch destination block and a
375  ///    list of operands that evaluate the condition. These
376  ///    operands can be passed to other TargetInstrInfo methods to create new
377  ///    branches.
378  /// 4. If this block ends with an conditional branch and an unconditional
379  ///    block, it returns the 'true' destination in TBB, the 'false' destination
380  ///    in FBB, and a list of operands that evaluate the condition. These
381  ///    operands can be passed to other TargetInstrInfo methods to create new
382  ///    branches.
383  ///
384  /// Note that RemoveBranch and InsertBranch must be implemented to support
385  /// cases where this method returns success.
386  ///
387  virtual bool AnalyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB,
388                             MachineBasicBlock *&FBB,
389                             std::vector<MachineOperand> &Cond) const {
390    return true;
391  }
392
393  /// RemoveBranch - Remove the branching code at the end of the specific MBB.
394  /// this is only invoked in cases where AnalyzeBranch returns success. It
395  /// returns the number of instructions that were removed.
396  virtual unsigned RemoveBranch(MachineBasicBlock &MBB) const {
397    assert(0 && "Target didn't implement TargetInstrInfo::RemoveBranch!");
398    return 0;
399  }
400
401  /// InsertBranch - Insert a branch into the end of the specified
402  /// MachineBasicBlock.  This operands to this method are the same as those
403  /// returned by AnalyzeBranch.  This is invoked in cases where AnalyzeBranch
404  /// returns success and when an unconditional branch (TBB is non-null, FBB is
405  /// null, Cond is empty) needs to be inserted. It returns the number of
406  /// instructions inserted.
407  virtual unsigned InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB,
408                            MachineBasicBlock *FBB,
409                            const std::vector<MachineOperand> &Cond) const {
410    assert(0 && "Target didn't implement TargetInstrInfo::InsertBranch!");
411    return 0;
412  }
413
414  /// BlockHasNoFallThrough - Return true if the specified block does not
415  /// fall-through into its successor block.  This is primarily used when a
416  /// branch is unanalyzable.  It is useful for things like unconditional
417  /// indirect branches (jump tables).
418  virtual bool BlockHasNoFallThrough(MachineBasicBlock &MBB) const {
419    return false;
420  }
421
422  /// ReverseBranchCondition - Reverses the branch condition of the specified
423  /// condition list, returning false on success and true if it cannot be
424  /// reversed.
425  virtual bool ReverseBranchCondition(std::vector<MachineOperand> &Cond) const {
426    return true;
427  }
428
429  /// insertNoop - Insert a noop into the instruction stream at the specified
430  /// point.
431  virtual void insertNoop(MachineBasicBlock &MBB,
432                          MachineBasicBlock::iterator MI) const {
433    assert(0 && "Target didn't implement insertNoop!");
434    abort();
435  }
436
437  /// isPredicated - Returns true if the instruction is already predicated.
438  ///
439  virtual bool isPredicated(const MachineInstr *MI) const {
440    return false;
441  }
442
443  /// isUnpredicatedTerminator - Returns true if the instruction is a
444  /// terminator instruction that has not been predicated.
445  virtual bool isUnpredicatedTerminator(const MachineInstr *MI) const;
446
447  /// PredicateInstruction - Convert the instruction into a predicated
448  /// instruction. It returns true if the operation was successful.
449  virtual
450  bool PredicateInstruction(MachineInstr *MI,
451                            const std::vector<MachineOperand> &Pred) const;
452
453  /// SubsumesPredicate - Returns true if the first specified predicate
454  /// subsumes the second, e.g. GE subsumes GT.
455  virtual
456  bool SubsumesPredicate(const std::vector<MachineOperand> &Pred1,
457                         const std::vector<MachineOperand> &Pred2) const {
458    return false;
459  }
460
461  /// DefinesPredicate - If the specified instruction defines any predicate
462  /// or condition code register(s) used for predication, returns true as well
463  /// as the definition predicate(s) by reference.
464  virtual bool DefinesPredicate(MachineInstr *MI,
465                                std::vector<MachineOperand> &Pred) const {
466    return false;
467  }
468
469  /// getPointerRegClass - Returns a TargetRegisterClass used for pointer
470  /// values.
471  virtual const TargetRegisterClass *getPointerRegClass() const {
472    assert(0 && "Target didn't implement getPointerRegClass!");
473    abort();
474    return 0; // Must return a value in order to compile with VS 2005
475  }
476};
477
478} // End llvm namespace
479
480#endif
481