TargetInstrInfo.h revision 13cea0bcefa892b6b73c39fd4d30d8bb42392e1f
1//===-- llvm/Target/TargetInstrInfo.h - Instruction Info --------*- C++ -*-===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This file describes the target machine instructions to the code generator. 11// 12//===----------------------------------------------------------------------===// 13 14#ifndef LLVM_TARGET_TARGETINSTRINFO_H 15#define LLVM_TARGET_TARGETINSTRINFO_H 16 17#include "llvm/CodeGen/MachineBasicBlock.h" 18#include "llvm/CodeGen/MachineFunction.h" 19#include "llvm/Support/DataTypes.h" 20#include <vector> 21#include <cassert> 22 23namespace llvm { 24 25class MachineInstr; 26class TargetMachine; 27class TargetRegisterClass; 28class LiveVariables; 29class CalleeSavedInfo; 30class SDNode; 31class SelectionDAG; 32 33template<class T> class SmallVectorImpl; 34 35//===----------------------------------------------------------------------===// 36// Machine Operand Flags and Description 37//===----------------------------------------------------------------------===// 38 39namespace TOI { 40 // Operand constraints: only "tied_to" for now. 41 enum OperandConstraint { 42 TIED_TO = 0 // Must be allocated the same register as. 43 }; 44 45 /// OperandFlags - These are flags set on operands, but should be considered 46 /// private, all access should go through the TargetOperandInfo accessors. 47 /// See the accessors for a description of what these are. 48 enum OperandFlags { 49 LookupPtrRegClass = 1 << 0, 50 Predicate = 1 << 1, 51 OptionalDef = 1 << 2 52 }; 53} 54 55/// TargetOperandInfo - This holds information about one operand of a machine 56/// instruction, indicating the register class for register operands, etc. 57/// 58class TargetOperandInfo { 59public: 60 /// RegClass - This specifies the register class enumeration of the operand 61 /// if the operand is a register. If not, this contains 0. 62 unsigned short RegClass; 63 unsigned short Flags; 64 /// Lower 16 bits are used to specify which constraints are set. The higher 16 65 /// bits are used to specify the value of constraints (4 bits each). 66 unsigned int Constraints; 67 /// Currently no other information. 68 69 /// isLookupPtrRegClass - Set if this operand is a pointer value and it 70 /// requires a callback to look up its register class. 71 bool isLookupPtrRegClass() const { return Flags & TOI::LookupPtrRegClass; } 72 73 /// isPredicate - Set if this is one of the operands that made up of 74 /// the predicate operand that controls an M_PREDICATED instruction. 75 bool isPredicate() const { return Flags & TOI::Predicate; } 76 77 /// isOptionalDef - Set if this operand is a optional def. 78 /// 79 bool isOptionalDef() const { return Flags & TOI::OptionalDef; } 80}; 81 82 83//===----------------------------------------------------------------------===// 84// Machine Instruction Flags and Description 85//===----------------------------------------------------------------------===// 86 87const unsigned M_BRANCH_FLAG = 1 << 0; 88const unsigned M_CALL_FLAG = 1 << 1; 89const unsigned M_RET_FLAG = 1 << 2; 90const unsigned M_BARRIER_FLAG = 1 << 3; 91const unsigned M_DELAY_SLOT_FLAG = 1 << 4; 92 93/// M_SIMPLE_LOAD_FLAG - This flag is set for instructions that are simple loads 94/// from memory. This should only be set on instructions that load a value from 95/// memory and return it in their only virtual register definition. 96const unsigned M_SIMPLE_LOAD_FLAG = 1 << 5; 97 98/// M_MAY_STORE_FLAG - This flag is set to any instruction that could possibly 99/// modify memory. Instructions with this flag set are not necessarily simple 100/// store instructions, they may store a modified value based on their operands, 101/// or may not actually modify anything, for example. 102const unsigned M_MAY_STORE_FLAG = 1 << 6; 103 104const unsigned M_INDIRECT_FLAG = 1 << 7; 105const unsigned M_IMPLICIT_DEF_FLAG = 1 << 8; 106 107// M_CONVERTIBLE_TO_3_ADDR - This is a 2-address instruction which can be 108// changed into a 3-address instruction if the first two operands cannot be 109// assigned to the same register. The target must implement the 110// TargetInstrInfo::convertToThreeAddress method for this instruction. 111const unsigned M_CONVERTIBLE_TO_3_ADDR = 1 << 9; 112 113// This M_COMMUTABLE - is a 2- or 3-address instruction (of the form X = op Y, 114// Z), which produces the same result if Y and Z are exchanged. 115const unsigned M_COMMUTABLE = 1 << 10; 116 117const unsigned M_TERMINATOR_FLAG = 1 << 11; 118 119// M_USES_CUSTOM_DAG_SCHED_INSERTION - Set if this instruction requires custom 120// insertion support when the DAG scheduler is inserting it into a machine basic 121// block. 122const unsigned M_USES_CUSTOM_DAG_SCHED_INSERTION = 1 << 12; 123 124const unsigned M_VARIADIC = 1 << 13; 125 126// M_PREDICABLE - Set if this instruction has a predicate operand that 127// controls execution. It may be set to 'always'. 128const unsigned M_PREDICABLE = 1 << 14; 129 130// M_REMATERIALIZIBLE - Set if this instruction can be trivally re-materialized 131// at any time, e.g. constant generation, load from constant pool. 132const unsigned M_REMATERIALIZIBLE = 1 << 15; 133 134// M_NOT_DUPLICABLE - Set if this instruction cannot be safely duplicated. 135// (e.g. instructions with unique labels attached). 136const unsigned M_NOT_DUPLICABLE = 1 << 16; 137 138const unsigned M_HAS_OPTIONAL_DEF = 1 << 17; 139 140// M_NEVER_HAS_SIDE_EFFECTS - Set if this instruction has no side effects that 141// are not captured by any operands of the instruction or other flags, and when 142// *all* instances of the instruction of that opcode have no side effects. 143// 144// Note: This and M_MAY_HAVE_SIDE_EFFECTS are mutually exclusive. You can't set 145// both! If neither flag is set, then the instruction *always* has side effects. 146const unsigned M_NEVER_HAS_SIDE_EFFECTS = 1 << 18; 147 148// M_MAY_HAVE_SIDE_EFFECTS - Set if some instances of this instruction can have 149// side effects. The virtual method "isReallySideEffectFree" is called to 150// determine this. Load instructions are an example of where this is useful. In 151// general, loads always have side effects. However, loads from constant pools 152// don't. We let the specific back end make this determination. 153// 154// Note: This and M_NEVER_HAS_SIDE_EFFECTS are mutually exclusive. You can't set 155// both! If neither flag is set, then the instruction *always* has side effects. 156const unsigned M_MAY_HAVE_SIDE_EFFECTS = 1 << 19; 157 158 159 160class TargetInstrDescriptor { 161public: 162 unsigned short Opcode; // The opcode number. 163 unsigned short NumOperands; // Num of args (may be more if variable_ops) 164 unsigned short NumDefs; // Num of args that are definitions. 165 unsigned short SchedClass; // enum identifying instr sched class 166 const char * Name; // Name of the instruction record in td file. 167 unsigned Flags; // flags identifying machine instr class 168 unsigned TSFlags; // Target Specific Flag values 169 const unsigned *ImplicitUses; // Registers implicitly read by this instr 170 const unsigned *ImplicitDefs; // Registers implicitly defined by this instr 171 const TargetOperandInfo *OpInfo; // 'numOperands' entries about operands. 172 173 /// getOperandConstraint - Returns the value of the specific constraint if 174 /// it is set. Returns -1 if it is not set. 175 int getOperandConstraint(unsigned OpNum, 176 TOI::OperandConstraint Constraint) const { 177 assert((OpNum < NumOperands || isVariadic()) && 178 "Invalid operand # of TargetInstrInfo"); 179 if (OpNum < NumOperands && 180 (OpInfo[OpNum].Constraints & (1 << Constraint))) { 181 unsigned Pos = 16 + Constraint * 4; 182 return (int)(OpInfo[OpNum].Constraints >> Pos) & 0xf; 183 } 184 return -1; 185 } 186 187 /// findTiedToSrcOperand - Returns the operand that is tied to the specified 188 /// dest operand. Returns -1 if there isn't one. 189 int findTiedToSrcOperand(unsigned OpNum) const; 190 191 /// getName - Return the name of the record in the .td file for this 192 /// instruction, for example "ADD8ri". 193 const char *getName() const { 194 return Name; 195 } 196 197 /// getNumOperands - Return the number of declared MachineOperands for this 198 /// MachineInstruction. Note that variadic (isVariadic() returns true) 199 /// instructions may have additional operands at the end of the list, and note 200 /// that the machine instruction may include implicit register def/uses as 201 /// well. 202 unsigned getNumOperands() const { 203 return NumOperands; 204 } 205 206 /// getNumDefs - Return the number of MachineOperands that are register 207 /// definitions. Register definitions always occur at the start of the 208 /// machine operand list. This is the number of "outs" in the .td file. 209 unsigned getNumDefs() const { 210 return NumDefs; 211 } 212 213 /// isVariadic - Return true if this instruction can have a variable number of 214 /// operands. In this case, the variable operands will be after the normal 215 /// operands but before the implicit definitions and uses (if any are 216 /// present). 217 bool isVariadic() const { 218 return Flags & M_VARIADIC; 219 } 220 221 /// hasOptionalDef - Set if this instruction has an optional definition, e.g. 222 /// ARM instructions which can set condition code if 's' bit is set. 223 bool hasOptionalDef() const { 224 return Flags & M_HAS_OPTIONAL_DEF; 225 } 226 227 /// getImplicitUses - Return a list of machine operands that are potentially 228 /// read by any instance of this machine instruction. For example, on X86, 229 /// the "adc" instruction adds two register operands and adds the carry bit in 230 /// from the flags register. In this case, the instruction is marked as 231 /// implicitly reading the flags. Likewise, the variable shift instruction on 232 /// X86 is marked as implicitly reading the 'CL' register, which it always 233 /// does. 234 /// 235 /// This method returns null if the instruction has no implicit uses. 236 const unsigned *getImplicitUses() const { 237 return ImplicitUses; 238 } 239 240 /// getImplicitDefs - Return a list of machine operands that are potentially 241 /// written by any instance of this machine instruction. For example, on X86, 242 /// many instructions implicitly set the flags register. In this case, they 243 /// are marked as setting the FLAGS. Likewise, many instructions always 244 /// deposit their result in a physical register. For example, the X86 divide 245 /// instruction always deposits the quotient and remainder in the EAX/EDX 246 /// registers. For that instruction, this will return a list containing the 247 /// EAX/EDX/EFLAGS registers. 248 /// 249 /// This method returns null if the instruction has no implicit uses. 250 const unsigned *getImplicitDefs() const { 251 return ImplicitDefs; 252 } 253 254 bool isReturn() const { 255 return Flags & M_RET_FLAG; 256 } 257 258 bool isCall() const { 259 return Flags & M_CALL_FLAG; 260 } 261 262 /// isImplicitDef - Return true if this is an "IMPLICIT_DEF" instruction, 263 /// which defines a register to an unspecified value. These basically 264 /// correspond to x = undef. 265 bool isImplicitDef() const { 266 return Flags & M_IMPLICIT_DEF_FLAG; 267 } 268 269 /// isBarrier - Returns true if the specified instruction stops control flow 270 /// from executing the instruction immediately following it. Examples include 271 /// unconditional branches and return instructions. 272 bool isBarrier() const { 273 return Flags & M_BARRIER_FLAG; 274 } 275 276 /// isTerminator - Returns true if this instruction part of the terminator for 277 /// a basic block. Typically this is things like return and branch 278 /// instructions. 279 /// 280 /// Various passes use this to insert code into the bottom of a basic block, 281 /// but before control flow occurs. 282 bool isTerminator() const { 283 return Flags & M_TERMINATOR_FLAG; 284 } 285 286 /// isBranch - Returns true if this is a conditional, unconditional, or 287 /// indirect branch. Predicates below can be used to discriminate between 288 /// these cases, and the TargetInstrInfo::AnalyzeBranch method can be used to 289 /// get more information. 290 bool isBranch() const { 291 return Flags & M_BRANCH_FLAG; 292 } 293 294 /// isIndirectBranch - Return true if this is an indirect branch, such as a 295 /// branch through a register. 296 bool isIndirectBranch() const { 297 return Flags & M_INDIRECT_FLAG; 298 } 299 300 /// isConditionalBranch - Return true if this is a branch which may fall 301 /// through to the next instruction or may transfer control flow to some other 302 /// block. The TargetInstrInfo::AnalyzeBranch method can be used to get more 303 /// information about this branch. 304 bool isConditionalBranch() const { 305 return isBranch() & !isBarrier() & !isIndirectBranch(); 306 } 307 308 /// isUnconditionalBranch - Return true if this is a branch which always 309 /// transfers control flow to some other block. The 310 /// TargetInstrInfo::AnalyzeBranch method can be used to get more information 311 /// about this branch. 312 bool isUnconditionalBranch() const { 313 return isBranch() & isBarrier() & !isIndirectBranch(); 314 } 315 316 bool isPredicable() const { 317 return Flags & M_PREDICABLE; 318 } 319 320 bool isNotDuplicable() const { 321 return Flags & M_NOT_DUPLICABLE; 322 } 323 324 bool isCommutableInstr() const { 325 return Flags & M_COMMUTABLE; 326 } 327 328 /// hasDelaySlot - Returns true if the specified instruction has a delay slot 329 /// which must be filled by the code generator. 330 bool hasDelaySlot() const { 331 return Flags & M_DELAY_SLOT_FLAG; 332 } 333 334 /// usesCustomDAGSchedInsertionHook - Return true if this instruction requires 335 /// custom insertion support when the DAG scheduler is inserting it into a 336 /// machine basic block. 337 bool usesCustomDAGSchedInsertionHook() const { 338 return Flags & M_USES_CUSTOM_DAG_SCHED_INSERTION; 339 } 340 341 /// isSimpleLoad - Return true for instructions that are simple loads from 342 /// memory. This should only be set on instructions that load a value from 343 /// memory and return it in their only virtual register definition. 344 /// Instructions that return a value loaded from memory and then modified in 345 /// some way should not return true for this. 346 bool isSimpleLoad() const { 347 return Flags & M_SIMPLE_LOAD_FLAG; 348 } 349 350 /// mayStore - Return true if this instruction could possibly modify memory. 351 /// Instructions with this flag set are not necessarily simple store 352 /// instructions, they may store a modified value based on their operands, or 353 /// may not actually modify anything, for example. 354 bool mayStore() const { 355 return Flags & M_MAY_STORE_FLAG; 356 } 357 358 unsigned getSchedClass() const { 359 return SchedClass; 360 } 361}; 362 363 364//--------------------------------------------------------------------------- 365/// 366/// TargetInstrInfo - Interface to description of machine instructions 367/// 368class TargetInstrInfo { 369 const TargetInstrDescriptor* desc; // raw array to allow static init'n 370 unsigned NumOpcodes; // number of entries in the desc array 371 unsigned numRealOpCodes; // number of non-dummy op codes 372 373 TargetInstrInfo(const TargetInstrInfo &); // DO NOT IMPLEMENT 374 void operator=(const TargetInstrInfo &); // DO NOT IMPLEMENT 375public: 376 TargetInstrInfo(const TargetInstrDescriptor *desc, unsigned NumOpcodes); 377 virtual ~TargetInstrInfo(); 378 379 // Invariant opcodes: All instruction sets have these as their low opcodes. 380 enum { 381 PHI = 0, 382 INLINEASM = 1, 383 LABEL = 2, 384 EXTRACT_SUBREG = 3, 385 INSERT_SUBREG = 4 386 }; 387 388 unsigned getNumOpcodes() const { return NumOpcodes; } 389 390 /// get - Return the machine instruction descriptor that corresponds to the 391 /// specified instruction opcode. 392 /// 393 const TargetInstrDescriptor& get(unsigned Opcode) const { 394 assert(Opcode < NumOpcodes); 395 return desc[Opcode]; 396 } 397 398 /// isTriviallyReMaterializable - Return true if the instruction is trivially 399 /// rematerializable, meaning it has no side effects and requires no operands 400 /// that aren't always available. 401 bool isTriviallyReMaterializable(MachineInstr *MI) const { 402 return (MI->getDesc()->Flags & M_REMATERIALIZIBLE) && 403 isReallyTriviallyReMaterializable(MI); 404 } 405 406 /// hasUnmodelledSideEffects - Returns true if the instruction has side 407 /// effects that are not captured by any operands of the instruction or other 408 /// flags. 409 bool hasUnmodelledSideEffects(MachineInstr *MI) const { 410 const TargetInstrDescriptor *TID = MI->getDesc(); 411 if (TID->Flags & M_NEVER_HAS_SIDE_EFFECTS) return false; 412 if (!(TID->Flags & M_MAY_HAVE_SIDE_EFFECTS)) return true; 413 return !isReallySideEffectFree(MI); // May have side effects 414 } 415protected: 416 /// isReallyTriviallyReMaterializable - For instructions with opcodes for 417 /// which the M_REMATERIALIZABLE flag is set, this function tests whether the 418 /// instruction itself is actually trivially rematerializable, considering 419 /// its operands. This is used for targets that have instructions that are 420 /// only trivially rematerializable for specific uses. This predicate must 421 /// return false if the instruction has any side effects other than 422 /// producing a value, or if it requres any address registers that are not 423 /// always available. 424 virtual bool isReallyTriviallyReMaterializable(MachineInstr *MI) const { 425 return true; 426 } 427 428 /// isReallySideEffectFree - If the M_MAY_HAVE_SIDE_EFFECTS flag is set, this 429 /// method is called to determine if the specific instance of this 430 /// instruction has side effects. This is useful in cases of instructions, 431 /// like loads, which generally always have side effects. A load from a 432 /// constant pool doesn't have side effects, though. So we need to 433 /// differentiate it from the general case. 434 virtual bool isReallySideEffectFree(MachineInstr *MI) const { 435 return false; 436 } 437public: 438 /// getOperandConstraint - Returns the value of the specific constraint if 439 /// it is set. Returns -1 if it is not set. 440 int getOperandConstraint(unsigned Opcode, unsigned OpNum, 441 TOI::OperandConstraint Constraint) const { 442 return get(Opcode).getOperandConstraint(OpNum, Constraint); 443 } 444 445 /// Return true if the instruction is a register to register move 446 /// and leave the source and dest operands in the passed parameters. 447 virtual bool isMoveInstr(const MachineInstr& MI, 448 unsigned& sourceReg, 449 unsigned& destReg) const { 450 return false; 451 } 452 453 /// isLoadFromStackSlot - If the specified machine instruction is a direct 454 /// load from a stack slot, return the virtual or physical register number of 455 /// the destination along with the FrameIndex of the loaded stack slot. If 456 /// not, return 0. This predicate must return 0 if the instruction has 457 /// any side effects other than loading from the stack slot. 458 virtual unsigned isLoadFromStackSlot(MachineInstr *MI, int &FrameIndex) const{ 459 return 0; 460 } 461 462 /// isStoreToStackSlot - If the specified machine instruction is a direct 463 /// store to a stack slot, return the virtual or physical register number of 464 /// the source reg along with the FrameIndex of the loaded stack slot. If 465 /// not, return 0. This predicate must return 0 if the instruction has 466 /// any side effects other than storing to the stack slot. 467 virtual unsigned isStoreToStackSlot(MachineInstr *MI, int &FrameIndex) const { 468 return 0; 469 } 470 471 /// convertToThreeAddress - This method must be implemented by targets that 472 /// set the M_CONVERTIBLE_TO_3_ADDR flag. When this flag is set, the target 473 /// may be able to convert a two-address instruction into one or more true 474 /// three-address instructions on demand. This allows the X86 target (for 475 /// example) to convert ADD and SHL instructions into LEA instructions if they 476 /// would require register copies due to two-addressness. 477 /// 478 /// This method returns a null pointer if the transformation cannot be 479 /// performed, otherwise it returns the last new instruction. 480 /// 481 virtual MachineInstr * 482 convertToThreeAddress(MachineFunction::iterator &MFI, 483 MachineBasicBlock::iterator &MBBI, LiveVariables &LV) const { 484 return 0; 485 } 486 487 /// commuteInstruction - If a target has any instructions that are commutable, 488 /// but require converting to a different instruction or making non-trivial 489 /// changes to commute them, this method can overloaded to do this. The 490 /// default implementation of this method simply swaps the first two operands 491 /// of MI and returns it. 492 /// 493 /// If a target wants to make more aggressive changes, they can construct and 494 /// return a new machine instruction. If an instruction cannot commute, it 495 /// can also return null. 496 /// 497 virtual MachineInstr *commuteInstruction(MachineInstr *MI) const = 0; 498 499 /// AnalyzeBranch - Analyze the branching code at the end of MBB, returning 500 /// true if it cannot be understood (e.g. it's a switch dispatch or isn't 501 /// implemented for a target). Upon success, this returns false and returns 502 /// with the following information in various cases: 503 /// 504 /// 1. If this block ends with no branches (it just falls through to its succ) 505 /// just return false, leaving TBB/FBB null. 506 /// 2. If this block ends with only an unconditional branch, it sets TBB to be 507 /// the destination block. 508 /// 3. If this block ends with an conditional branch and it falls through to 509 /// an successor block, it sets TBB to be the branch destination block and a 510 /// list of operands that evaluate the condition. These 511 /// operands can be passed to other TargetInstrInfo methods to create new 512 /// branches. 513 /// 4. If this block ends with an conditional branch and an unconditional 514 /// block, it returns the 'true' destination in TBB, the 'false' destination 515 /// in FBB, and a list of operands that evaluate the condition. These 516 /// operands can be passed to other TargetInstrInfo methods to create new 517 /// branches. 518 /// 519 /// Note that RemoveBranch and InsertBranch must be implemented to support 520 /// cases where this method returns success. 521 /// 522 virtual bool AnalyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB, 523 MachineBasicBlock *&FBB, 524 std::vector<MachineOperand> &Cond) const { 525 return true; 526 } 527 528 /// RemoveBranch - Remove the branching code at the end of the specific MBB. 529 /// this is only invoked in cases where AnalyzeBranch returns success. It 530 /// returns the number of instructions that were removed. 531 virtual unsigned RemoveBranch(MachineBasicBlock &MBB) const { 532 assert(0 && "Target didn't implement TargetInstrInfo::RemoveBranch!"); 533 return 0; 534 } 535 536 /// InsertBranch - Insert a branch into the end of the specified 537 /// MachineBasicBlock. This operands to this method are the same as those 538 /// returned by AnalyzeBranch. This is invoked in cases where AnalyzeBranch 539 /// returns success and when an unconditional branch (TBB is non-null, FBB is 540 /// null, Cond is empty) needs to be inserted. It returns the number of 541 /// instructions inserted. 542 virtual unsigned InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB, 543 MachineBasicBlock *FBB, 544 const std::vector<MachineOperand> &Cond) const { 545 assert(0 && "Target didn't implement TargetInstrInfo::InsertBranch!"); 546 return 0; 547 } 548 549 /// copyRegToReg - Add a copy between a pair of registers 550 virtual void copyRegToReg(MachineBasicBlock &MBB, 551 MachineBasicBlock::iterator MI, 552 unsigned DestReg, unsigned SrcReg, 553 const TargetRegisterClass *DestRC, 554 const TargetRegisterClass *SrcRC) const { 555 assert(0 && "Target didn't implement TargetInstrInfo::copyRegToReg!"); 556 } 557 558 virtual void storeRegToStackSlot(MachineBasicBlock &MBB, 559 MachineBasicBlock::iterator MI, 560 unsigned SrcReg, bool isKill, int FrameIndex, 561 const TargetRegisterClass *RC) const { 562 assert(0 && "Target didn't implement TargetInstrInfo::storeRegToStackSlot!"); 563 } 564 565 virtual void storeRegToAddr(MachineFunction &MF, unsigned SrcReg, bool isKill, 566 SmallVectorImpl<MachineOperand> &Addr, 567 const TargetRegisterClass *RC, 568 SmallVectorImpl<MachineInstr*> &NewMIs) const { 569 assert(0 && "Target didn't implement TargetInstrInfo::storeRegToAddr!"); 570 } 571 572 virtual void loadRegFromStackSlot(MachineBasicBlock &MBB, 573 MachineBasicBlock::iterator MI, 574 unsigned DestReg, int FrameIndex, 575 const TargetRegisterClass *RC) const { 576 assert(0 && "Target didn't implement TargetInstrInfo::loadRegFromStackSlot!"); 577 } 578 579 virtual void loadRegFromAddr(MachineFunction &MF, unsigned DestReg, 580 SmallVectorImpl<MachineOperand> &Addr, 581 const TargetRegisterClass *RC, 582 SmallVectorImpl<MachineInstr*> &NewMIs) const { 583 assert(0 && "Target didn't implement TargetInstrInfo::loadRegFromAddr!"); 584 } 585 586 /// spillCalleeSavedRegisters - Issues instruction(s) to spill all callee 587 /// saved registers and returns true if it isn't possible / profitable to do 588 /// so by issuing a series of store instructions via 589 /// storeRegToStackSlot(). Returns false otherwise. 590 virtual bool spillCalleeSavedRegisters(MachineBasicBlock &MBB, 591 MachineBasicBlock::iterator MI, 592 const std::vector<CalleeSavedInfo> &CSI) const { 593 return false; 594 } 595 596 /// restoreCalleeSavedRegisters - Issues instruction(s) to restore all callee 597 /// saved registers and returns true if it isn't possible / profitable to do 598 /// so by issuing a series of load instructions via loadRegToStackSlot(). 599 /// Returns false otherwise. 600 virtual bool restoreCalleeSavedRegisters(MachineBasicBlock &MBB, 601 MachineBasicBlock::iterator MI, 602 const std::vector<CalleeSavedInfo> &CSI) const { 603 return false; 604 } 605 606 /// foldMemoryOperand - Attempt to fold a load or store of the specified stack 607 /// slot into the specified machine instruction for the specified operand(s). 608 /// If this is possible, a new instruction is returned with the specified 609 /// operand folded, otherwise NULL is returned. The client is responsible for 610 /// removing the old instruction and adding the new one in the instruction 611 /// stream. 612 virtual MachineInstr* foldMemoryOperand(MachineInstr* MI, 613 SmallVectorImpl<unsigned> &Ops, 614 int FrameIndex) const { 615 return 0; 616 } 617 618 /// foldMemoryOperand - Same as the previous version except it allows folding 619 /// of any load and store from / to any address, not just from a specific 620 /// stack slot. 621 virtual MachineInstr* foldMemoryOperand(MachineInstr* MI, 622 SmallVectorImpl<unsigned> &Ops, 623 MachineInstr* LoadMI) const { 624 return 0; 625 } 626 627 /// canFoldMemoryOperand - Returns true if the specified load / store is 628 /// folding is possible. 629 virtual 630 bool canFoldMemoryOperand(MachineInstr *MI, 631 SmallVectorImpl<unsigned> &Ops) const{ 632 return false; 633 } 634 635 /// unfoldMemoryOperand - Separate a single instruction which folded a load or 636 /// a store or a load and a store into two or more instruction. If this is 637 /// possible, returns true as well as the new instructions by reference. 638 virtual bool unfoldMemoryOperand(MachineFunction &MF, MachineInstr *MI, 639 unsigned Reg, bool UnfoldLoad, bool UnfoldStore, 640 SmallVectorImpl<MachineInstr*> &NewMIs) const{ 641 return false; 642 } 643 644 virtual bool unfoldMemoryOperand(SelectionDAG &DAG, SDNode *N, 645 SmallVectorImpl<SDNode*> &NewNodes) const { 646 return false; 647 } 648 649 /// getOpcodeAfterMemoryUnfold - Returns the opcode of the would be new 650 /// instruction after load / store are unfolded from an instruction of the 651 /// specified opcode. It returns zero if the specified unfolding is not 652 /// possible. 653 virtual unsigned getOpcodeAfterMemoryUnfold(unsigned Opc, 654 bool UnfoldLoad, bool UnfoldStore) const { 655 return 0; 656 } 657 658 /// BlockHasNoFallThrough - Return true if the specified block does not 659 /// fall-through into its successor block. This is primarily used when a 660 /// branch is unanalyzable. It is useful for things like unconditional 661 /// indirect branches (jump tables). 662 virtual bool BlockHasNoFallThrough(MachineBasicBlock &MBB) const { 663 return false; 664 } 665 666 /// ReverseBranchCondition - Reverses the branch condition of the specified 667 /// condition list, returning false on success and true if it cannot be 668 /// reversed. 669 virtual bool ReverseBranchCondition(std::vector<MachineOperand> &Cond) const { 670 return true; 671 } 672 673 /// insertNoop - Insert a noop into the instruction stream at the specified 674 /// point. 675 virtual void insertNoop(MachineBasicBlock &MBB, 676 MachineBasicBlock::iterator MI) const { 677 assert(0 && "Target didn't implement insertNoop!"); 678 abort(); 679 } 680 681 /// isPredicated - Returns true if the instruction is already predicated. 682 /// 683 virtual bool isPredicated(const MachineInstr *MI) const { 684 return false; 685 } 686 687 /// isUnpredicatedTerminator - Returns true if the instruction is a 688 /// terminator instruction that has not been predicated. 689 virtual bool isUnpredicatedTerminator(const MachineInstr *MI) const; 690 691 /// PredicateInstruction - Convert the instruction into a predicated 692 /// instruction. It returns true if the operation was successful. 693 virtual 694 bool PredicateInstruction(MachineInstr *MI, 695 const std::vector<MachineOperand> &Pred) const = 0; 696 697 /// SubsumesPredicate - Returns true if the first specified predicate 698 /// subsumes the second, e.g. GE subsumes GT. 699 virtual 700 bool SubsumesPredicate(const std::vector<MachineOperand> &Pred1, 701 const std::vector<MachineOperand> &Pred2) const { 702 return false; 703 } 704 705 /// DefinesPredicate - If the specified instruction defines any predicate 706 /// or condition code register(s) used for predication, returns true as well 707 /// as the definition predicate(s) by reference. 708 virtual bool DefinesPredicate(MachineInstr *MI, 709 std::vector<MachineOperand> &Pred) const { 710 return false; 711 } 712 713 /// getPointerRegClass - Returns a TargetRegisterClass used for pointer 714 /// values. 715 virtual const TargetRegisterClass *getPointerRegClass() const { 716 assert(0 && "Target didn't implement getPointerRegClass!"); 717 abort(); 718 return 0; // Must return a value in order to compile with VS 2005 719 } 720}; 721 722/// TargetInstrInfoImpl - This is the default implementation of 723/// TargetInstrInfo, which just provides a couple of default implementations 724/// for various methods. This separated out because it is implemented in 725/// libcodegen, not in libtarget. 726class TargetInstrInfoImpl : public TargetInstrInfo { 727protected: 728 TargetInstrInfoImpl(const TargetInstrDescriptor *desc, unsigned NumOpcodes) 729 : TargetInstrInfo(desc, NumOpcodes) {} 730public: 731 virtual MachineInstr *commuteInstruction(MachineInstr *MI) const; 732 virtual bool PredicateInstruction(MachineInstr *MI, 733 const std::vector<MachineOperand> &Pred) const; 734 735}; 736 737} // End llvm namespace 738 739#endif 740