TargetInstrInfo.h revision 13d41b9d721f98372b97d2ec119e6c91932ab0ae
1//===-- llvm/Target/TargetInstrInfo.h - Instruction Info --------*- C++ -*-===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file was developed by the LLVM research group and is distributed under 6// the University of Illinois Open Source License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This file describes the target machine instructions to the code generator. 11// 12//===----------------------------------------------------------------------===// 13 14#ifndef LLVM_TARGET_TARGETINSTRINFO_H 15#define LLVM_TARGET_TARGETINSTRINFO_H 16 17#include "llvm/CodeGen/MachineBasicBlock.h" 18#include "llvm/Support/DataTypes.h" 19#include <vector> 20#include <cassert> 21 22namespace llvm { 23 24class MachineInstr; 25class TargetMachine; 26class Value; 27class Type; 28class Instruction; 29class Constant; 30class Function; 31class MachineCodeForInstruction; 32class TargetRegisterClass; 33 34//--------------------------------------------------------------------------- 35// Data types used to define information about a single machine instruction 36//--------------------------------------------------------------------------- 37 38typedef short MachineOpCode; 39typedef unsigned InstrSchedClass; 40 41//--------------------------------------------------------------------------- 42// struct TargetInstrDescriptor: 43// Predefined information about each machine instruction. 44// Designed to initialized statically. 45// 46 47const unsigned M_BRANCH_FLAG = 1 << 0; 48const unsigned M_CALL_FLAG = 1 << 1; 49const unsigned M_RET_FLAG = 1 << 2; 50const unsigned M_BARRIER_FLAG = 1 << 3; 51const unsigned M_DELAY_SLOT_FLAG = 1 << 4; 52const unsigned M_LOAD_FLAG = 1 << 5; 53const unsigned M_STORE_FLAG = 1 << 6; 54 55// M_2_ADDR_FLAG - 3-addr instructions which really work like 2-addr ones. 56const unsigned M_2_ADDR_FLAG = 1 << 7; 57 58// M_CONVERTIBLE_TO_3_ADDR - This is a M_2_ADDR_FLAG instruction which can be 59// changed into a 3-address instruction if the first two operands cannot be 60// assigned to the same register. The target must implement the 61// TargetInstrInfo::convertToThreeAddress method for this instruction. 62const unsigned M_CONVERTIBLE_TO_3_ADDR = 1 << 8; 63 64// This M_COMMUTABLE - is a 2- or 3-address instruction (of the form X = op Y, 65// Z), which produces the same result if Y and Z are exchanged. 66const unsigned M_COMMUTABLE = 1 << 9; 67 68// M_TERMINATOR_FLAG - Is this instruction part of the terminator for a basic 69// block? Typically this is things like return and branch instructions. 70// Various passes use this to insert code into the bottom of a basic block, but 71// before control flow occurs. 72const unsigned M_TERMINATOR_FLAG = 1 << 10; 73 74// M_USES_CUSTOM_DAG_SCHED_INSERTION - Set if this instruction requires custom 75// insertion support when the DAG scheduler is inserting it into a machine basic 76// block. 77const unsigned M_USES_CUSTOM_DAG_SCHED_INSERTION = 1 << 11; 78 79/// TargetOperandInfo - This holds information about one operand of a machine 80/// instruction, indicating the register class for register operands, etc. 81/// 82class TargetOperandInfo { 83public: 84 /// RegClass - This specifies the register class of the operand if the 85 /// operand is a register. If not, this contains null. 86 const TargetRegisterClass *RegClass; 87 88 /// Currently no other information. 89}; 90 91 92class TargetInstrDescriptor { 93public: 94 const char * Name; // Assembly language mnemonic for the opcode. 95 int numOperands; // Number of args; -1 if variable #args 96 InstrSchedClass schedClass; // enum identifying instr sched class 97 unsigned Flags; // flags identifying machine instr class 98 unsigned TSFlags; // Target Specific Flag values 99 const unsigned *ImplicitUses; // Registers implicitly read by this instr 100 const unsigned *ImplicitDefs; // Registers implicitly defined by this instr 101 const TargetOperandInfo *OpInfo; // 'numOperands' entries about operands. 102}; 103 104 105//--------------------------------------------------------------------------- 106/// 107/// TargetInstrInfo - Interface to description of machine instructions 108/// 109class TargetInstrInfo { 110 const TargetInstrDescriptor* desc; // raw array to allow static init'n 111 unsigned NumOpcodes; // number of entries in the desc array 112 unsigned numRealOpCodes; // number of non-dummy op codes 113 114 TargetInstrInfo(const TargetInstrInfo &); // DO NOT IMPLEMENT 115 void operator=(const TargetInstrInfo &); // DO NOT IMPLEMENT 116public: 117 TargetInstrInfo(const TargetInstrDescriptor *desc, unsigned NumOpcodes); 118 virtual ~TargetInstrInfo(); 119 120 // Invariant opcodes: All instruction sets have these as their low opcodes. 121 enum { 122 PHI = 0, 123 INLINEASM = 1 124 }; 125 126 unsigned getNumOpcodes() const { return NumOpcodes; } 127 128 /// get - Return the machine instruction descriptor that corresponds to the 129 /// specified instruction opcode. 130 /// 131 const TargetInstrDescriptor& get(MachineOpCode Opcode) const { 132 assert((unsigned)Opcode < NumOpcodes); 133 return desc[Opcode]; 134 } 135 136 const char *getName(MachineOpCode Opcode) const { 137 return get(Opcode).Name; 138 } 139 140 int getNumOperands(MachineOpCode Opcode) const { 141 return get(Opcode).numOperands; 142 } 143 144 InstrSchedClass getSchedClass(MachineOpCode Opcode) const { 145 return get(Opcode).schedClass; 146 } 147 148 const unsigned *getImplicitUses(MachineOpCode Opcode) const { 149 return get(Opcode).ImplicitUses; 150 } 151 152 const unsigned *getImplicitDefs(MachineOpCode Opcode) const { 153 return get(Opcode).ImplicitDefs; 154 } 155 156 157 // 158 // Query instruction class flags according to the machine-independent 159 // flags listed above. 160 // 161 bool isReturn(MachineOpCode Opcode) const { 162 return get(Opcode).Flags & M_RET_FLAG; 163 } 164 165 bool isTwoAddrInstr(MachineOpCode Opcode) const { 166 return get(Opcode).Flags & M_2_ADDR_FLAG; 167 } 168 bool isCommutableInstr(MachineOpCode Opcode) const { 169 return get(Opcode).Flags & M_COMMUTABLE; 170 } 171 bool isTerminatorInstr(unsigned Opcode) const { 172 return get(Opcode).Flags & M_TERMINATOR_FLAG; 173 } 174 175 bool isBranch(MachineOpCode Opcode) const { 176 return get(Opcode).Flags & M_BRANCH_FLAG; 177 } 178 179 /// isBarrier - Returns true if the specified instruction stops control flow 180 /// from executing the instruction immediately following it. Examples include 181 /// unconditional branches and return instructions. 182 bool isBarrier(MachineOpCode Opcode) const { 183 return get(Opcode).Flags & M_BARRIER_FLAG; 184 } 185 186 bool isCall(MachineOpCode Opcode) const { 187 return get(Opcode).Flags & M_CALL_FLAG; 188 } 189 bool isLoad(MachineOpCode Opcode) const { 190 return get(Opcode).Flags & M_LOAD_FLAG; 191 } 192 bool isStore(MachineOpCode Opcode) const { 193 return get(Opcode).Flags & M_STORE_FLAG; 194 } 195 196 /// usesCustomDAGSchedInsertionHook - Return true if this instruction requires 197 /// custom insertion support when the DAG scheduler is inserting it into a 198 /// machine basic block. 199 bool usesCustomDAGSchedInsertionHook(unsigned Opcode) const { 200 return get(Opcode).Flags & M_USES_CUSTOM_DAG_SCHED_INSERTION; 201 } 202 203 /// Return true if the instruction is a register to register move 204 /// and leave the source and dest operands in the passed parameters. 205 virtual bool isMoveInstr(const MachineInstr& MI, 206 unsigned& sourceReg, 207 unsigned& destReg) const { 208 return false; 209 } 210 211 /// isLoadFromStackSlot - If the specified machine instruction is a direct 212 /// load from a stack slot, return the virtual or physical register number of 213 /// the destination along with the FrameIndex of the loaded stack slot. If 214 /// not, return 0. This predicate must return 0 if the instruction has 215 /// any side effects other than loading from the stack slot. 216 virtual unsigned isLoadFromStackSlot(MachineInstr *MI, int &FrameIndex) const{ 217 return 0; 218 } 219 220 /// isStoreToStackSlot - If the specified machine instruction is a direct 221 /// store to a stack slot, return the virtual or physical register number of 222 /// the source reg along with the FrameIndex of the loaded stack slot. If 223 /// not, return 0. This predicate must return 0 if the instruction has 224 /// any side effects other than storing to the stack slot. 225 virtual unsigned isStoreToStackSlot(MachineInstr *MI, int &FrameIndex) const { 226 return 0; 227 } 228 229 /// convertToThreeAddress - This method must be implemented by targets that 230 /// set the M_CONVERTIBLE_TO_3_ADDR flag. When this flag is set, the target 231 /// may be able to convert a two-address instruction into a true 232 /// three-address instruction on demand. This allows the X86 target (for 233 /// example) to convert ADD and SHL instructions into LEA instructions if they 234 /// would require register copies due to two-addressness. 235 /// 236 /// This method returns a null pointer if the transformation cannot be 237 /// performed, otherwise it returns the new instruction. 238 /// 239 virtual MachineInstr *convertToThreeAddress(MachineInstr *TA) const { 240 return 0; 241 } 242 243 /// commuteInstruction - If a target has any instructions that are commutable, 244 /// but require converting to a different instruction or making non-trivial 245 /// changes to commute them, this method can overloaded to do this. The 246 /// default implementation of this method simply swaps the first two operands 247 /// of MI and returns it. 248 /// 249 /// If a target wants to make more aggressive changes, they can construct and 250 /// return a new machine instruction. If an instruction cannot commute, it 251 /// can also return null. 252 /// 253 virtual MachineInstr *commuteInstruction(MachineInstr *MI) const; 254 255 /// Insert a goto (unconditional branch) sequence to TMBB, at the 256 /// end of MBB 257 virtual void insertGoto(MachineBasicBlock& MBB, 258 MachineBasicBlock& TMBB) const { 259 assert(0 && "Target didn't implement insertGoto!"); 260 } 261 262 /// Reverses the branch condition of the MachineInstr pointed by 263 /// MI. The instruction is replaced and the new MI is returned. 264 virtual MachineBasicBlock::iterator 265 reverseBranchCondition(MachineBasicBlock::iterator MI) const { 266 assert(0 && "Target didn't implement reverseBranchCondition!"); 267 abort(); 268 return MI; 269 } 270 271 /// insertNoop - Insert a noop into the instruction stream at the specified 272 /// point. 273 virtual void insertNoop(MachineBasicBlock &MBB, 274 MachineBasicBlock::iterator MI) const { 275 assert(0 && "Target didn't implement insertNoop!"); 276 abort(); 277 } 278 279 /// hasDelaySlot - Returns true if the specified instruction has a delay slot 280 /// which must be filled by the code generator. 281 bool hasDelaySlot(unsigned Opcode) const { 282 return get(Opcode).Flags & M_DELAY_SLOT_FLAG; 283 } 284}; 285 286} // End llvm namespace 287 288#endif 289