TargetInstrInfo.h revision 1b4aeb5cec6b6732d0833bac388c20de04fab961
1//===-- llvm/Target/TargetInstrInfo.h - Instruction Info --------*- C++ -*-===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file was developed by the LLVM research group and is distributed under 6// the University of Illinois Open Source License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This file describes the target machine instructions to the code generator. 11// 12//===----------------------------------------------------------------------===// 13 14#ifndef LLVM_TARGET_TARGETINSTRINFO_H 15#define LLVM_TARGET_TARGETINSTRINFO_H 16 17#include "Support/DataTypes.h" 18#include <vector> 19#include <cassert> 20 21namespace llvm { 22 23class MachineInstr; 24class TargetMachine; 25class Value; 26class Type; 27class Instruction; 28class Constant; 29class Function; 30class MachineCodeForInstruction; 31 32//--------------------------------------------------------------------------- 33// Data types used to define information about a single machine instruction 34//--------------------------------------------------------------------------- 35 36typedef short MachineOpCode; 37typedef unsigned InstrSchedClass; 38 39//--------------------------------------------------------------------------- 40// struct TargetInstrDescriptor: 41// Predefined information about each machine instruction. 42// Designed to initialized statically. 43// 44 45const unsigned M_NOP_FLAG = 1 << 0; 46const unsigned M_BRANCH_FLAG = 1 << 1; 47const unsigned M_CALL_FLAG = 1 << 2; 48const unsigned M_RET_FLAG = 1 << 3; 49const unsigned M_CC_FLAG = 1 << 6; 50const unsigned M_LOAD_FLAG = 1 << 10; 51const unsigned M_STORE_FLAG = 1 << 12; 52const unsigned M_DUMMY_PHI_FLAG = 1 << 13; 53const unsigned M_PSEUDO_FLAG = 1 << 14; // Pseudo instruction 54// 3-addr instructions which really work like 2-addr ones, eg. X86 add/sub 55const unsigned M_2_ADDR_FLAG = 1 << 15; 56 57// M_TERMINATOR_FLAG - Is this instruction part of the terminator for a basic 58// block? Typically this is things like return and branch instructions. 59// Various passes use this to insert code into the bottom of a basic block, but 60// before control flow occurs. 61const unsigned M_TERMINATOR_FLAG = 1 << 16; 62 63struct TargetInstrDescriptor { 64 const char * Name; // Assembly language mnemonic for the opcode. 65 int numOperands; // Number of args; -1 if variable #args 66 int resultPos; // Position of the result; -1 if no result 67 unsigned maxImmedConst; // Largest +ve constant in IMMED field or 0. 68 bool immedIsSignExtended; // Is IMMED field sign-extended? If so, 69 // smallest -ve value is -(maxImmedConst+1). 70 unsigned numDelaySlots; // Number of delay slots after instruction 71 unsigned latency; // Latency in machine cycles 72 InstrSchedClass schedClass; // enum identifying instr sched class 73 unsigned Flags; // flags identifying machine instr class 74 unsigned TSFlags; // Target Specific Flag values 75 const unsigned *ImplicitUses; // Registers implicitly read by this instr 76 const unsigned *ImplicitDefs; // Registers implicitly defined by this instr 77}; 78 79 80//--------------------------------------------------------------------------- 81/// 82/// TargetInstrInfo - Interface to description of machine instructions 83/// 84class TargetInstrInfo { 85 const TargetInstrDescriptor* desc; // raw array to allow static init'n 86 unsigned NumOpcodes; // number of entries in the desc array 87 unsigned numRealOpCodes; // number of non-dummy op codes 88 89 TargetInstrInfo(const TargetInstrInfo &); // DO NOT IMPLEMENT 90 void operator=(const TargetInstrInfo &); // DO NOT IMPLEMENT 91public: 92 TargetInstrInfo(const TargetInstrDescriptor *desc, unsigned NumOpcodes); 93 virtual ~TargetInstrInfo(); 94 95 // Invariant: All instruction sets use opcode #0 as the PHI instruction 96 enum { PHI = 0 }; 97 98 unsigned getNumOpcodes() const { return NumOpcodes; } 99 100 /// get - Return the machine instruction descriptor that corresponds to the 101 /// specified instruction opcode. 102 /// 103 const TargetInstrDescriptor& get(MachineOpCode opCode) const { 104 assert((unsigned)opCode < NumOpcodes); 105 return desc[opCode]; 106 } 107 108 const char *getName(MachineOpCode opCode) const { 109 return get(opCode).Name; 110 } 111 112 int getNumOperands(MachineOpCode opCode) const { 113 return get(opCode).numOperands; 114 } 115 116 117 InstrSchedClass getSchedClass(MachineOpCode opCode) const { 118 return get(opCode).schedClass; 119 } 120 121 const unsigned *getImplicitUses(MachineOpCode opCode) const { 122 return get(opCode).ImplicitUses; 123 } 124 125 const unsigned *getImplicitDefs(MachineOpCode opCode) const { 126 return get(opCode).ImplicitDefs; 127 } 128 129 130 // 131 // Query instruction class flags according to the machine-independent 132 // flags listed above. 133 // 134 bool isReturn(MachineOpCode opCode) const { 135 return get(opCode).Flags & M_RET_FLAG; 136 } 137 138 bool isPseudoInstr(MachineOpCode opCode) const { 139 return get(opCode).Flags & M_PSEUDO_FLAG; 140 } 141 bool isTwoAddrInstr(MachineOpCode opCode) const { 142 return get(opCode).Flags & M_2_ADDR_FLAG; 143 } 144 bool isTerminatorInstr(unsigned Opcode) const { 145 return get(Opcode).Flags & M_TERMINATOR_FLAG; 146 } 147 148 // 149 // Return true if the instruction is a register to register move and 150 // leave the source and dest operands in the passed parameters. 151 // 152 virtual bool isMoveInstr(const MachineInstr& MI, 153 unsigned& sourceReg, 154 unsigned& destReg) const { 155 return false; 156 } 157 158 159 160 161 //------------------------------------------------------------------------- 162 // Code generation support for creating individual machine instructions 163 // 164 // WARNING: These methods are Sparc specific 165 // 166 // DO NOT USE ANY OF THESE METHODS THEY ARE DEPRECATED! 167 // 168 //------------------------------------------------------------------------- 169 170 int getResultPos(MachineOpCode opCode) const { 171 return get(opCode).resultPos; 172 } 173 unsigned getNumDelaySlots(MachineOpCode opCode) const { 174 return get(opCode).numDelaySlots; 175 } 176 bool isCCInstr(MachineOpCode opCode) const { 177 return get(opCode).Flags & M_CC_FLAG; 178 } 179 bool isNop(MachineOpCode opCode) const { 180 return get(opCode).Flags & M_NOP_FLAG; 181 } 182 bool isBranch(MachineOpCode opCode) const { 183 return get(opCode).Flags & M_BRANCH_FLAG; 184 } 185 bool isCall(MachineOpCode opCode) const { 186 return get(opCode).Flags & M_CALL_FLAG; 187 } 188 bool isLoad(MachineOpCode opCode) const { 189 return get(opCode).Flags & M_LOAD_FLAG; 190 } 191 bool isStore(MachineOpCode opCode) const { 192 return get(opCode).Flags & M_STORE_FLAG; 193 } 194 bool isDummyPhiInstr(MachineOpCode opCode) const { 195 return get(opCode).Flags & M_DUMMY_PHI_FLAG; 196 } 197 // Check if an instruction can be issued before its operands are ready, 198 // or if a subsequent instruction that uses its result can be issued 199 // before the results are ready. 200 // Default to true since most instructions on many architectures allow this. 201 // 202 virtual bool hasOperandInterlock(MachineOpCode opCode) const { 203 return true; 204 } 205 virtual bool hasResultInterlock(MachineOpCode opCode) const { 206 return true; 207 } 208 209 // 210 // Latencies for individual instructions and instruction pairs 211 // 212 virtual int minLatency(MachineOpCode opCode) const { 213 return get(opCode).latency; 214 } 215 216 virtual int maxLatency(MachineOpCode opCode) const { 217 return get(opCode).latency; 218 } 219 220 // 221 // Which operand holds an immediate constant? Returns -1 if none 222 // 223 virtual int getImmedConstantPos(MachineOpCode opCode) const { 224 return -1; // immediate position is machine specific, so say -1 == "none" 225 } 226 227 // Check if the specified constant fits in the immediate field 228 // of this machine instruction 229 // 230 virtual bool constantFitsInImmedField(MachineOpCode opCode, 231 int64_t intValue) const; 232 233 // Return the largest positive constant that can be held in the IMMED field 234 // of this machine instruction. 235 // isSignExtended is set to true if the value is sign-extended before use 236 // (this is true for all immediate fields in SPARC instructions). 237 // Return 0 if the instruction has no IMMED field. 238 // 239 virtual uint64_t maxImmedConstant(MachineOpCode opCode, 240 bool &isSignExtended) const { 241 isSignExtended = get(opCode).immedIsSignExtended; 242 return get(opCode).maxImmedConst; 243 } 244 245 //------------------------------------------------------------------------- 246 // Queries about representation of LLVM quantities (e.g., constants) 247 //------------------------------------------------------------------------- 248 249 /// ConstantTypeMustBeLoaded - Test if this type of constant must be loaded 250 /// from memory into a register, i.e., cannot be set bitwise in register and 251 /// cannot use immediate fields of instructions. Note that this only makes 252 /// sense for primitive types. 253 /// 254 virtual bool ConstantTypeMustBeLoaded(const Constant* CV) const; 255}; 256 257} // End llvm namespace 258 259#endif 260