TargetInstrInfo.h revision 1ee29257428960fede862fcfdbe80d5d007927e9
127ed8ad2db653f6ac07dcf8bcc05e2409c8bb024aimitakeshi//===-- llvm/Target/TargetInstrInfo.h - Instruction Info --------*- C++ -*-===// 227ed8ad2db653f6ac07dcf8bcc05e2409c8bb024aimitakeshi// 327ed8ad2db653f6ac07dcf8bcc05e2409c8bb024aimitakeshi// The LLVM Compiler Infrastructure 427ed8ad2db653f6ac07dcf8bcc05e2409c8bb024aimitakeshi// 527ed8ad2db653f6ac07dcf8bcc05e2409c8bb024aimitakeshi// This file was developed by the LLVM research group and is distributed under 627ed8ad2db653f6ac07dcf8bcc05e2409c8bb024aimitakeshi// the University of Illinois Open Source License. See LICENSE.TXT for details. 727ed8ad2db653f6ac07dcf8bcc05e2409c8bb024aimitakeshi// 827ed8ad2db653f6ac07dcf8bcc05e2409c8bb024aimitakeshi//===----------------------------------------------------------------------===// 927ed8ad2db653f6ac07dcf8bcc05e2409c8bb024aimitakeshi// 1027ed8ad2db653f6ac07dcf8bcc05e2409c8bb024aimitakeshi// This file describes the target machine instructions to the code generator. 1127ed8ad2db653f6ac07dcf8bcc05e2409c8bb024aimitakeshi// 1227ed8ad2db653f6ac07dcf8bcc05e2409c8bb024aimitakeshi//===----------------------------------------------------------------------===// 1327ed8ad2db653f6ac07dcf8bcc05e2409c8bb024aimitakeshi 1427ed8ad2db653f6ac07dcf8bcc05e2409c8bb024aimitakeshi#ifndef LLVM_TARGET_TARGETINSTRINFO_H 1527ed8ad2db653f6ac07dcf8bcc05e2409c8bb024aimitakeshi#define LLVM_TARGET_TARGETINSTRINFO_H 1627ed8ad2db653f6ac07dcf8bcc05e2409c8bb024aimitakeshi 1727ed8ad2db653f6ac07dcf8bcc05e2409c8bb024aimitakeshi#include "llvm/CodeGen/MachineBasicBlock.h" 1827ed8ad2db653f6ac07dcf8bcc05e2409c8bb024aimitakeshi#include "llvm/CodeGen/MachineFunction.h" 1927ed8ad2db653f6ac07dcf8bcc05e2409c8bb024aimitakeshi#include "llvm/Support/DataTypes.h" 2027ed8ad2db653f6ac07dcf8bcc05e2409c8bb024aimitakeshi#include <vector> 2127ed8ad2db653f6ac07dcf8bcc05e2409c8bb024aimitakeshi#include <cassert> 2227ed8ad2db653f6ac07dcf8bcc05e2409c8bb024aimitakeshi 2327ed8ad2db653f6ac07dcf8bcc05e2409c8bb024aimitakeshinamespace llvm { 2427ed8ad2db653f6ac07dcf8bcc05e2409c8bb024aimitakeshi 253473846f64f5b28e1cbeb70ef5867073fc93159eTakeshi Aimiclass MachineInstr; 2627ed8ad2db653f6ac07dcf8bcc05e2409c8bb024aimitakeshiclass TargetMachine; 2727ed8ad2db653f6ac07dcf8bcc05e2409c8bb024aimitakeshiclass Value; 2827ed8ad2db653f6ac07dcf8bcc05e2409c8bb024aimitakeshiclass Type; 2927ed8ad2db653f6ac07dcf8bcc05e2409c8bb024aimitakeshiclass Instruction; 3027ed8ad2db653f6ac07dcf8bcc05e2409c8bb024aimitakeshiclass Constant; 3127ed8ad2db653f6ac07dcf8bcc05e2409c8bb024aimitakeshiclass Function; 3227ed8ad2db653f6ac07dcf8bcc05e2409c8bb024aimitakeshiclass MachineCodeForInstruction; 3327ed8ad2db653f6ac07dcf8bcc05e2409c8bb024aimitakeshiclass TargetRegisterClass; 3427ed8ad2db653f6ac07dcf8bcc05e2409c8bb024aimitakeshiclass LiveVariables; 3527ed8ad2db653f6ac07dcf8bcc05e2409c8bb024aimitakeshi 3627ed8ad2db653f6ac07dcf8bcc05e2409c8bb024aimitakeshi//--------------------------------------------------------------------------- 3727ed8ad2db653f6ac07dcf8bcc05e2409c8bb024aimitakeshi// Data types used to define information about a single machine instruction 3827ed8ad2db653f6ac07dcf8bcc05e2409c8bb024aimitakeshi//--------------------------------------------------------------------------- 3927ed8ad2db653f6ac07dcf8bcc05e2409c8bb024aimitakeshi 4027ed8ad2db653f6ac07dcf8bcc05e2409c8bb024aimitakeshitypedef short MachineOpCode; 4127ed8ad2db653f6ac07dcf8bcc05e2409c8bb024aimitakeshitypedef unsigned InstrSchedClass; 4227ed8ad2db653f6ac07dcf8bcc05e2409c8bb024aimitakeshi 4327ed8ad2db653f6ac07dcf8bcc05e2409c8bb024aimitakeshi//--------------------------------------------------------------------------- 4427ed8ad2db653f6ac07dcf8bcc05e2409c8bb024aimitakeshi// struct TargetInstrDescriptor: 4527ed8ad2db653f6ac07dcf8bcc05e2409c8bb024aimitakeshi// Predefined information about each machine instruction. 4627ed8ad2db653f6ac07dcf8bcc05e2409c8bb024aimitakeshi// Designed to initialized statically. 4727ed8ad2db653f6ac07dcf8bcc05e2409c8bb024aimitakeshi// 4827ed8ad2db653f6ac07dcf8bcc05e2409c8bb024aimitakeshi 4927ed8ad2db653f6ac07dcf8bcc05e2409c8bb024aimitakeshiconst unsigned M_BRANCH_FLAG = 1 << 0; 5027ed8ad2db653f6ac07dcf8bcc05e2409c8bb024aimitakeshiconst unsigned M_CALL_FLAG = 1 << 1; 5127ed8ad2db653f6ac07dcf8bcc05e2409c8bb024aimitakeshiconst unsigned M_RET_FLAG = 1 << 2; 5227ed8ad2db653f6ac07dcf8bcc05e2409c8bb024aimitakeshiconst unsigned M_BARRIER_FLAG = 1 << 3; 5327ed8ad2db653f6ac07dcf8bcc05e2409c8bb024aimitakeshiconst unsigned M_DELAY_SLOT_FLAG = 1 << 4; 5427ed8ad2db653f6ac07dcf8bcc05e2409c8bb024aimitakeshiconst unsigned M_LOAD_FLAG = 1 << 5; 5527ed8ad2db653f6ac07dcf8bcc05e2409c8bb024aimitakeshiconst unsigned M_STORE_FLAG = 1 << 6; 5627ed8ad2db653f6ac07dcf8bcc05e2409c8bb024aimitakeshi 5727ed8ad2db653f6ac07dcf8bcc05e2409c8bb024aimitakeshi// M_CONVERTIBLE_TO_3_ADDR - This is a 2-address instruction which can be 5827ed8ad2db653f6ac07dcf8bcc05e2409c8bb024aimitakeshi// changed into a 3-address instruction if the first two operands cannot be 5927ed8ad2db653f6ac07dcf8bcc05e2409c8bb024aimitakeshi// assigned to the same register. The target must implement the 6027ed8ad2db653f6ac07dcf8bcc05e2409c8bb024aimitakeshi// TargetInstrInfo::convertToThreeAddress method for this instruction. 6127ed8ad2db653f6ac07dcf8bcc05e2409c8bb024aimitakeshiconst unsigned M_CONVERTIBLE_TO_3_ADDR = 1 << 7; 6227ed8ad2db653f6ac07dcf8bcc05e2409c8bb024aimitakeshi 6327ed8ad2db653f6ac07dcf8bcc05e2409c8bb024aimitakeshi// This M_COMMUTABLE - is a 2- or 3-address instruction (of the form X = op Y, 6427ed8ad2db653f6ac07dcf8bcc05e2409c8bb024aimitakeshi// Z), which produces the same result if Y and Z are exchanged. 6527ed8ad2db653f6ac07dcf8bcc05e2409c8bb024aimitakeshiconst unsigned M_COMMUTABLE = 1 << 8; 6627ed8ad2db653f6ac07dcf8bcc05e2409c8bb024aimitakeshi 6727ed8ad2db653f6ac07dcf8bcc05e2409c8bb024aimitakeshi// M_TERMINATOR_FLAG - Is this instruction part of the terminator for a basic 6827ed8ad2db653f6ac07dcf8bcc05e2409c8bb024aimitakeshi// block? Typically this is things like return and branch instructions. 6927ed8ad2db653f6ac07dcf8bcc05e2409c8bb024aimitakeshi// Various passes use this to insert code into the bottom of a basic block, but 7027ed8ad2db653f6ac07dcf8bcc05e2409c8bb024aimitakeshi// before control flow occurs. 7127ed8ad2db653f6ac07dcf8bcc05e2409c8bb024aimitakeshiconst unsigned M_TERMINATOR_FLAG = 1 << 9; 7227ed8ad2db653f6ac07dcf8bcc05e2409c8bb024aimitakeshi 7327ed8ad2db653f6ac07dcf8bcc05e2409c8bb024aimitakeshi// M_USES_CUSTOM_DAG_SCHED_INSERTION - Set if this instruction requires custom 7427ed8ad2db653f6ac07dcf8bcc05e2409c8bb024aimitakeshi// insertion support when the DAG scheduler is inserting it into a machine basic 7527ed8ad2db653f6ac07dcf8bcc05e2409c8bb024aimitakeshi// block. 7627ed8ad2db653f6ac07dcf8bcc05e2409c8bb024aimitakeshiconst unsigned M_USES_CUSTOM_DAG_SCHED_INSERTION = 1 << 10; 7727ed8ad2db653f6ac07dcf8bcc05e2409c8bb024aimitakeshi 7827ed8ad2db653f6ac07dcf8bcc05e2409c8bb024aimitakeshi// M_VARIABLE_OPS - Set if this instruction can have a variable number of extra 7927ed8ad2db653f6ac07dcf8bcc05e2409c8bb024aimitakeshi// operands in addition to the minimum number operands specified. 8027ed8ad2db653f6ac07dcf8bcc05e2409c8bb024aimitakeshiconst unsigned M_VARIABLE_OPS = 1 << 11; 8127ed8ad2db653f6ac07dcf8bcc05e2409c8bb024aimitakeshi 8227ed8ad2db653f6ac07dcf8bcc05e2409c8bb024aimitakeshi// M_PREDICATED - Set if this instruction has a predicate that controls its 8327ed8ad2db653f6ac07dcf8bcc05e2409c8bb024aimitakeshi// execution. 8427ed8ad2db653f6ac07dcf8bcc05e2409c8bb024aimitakeshiconst unsigned M_PREDICATED = 1 << 12; 8527ed8ad2db653f6ac07dcf8bcc05e2409c8bb024aimitakeshi 8627ed8ad2db653f6ac07dcf8bcc05e2409c8bb024aimitakeshi 8727ed8ad2db653f6ac07dcf8bcc05e2409c8bb024aimitakeshi// Machine operand flags 8827ed8ad2db653f6ac07dcf8bcc05e2409c8bb024aimitakeshi// M_LOOK_UP_PTR_REG_CLASS - Set if this operand is a pointer value and it 8927ed8ad2db653f6ac07dcf8bcc05e2409c8bb024aimitakeshi// requires a callback to look up its register class. 9027ed8ad2db653f6ac07dcf8bcc05e2409c8bb024aimitakeshiconst unsigned M_LOOK_UP_PTR_REG_CLASS = 1 << 0; 9127ed8ad2db653f6ac07dcf8bcc05e2409c8bb024aimitakeshi 9227ed8ad2db653f6ac07dcf8bcc05e2409c8bb024aimitakeshi/// M_PREDICATE_OPERAND - Set if this is the first operand of a predicate 9327ed8ad2db653f6ac07dcf8bcc05e2409c8bb024aimitakeshi/// operand that controls an M_PREDICATED instruction. 9427ed8ad2db653f6ac07dcf8bcc05e2409c8bb024aimitakeshiconst unsigned M_PREDICATE_OPERAND = 1 << 1; 9527ed8ad2db653f6ac07dcf8bcc05e2409c8bb024aimitakeshi 9627ed8ad2db653f6ac07dcf8bcc05e2409c8bb024aimitakeshinamespace TOI { 9727ed8ad2db653f6ac07dcf8bcc05e2409c8bb024aimitakeshi // Operand constraints: only "tied_to" for now. 9827ed8ad2db653f6ac07dcf8bcc05e2409c8bb024aimitakeshi enum OperandConstraint { 9927ed8ad2db653f6ac07dcf8bcc05e2409c8bb024aimitakeshi TIED_TO = 0 // Must be allocated the same register as. 10027ed8ad2db653f6ac07dcf8bcc05e2409c8bb024aimitakeshi }; 10127ed8ad2db653f6ac07dcf8bcc05e2409c8bb024aimitakeshi} 10227ed8ad2db653f6ac07dcf8bcc05e2409c8bb024aimitakeshi 10327ed8ad2db653f6ac07dcf8bcc05e2409c8bb024aimitakeshi/// TargetOperandInfo - This holds information about one operand of a machine 10427ed8ad2db653f6ac07dcf8bcc05e2409c8bb024aimitakeshi/// instruction, indicating the register class for register operands, etc. 10527ed8ad2db653f6ac07dcf8bcc05e2409c8bb024aimitakeshi/// 10627ed8ad2db653f6ac07dcf8bcc05e2409c8bb024aimitakeshiclass TargetOperandInfo { 10727ed8ad2db653f6ac07dcf8bcc05e2409c8bb024aimitakeshipublic: 1083473846f64f5b28e1cbeb70ef5867073fc93159eTakeshi Aimi /// RegClass - This specifies the register class enumeration of the operand 1093473846f64f5b28e1cbeb70ef5867073fc93159eTakeshi Aimi /// if the operand is a register. If not, this contains 0. 1103473846f64f5b28e1cbeb70ef5867073fc93159eTakeshi Aimi unsigned short RegClass; 1113473846f64f5b28e1cbeb70ef5867073fc93159eTakeshi Aimi unsigned short Flags; 1123473846f64f5b28e1cbeb70ef5867073fc93159eTakeshi Aimi /// Lower 16 bits are used to specify which constraints are set. The higher 16 1133473846f64f5b28e1cbeb70ef5867073fc93159eTakeshi Aimi /// bits are used to specify the value of constraints (4 bits each). 1143473846f64f5b28e1cbeb70ef5867073fc93159eTakeshi Aimi unsigned int Constraints; 1153473846f64f5b28e1cbeb70ef5867073fc93159eTakeshi Aimi /// Currently no other information. 1163473846f64f5b28e1cbeb70ef5867073fc93159eTakeshi Aimi}; 1173473846f64f5b28e1cbeb70ef5867073fc93159eTakeshi Aimi 1183473846f64f5b28e1cbeb70ef5867073fc93159eTakeshi Aimi 1193473846f64f5b28e1cbeb70ef5867073fc93159eTakeshi Aimiclass TargetInstrDescriptor { 12027ed8ad2db653f6ac07dcf8bcc05e2409c8bb024aimitakeshipublic: 12127ed8ad2db653f6ac07dcf8bcc05e2409c8bb024aimitakeshi MachineOpCode Opcode; // The opcode. 12227ed8ad2db653f6ac07dcf8bcc05e2409c8bb024aimitakeshi unsigned short numOperands; // Num of args (may be more if variable_ops). 12327ed8ad2db653f6ac07dcf8bcc05e2409c8bb024aimitakeshi const char * Name; // Assembly language mnemonic for the opcode. 12427ed8ad2db653f6ac07dcf8bcc05e2409c8bb024aimitakeshi InstrSchedClass schedClass; // enum identifying instr sched class 12527ed8ad2db653f6ac07dcf8bcc05e2409c8bb024aimitakeshi unsigned Flags; // flags identifying machine instr class 12627ed8ad2db653f6ac07dcf8bcc05e2409c8bb024aimitakeshi unsigned TSFlags; // Target Specific Flag values 12727ed8ad2db653f6ac07dcf8bcc05e2409c8bb024aimitakeshi const unsigned *ImplicitUses; // Registers implicitly read by this instr 12827ed8ad2db653f6ac07dcf8bcc05e2409c8bb024aimitakeshi const unsigned *ImplicitDefs; // Registers implicitly defined by this instr 12927ed8ad2db653f6ac07dcf8bcc05e2409c8bb024aimitakeshi const TargetOperandInfo *OpInfo; // 'numOperands' entries about operands. 13027ed8ad2db653f6ac07dcf8bcc05e2409c8bb024aimitakeshi 13127ed8ad2db653f6ac07dcf8bcc05e2409c8bb024aimitakeshi /// getOperandConstraint - Returns the value of the specific constraint if 13227ed8ad2db653f6ac07dcf8bcc05e2409c8bb024aimitakeshi /// it is set. Returns -1 if it is not set. 13327ed8ad2db653f6ac07dcf8bcc05e2409c8bb024aimitakeshi int getOperandConstraint(unsigned OpNum, 13427ed8ad2db653f6ac07dcf8bcc05e2409c8bb024aimitakeshi TOI::OperandConstraint Constraint) const { 13527ed8ad2db653f6ac07dcf8bcc05e2409c8bb024aimitakeshi assert((OpNum < numOperands || (Flags & M_VARIABLE_OPS)) && 13627ed8ad2db653f6ac07dcf8bcc05e2409c8bb024aimitakeshi "Invalid operand # of TargetInstrInfo"); 13727ed8ad2db653f6ac07dcf8bcc05e2409c8bb024aimitakeshi if (OpNum < numOperands && 13827ed8ad2db653f6ac07dcf8bcc05e2409c8bb024aimitakeshi (OpInfo[OpNum].Constraints & (1 << Constraint))) { 13927ed8ad2db653f6ac07dcf8bcc05e2409c8bb024aimitakeshi unsigned Pos = 16 + Constraint * 4; 14027ed8ad2db653f6ac07dcf8bcc05e2409c8bb024aimitakeshi return (int)(OpInfo[OpNum].Constraints >> Pos) & 0xf; 14127ed8ad2db653f6ac07dcf8bcc05e2409c8bb024aimitakeshi } 14227ed8ad2db653f6ac07dcf8bcc05e2409c8bb024aimitakeshi return -1; 14327ed8ad2db653f6ac07dcf8bcc05e2409c8bb024aimitakeshi } 14427ed8ad2db653f6ac07dcf8bcc05e2409c8bb024aimitakeshi 14527ed8ad2db653f6ac07dcf8bcc05e2409c8bb024aimitakeshi /// findTiedToSrcOperand - Returns the operand that is tied to the specified 14627ed8ad2db653f6ac07dcf8bcc05e2409c8bb024aimitakeshi /// dest operand. Returns -1 if there isn't one. 14727ed8ad2db653f6ac07dcf8bcc05e2409c8bb024aimitakeshi int findTiedToSrcOperand(unsigned OpNum) const; 14827ed8ad2db653f6ac07dcf8bcc05e2409c8bb024aimitakeshi}; 14927ed8ad2db653f6ac07dcf8bcc05e2409c8bb024aimitakeshi 15027ed8ad2db653f6ac07dcf8bcc05e2409c8bb024aimitakeshi 15127ed8ad2db653f6ac07dcf8bcc05e2409c8bb024aimitakeshi//--------------------------------------------------------------------------- 15227ed8ad2db653f6ac07dcf8bcc05e2409c8bb024aimitakeshi/// 15327ed8ad2db653f6ac07dcf8bcc05e2409c8bb024aimitakeshi/// TargetInstrInfo - Interface to description of machine instructions 15427ed8ad2db653f6ac07dcf8bcc05e2409c8bb024aimitakeshi/// 15527ed8ad2db653f6ac07dcf8bcc05e2409c8bb024aimitakeshiclass TargetInstrInfo { 15627ed8ad2db653f6ac07dcf8bcc05e2409c8bb024aimitakeshi const TargetInstrDescriptor* desc; // raw array to allow static init'n 15727ed8ad2db653f6ac07dcf8bcc05e2409c8bb024aimitakeshi unsigned NumOpcodes; // number of entries in the desc array 1582272ee27d9022d173b6eab45c409b3c3f57f30ecTakeshi Aimi unsigned numRealOpCodes; // number of non-dummy op codes 1592272ee27d9022d173b6eab45c409b3c3f57f30ecTakeshi Aimi 16027ed8ad2db653f6ac07dcf8bcc05e2409c8bb024aimitakeshi TargetInstrInfo(const TargetInstrInfo &); // DO NOT IMPLEMENT 1612272ee27d9022d173b6eab45c409b3c3f57f30ecTakeshi Aimi void operator=(const TargetInstrInfo &); // DO NOT IMPLEMENT 16227ed8ad2db653f6ac07dcf8bcc05e2409c8bb024aimitakeshipublic: 16327ed8ad2db653f6ac07dcf8bcc05e2409c8bb024aimitakeshi TargetInstrInfo(const TargetInstrDescriptor *desc, unsigned NumOpcodes); 16427ed8ad2db653f6ac07dcf8bcc05e2409c8bb024aimitakeshi virtual ~TargetInstrInfo(); 16527ed8ad2db653f6ac07dcf8bcc05e2409c8bb024aimitakeshi 16627ed8ad2db653f6ac07dcf8bcc05e2409c8bb024aimitakeshi // Invariant opcodes: All instruction sets have these as their low opcodes. 16727ed8ad2db653f6ac07dcf8bcc05e2409c8bb024aimitakeshi enum { 16827ed8ad2db653f6ac07dcf8bcc05e2409c8bb024aimitakeshi PHI = 0, 16927ed8ad2db653f6ac07dcf8bcc05e2409c8bb024aimitakeshi INLINEASM = 1, 17027ed8ad2db653f6ac07dcf8bcc05e2409c8bb024aimitakeshi LABEL = 2 17127ed8ad2db653f6ac07dcf8bcc05e2409c8bb024aimitakeshi }; 17227ed8ad2db653f6ac07dcf8bcc05e2409c8bb024aimitakeshi 17327ed8ad2db653f6ac07dcf8bcc05e2409c8bb024aimitakeshi unsigned getNumOpcodes() const { return NumOpcodes; } 17427ed8ad2db653f6ac07dcf8bcc05e2409c8bb024aimitakeshi 17527ed8ad2db653f6ac07dcf8bcc05e2409c8bb024aimitakeshi /// get - Return the machine instruction descriptor that corresponds to the 17627ed8ad2db653f6ac07dcf8bcc05e2409c8bb024aimitakeshi /// specified instruction opcode. 17727ed8ad2db653f6ac07dcf8bcc05e2409c8bb024aimitakeshi /// 17827ed8ad2db653f6ac07dcf8bcc05e2409c8bb024aimitakeshi const TargetInstrDescriptor& get(MachineOpCode Opcode) const { 17927ed8ad2db653f6ac07dcf8bcc05e2409c8bb024aimitakeshi assert((unsigned)Opcode < NumOpcodes); 18027ed8ad2db653f6ac07dcf8bcc05e2409c8bb024aimitakeshi return desc[Opcode]; 18127ed8ad2db653f6ac07dcf8bcc05e2409c8bb024aimitakeshi } 18227ed8ad2db653f6ac07dcf8bcc05e2409c8bb024aimitakeshi 18327ed8ad2db653f6ac07dcf8bcc05e2409c8bb024aimitakeshi const char *getName(MachineOpCode Opcode) const { 18427ed8ad2db653f6ac07dcf8bcc05e2409c8bb024aimitakeshi return get(Opcode).Name; 18527ed8ad2db653f6ac07dcf8bcc05e2409c8bb024aimitakeshi } 18627ed8ad2db653f6ac07dcf8bcc05e2409c8bb024aimitakeshi 18727ed8ad2db653f6ac07dcf8bcc05e2409c8bb024aimitakeshi int getNumOperands(MachineOpCode Opcode) const { 18827ed8ad2db653f6ac07dcf8bcc05e2409c8bb024aimitakeshi return get(Opcode).numOperands; 18927ed8ad2db653f6ac07dcf8bcc05e2409c8bb024aimitakeshi } 19027ed8ad2db653f6ac07dcf8bcc05e2409c8bb024aimitakeshi 19127ed8ad2db653f6ac07dcf8bcc05e2409c8bb024aimitakeshi InstrSchedClass getSchedClass(MachineOpCode Opcode) const { 19227ed8ad2db653f6ac07dcf8bcc05e2409c8bb024aimitakeshi return get(Opcode).schedClass; 19327ed8ad2db653f6ac07dcf8bcc05e2409c8bb024aimitakeshi } 19427ed8ad2db653f6ac07dcf8bcc05e2409c8bb024aimitakeshi 19527ed8ad2db653f6ac07dcf8bcc05e2409c8bb024aimitakeshi const unsigned *getImplicitUses(MachineOpCode Opcode) const { 19627ed8ad2db653f6ac07dcf8bcc05e2409c8bb024aimitakeshi return get(Opcode).ImplicitUses; 19727ed8ad2db653f6ac07dcf8bcc05e2409c8bb024aimitakeshi } 19827ed8ad2db653f6ac07dcf8bcc05e2409c8bb024aimitakeshi 19927ed8ad2db653f6ac07dcf8bcc05e2409c8bb024aimitakeshi const unsigned *getImplicitDefs(MachineOpCode Opcode) const { 20027ed8ad2db653f6ac07dcf8bcc05e2409c8bb024aimitakeshi return get(Opcode).ImplicitDefs; 20127ed8ad2db653f6ac07dcf8bcc05e2409c8bb024aimitakeshi } 20227ed8ad2db653f6ac07dcf8bcc05e2409c8bb024aimitakeshi 20327ed8ad2db653f6ac07dcf8bcc05e2409c8bb024aimitakeshi 20427ed8ad2db653f6ac07dcf8bcc05e2409c8bb024aimitakeshi // 20527ed8ad2db653f6ac07dcf8bcc05e2409c8bb024aimitakeshi // Query instruction class flags according to the machine-independent 20627ed8ad2db653f6ac07dcf8bcc05e2409c8bb024aimitakeshi // flags listed above. 20727ed8ad2db653f6ac07dcf8bcc05e2409c8bb024aimitakeshi // 2082272ee27d9022d173b6eab45c409b3c3f57f30ecTakeshi Aimi bool isReturn(MachineOpCode Opcode) const { 2092272ee27d9022d173b6eab45c409b3c3f57f30ecTakeshi Aimi return get(Opcode).Flags & M_RET_FLAG; 21027ed8ad2db653f6ac07dcf8bcc05e2409c8bb024aimitakeshi } 2112272ee27d9022d173b6eab45c409b3c3f57f30ecTakeshi Aimi 21227ed8ad2db653f6ac07dcf8bcc05e2409c8bb024aimitakeshi bool isPredicated(MachineOpCode Opcode) const { 21327ed8ad2db653f6ac07dcf8bcc05e2409c8bb024aimitakeshi return get(Opcode).Flags & M_PREDICATED; 21427ed8ad2db653f6ac07dcf8bcc05e2409c8bb024aimitakeshi } 21527ed8ad2db653f6ac07dcf8bcc05e2409c8bb024aimitakeshi bool isCommutableInstr(MachineOpCode Opcode) const { 21627ed8ad2db653f6ac07dcf8bcc05e2409c8bb024aimitakeshi return get(Opcode).Flags & M_COMMUTABLE; 21727ed8ad2db653f6ac07dcf8bcc05e2409c8bb024aimitakeshi } 21827ed8ad2db653f6ac07dcf8bcc05e2409c8bb024aimitakeshi bool isTerminatorInstr(unsigned Opcode) const { 21927ed8ad2db653f6ac07dcf8bcc05e2409c8bb024aimitakeshi return get(Opcode).Flags & M_TERMINATOR_FLAG; 22027ed8ad2db653f6ac07dcf8bcc05e2409c8bb024aimitakeshi } 22127ed8ad2db653f6ac07dcf8bcc05e2409c8bb024aimitakeshi 2222272ee27d9022d173b6eab45c409b3c3f57f30ecTakeshi Aimi bool isBranch(MachineOpCode Opcode) const { 2232272ee27d9022d173b6eab45c409b3c3f57f30ecTakeshi Aimi return get(Opcode).Flags & M_BRANCH_FLAG; 22427ed8ad2db653f6ac07dcf8bcc05e2409c8bb024aimitakeshi } 2252272ee27d9022d173b6eab45c409b3c3f57f30ecTakeshi Aimi 226a2cd44cb5067b4fe98794860690394254d3ac73cGloria Wang /// isBarrier - Returns true if the specified instruction stops control flow 22727ed8ad2db653f6ac07dcf8bcc05e2409c8bb024aimitakeshi /// from executing the instruction immediately following it. Examples include 22827ed8ad2db653f6ac07dcf8bcc05e2409c8bb024aimitakeshi /// unconditional branches and return instructions. 22927ed8ad2db653f6ac07dcf8bcc05e2409c8bb024aimitakeshi bool isBarrier(MachineOpCode Opcode) const { 23027ed8ad2db653f6ac07dcf8bcc05e2409c8bb024aimitakeshi return get(Opcode).Flags & M_BARRIER_FLAG; 23127ed8ad2db653f6ac07dcf8bcc05e2409c8bb024aimitakeshi } 23227ed8ad2db653f6ac07dcf8bcc05e2409c8bb024aimitakeshi 23327ed8ad2db653f6ac07dcf8bcc05e2409c8bb024aimitakeshi bool isCall(MachineOpCode Opcode) const { 23427ed8ad2db653f6ac07dcf8bcc05e2409c8bb024aimitakeshi return get(Opcode).Flags & M_CALL_FLAG; 23527ed8ad2db653f6ac07dcf8bcc05e2409c8bb024aimitakeshi } 23627ed8ad2db653f6ac07dcf8bcc05e2409c8bb024aimitakeshi bool isLoad(MachineOpCode Opcode) const { 23727ed8ad2db653f6ac07dcf8bcc05e2409c8bb024aimitakeshi return get(Opcode).Flags & M_LOAD_FLAG; 23827ed8ad2db653f6ac07dcf8bcc05e2409c8bb024aimitakeshi } 23927ed8ad2db653f6ac07dcf8bcc05e2409c8bb024aimitakeshi bool isStore(MachineOpCode Opcode) const { 24027ed8ad2db653f6ac07dcf8bcc05e2409c8bb024aimitakeshi return get(Opcode).Flags & M_STORE_FLAG; 24127ed8ad2db653f6ac07dcf8bcc05e2409c8bb024aimitakeshi } 24227ed8ad2db653f6ac07dcf8bcc05e2409c8bb024aimitakeshi 24327ed8ad2db653f6ac07dcf8bcc05e2409c8bb024aimitakeshi /// hasDelaySlot - Returns true if the specified instruction has a delay slot 24427ed8ad2db653f6ac07dcf8bcc05e2409c8bb024aimitakeshi /// which must be filled by the code generator. 2452272ee27d9022d173b6eab45c409b3c3f57f30ecTakeshi Aimi bool hasDelaySlot(unsigned Opcode) const { 2462272ee27d9022d173b6eab45c409b3c3f57f30ecTakeshi Aimi return get(Opcode).Flags & M_DELAY_SLOT_FLAG; 24727ed8ad2db653f6ac07dcf8bcc05e2409c8bb024aimitakeshi } 2482272ee27d9022d173b6eab45c409b3c3f57f30ecTakeshi Aimi 24927ed8ad2db653f6ac07dcf8bcc05e2409c8bb024aimitakeshi /// usesCustomDAGSchedInsertionHook - Return true if this instruction requires 25027ed8ad2db653f6ac07dcf8bcc05e2409c8bb024aimitakeshi /// custom insertion support when the DAG scheduler is inserting it into a 25127ed8ad2db653f6ac07dcf8bcc05e2409c8bb024aimitakeshi /// machine basic block. 25227ed8ad2db653f6ac07dcf8bcc05e2409c8bb024aimitakeshi bool usesCustomDAGSchedInsertionHook(unsigned Opcode) const { 25327ed8ad2db653f6ac07dcf8bcc05e2409c8bb024aimitakeshi return get(Opcode).Flags & M_USES_CUSTOM_DAG_SCHED_INSERTION; 25427ed8ad2db653f6ac07dcf8bcc05e2409c8bb024aimitakeshi } 2552272ee27d9022d173b6eab45c409b3c3f57f30ecTakeshi Aimi 2562272ee27d9022d173b6eab45c409b3c3f57f30ecTakeshi Aimi bool hasVariableOperands(MachineOpCode Opcode) const { 25727ed8ad2db653f6ac07dcf8bcc05e2409c8bb024aimitakeshi return get(Opcode).Flags & M_VARIABLE_OPS; 2582272ee27d9022d173b6eab45c409b3c3f57f30ecTakeshi Aimi } 25927ed8ad2db653f6ac07dcf8bcc05e2409c8bb024aimitakeshi 26027ed8ad2db653f6ac07dcf8bcc05e2409c8bb024aimitakeshi /// getOperandConstraint - Returns the value of the specific constraint if 26127ed8ad2db653f6ac07dcf8bcc05e2409c8bb024aimitakeshi /// it is set. Returns -1 if it is not set. 26227ed8ad2db653f6ac07dcf8bcc05e2409c8bb024aimitakeshi int getOperandConstraint(MachineOpCode Opcode, unsigned OpNum, 26327ed8ad2db653f6ac07dcf8bcc05e2409c8bb024aimitakeshi TOI::OperandConstraint Constraint) const { 26427ed8ad2db653f6ac07dcf8bcc05e2409c8bb024aimitakeshi return get(Opcode).getOperandConstraint(OpNum, Constraint); 26527ed8ad2db653f6ac07dcf8bcc05e2409c8bb024aimitakeshi } 26627ed8ad2db653f6ac07dcf8bcc05e2409c8bb024aimitakeshi 26727ed8ad2db653f6ac07dcf8bcc05e2409c8bb024aimitakeshi /// Return true if the instruction is a register to register move 2682272ee27d9022d173b6eab45c409b3c3f57f30ecTakeshi Aimi /// and leave the source and dest operands in the passed parameters. 2692272ee27d9022d173b6eab45c409b3c3f57f30ecTakeshi Aimi virtual bool isMoveInstr(const MachineInstr& MI, 27027ed8ad2db653f6ac07dcf8bcc05e2409c8bb024aimitakeshi unsigned& sourceReg, 2712272ee27d9022d173b6eab45c409b3c3f57f30ecTakeshi Aimi unsigned& destReg) const { 27227ed8ad2db653f6ac07dcf8bcc05e2409c8bb024aimitakeshi return false; 27327ed8ad2db653f6ac07dcf8bcc05e2409c8bb024aimitakeshi } 27427ed8ad2db653f6ac07dcf8bcc05e2409c8bb024aimitakeshi 27527ed8ad2db653f6ac07dcf8bcc05e2409c8bb024aimitakeshi /// isLoadFromStackSlot - If the specified machine instruction is a direct 27627ed8ad2db653f6ac07dcf8bcc05e2409c8bb024aimitakeshi /// load from a stack slot, return the virtual or physical register number of 27727ed8ad2db653f6ac07dcf8bcc05e2409c8bb024aimitakeshi /// the destination along with the FrameIndex of the loaded stack slot. If 27827ed8ad2db653f6ac07dcf8bcc05e2409c8bb024aimitakeshi /// not, return 0. This predicate must return 0 if the instruction has 27927ed8ad2db653f6ac07dcf8bcc05e2409c8bb024aimitakeshi /// any side effects other than loading from the stack slot. 28027ed8ad2db653f6ac07dcf8bcc05e2409c8bb024aimitakeshi virtual unsigned isLoadFromStackSlot(MachineInstr *MI, int &FrameIndex) const{ 28127ed8ad2db653f6ac07dcf8bcc05e2409c8bb024aimitakeshi return 0; 28227ed8ad2db653f6ac07dcf8bcc05e2409c8bb024aimitakeshi } 28327ed8ad2db653f6ac07dcf8bcc05e2409c8bb024aimitakeshi 28427ed8ad2db653f6ac07dcf8bcc05e2409c8bb024aimitakeshi /// isStoreToStackSlot - If the specified machine instruction is a direct 28527ed8ad2db653f6ac07dcf8bcc05e2409c8bb024aimitakeshi /// store to a stack slot, return the virtual or physical register number of 28627ed8ad2db653f6ac07dcf8bcc05e2409c8bb024aimitakeshi /// the source reg along with the FrameIndex of the loaded stack slot. If 28727ed8ad2db653f6ac07dcf8bcc05e2409c8bb024aimitakeshi /// not, return 0. This predicate must return 0 if the instruction has 28827ed8ad2db653f6ac07dcf8bcc05e2409c8bb024aimitakeshi /// any side effects other than storing to the stack slot. 28927ed8ad2db653f6ac07dcf8bcc05e2409c8bb024aimitakeshi virtual unsigned isStoreToStackSlot(MachineInstr *MI, int &FrameIndex) const { 29027ed8ad2db653f6ac07dcf8bcc05e2409c8bb024aimitakeshi return 0; 29127ed8ad2db653f6ac07dcf8bcc05e2409c8bb024aimitakeshi } 29227ed8ad2db653f6ac07dcf8bcc05e2409c8bb024aimitakeshi 29327ed8ad2db653f6ac07dcf8bcc05e2409c8bb024aimitakeshi /// convertToThreeAddress - This method must be implemented by targets that 29427ed8ad2db653f6ac07dcf8bcc05e2409c8bb024aimitakeshi /// set the M_CONVERTIBLE_TO_3_ADDR flag. When this flag is set, the target 29527ed8ad2db653f6ac07dcf8bcc05e2409c8bb024aimitakeshi /// may be able to convert a two-address instruction into one or moretrue 29627ed8ad2db653f6ac07dcf8bcc05e2409c8bb024aimitakeshi /// three-address instructions on demand. This allows the X86 target (for 29727ed8ad2db653f6ac07dcf8bcc05e2409c8bb024aimitakeshi /// example) to convert ADD and SHL instructions into LEA instructions if they 29827ed8ad2db653f6ac07dcf8bcc05e2409c8bb024aimitakeshi /// would require register copies due to two-addressness. 29927ed8ad2db653f6ac07dcf8bcc05e2409c8bb024aimitakeshi /// 30027ed8ad2db653f6ac07dcf8bcc05e2409c8bb024aimitakeshi /// This method returns a null pointer if the transformation cannot be 30127ed8ad2db653f6ac07dcf8bcc05e2409c8bb024aimitakeshi /// performed, otherwise it returns the last new instruction. 30227ed8ad2db653f6ac07dcf8bcc05e2409c8bb024aimitakeshi /// 30327ed8ad2db653f6ac07dcf8bcc05e2409c8bb024aimitakeshi virtual MachineInstr * 30427ed8ad2db653f6ac07dcf8bcc05e2409c8bb024aimitakeshi convertToThreeAddress(MachineFunction::iterator &MFI, 30527ed8ad2db653f6ac07dcf8bcc05e2409c8bb024aimitakeshi MachineBasicBlock::iterator &MBBI, LiveVariables &LV) const { 30627ed8ad2db653f6ac07dcf8bcc05e2409c8bb024aimitakeshi return 0; 30727ed8ad2db653f6ac07dcf8bcc05e2409c8bb024aimitakeshi } 30827ed8ad2db653f6ac07dcf8bcc05e2409c8bb024aimitakeshi 30927ed8ad2db653f6ac07dcf8bcc05e2409c8bb024aimitakeshi /// commuteInstruction - If a target has any instructions that are commutable, 31027ed8ad2db653f6ac07dcf8bcc05e2409c8bb024aimitakeshi /// but require converting to a different instruction or making non-trivial 31127ed8ad2db653f6ac07dcf8bcc05e2409c8bb024aimitakeshi /// changes to commute them, this method can overloaded to do this. The 31227ed8ad2db653f6ac07dcf8bcc05e2409c8bb024aimitakeshi /// default implementation of this method simply swaps the first two operands 31327ed8ad2db653f6ac07dcf8bcc05e2409c8bb024aimitakeshi /// of MI and returns it. 31427ed8ad2db653f6ac07dcf8bcc05e2409c8bb024aimitakeshi /// 31527ed8ad2db653f6ac07dcf8bcc05e2409c8bb024aimitakeshi /// If a target wants to make more aggressive changes, they can construct and 31627ed8ad2db653f6ac07dcf8bcc05e2409c8bb024aimitakeshi /// return a new machine instruction. If an instruction cannot commute, it 31727ed8ad2db653f6ac07dcf8bcc05e2409c8bb024aimitakeshi /// can also return null. 31827ed8ad2db653f6ac07dcf8bcc05e2409c8bb024aimitakeshi /// 31927ed8ad2db653f6ac07dcf8bcc05e2409c8bb024aimitakeshi virtual MachineInstr *commuteInstruction(MachineInstr *MI) const; 32027ed8ad2db653f6ac07dcf8bcc05e2409c8bb024aimitakeshi 32127ed8ad2db653f6ac07dcf8bcc05e2409c8bb024aimitakeshi /// AnalyzeBranch - Analyze the branching code at the end of MBB, returning 32227ed8ad2db653f6ac07dcf8bcc05e2409c8bb024aimitakeshi /// true if it cannot be understood (e.g. it's a switch dispatch or isn't 3239d2f386dd2885eaffa11fd494ae258bb09fe6397James Dong /// implemented for a target). Upon success, this returns false and returns 3249d2f386dd2885eaffa11fd494ae258bb09fe6397James Dong /// with the following information in various cases: 32527ed8ad2db653f6ac07dcf8bcc05e2409c8bb024aimitakeshi /// 32627ed8ad2db653f6ac07dcf8bcc05e2409c8bb024aimitakeshi /// 1. If this block ends with no branches (it just falls through to its succ) 32727ed8ad2db653f6ac07dcf8bcc05e2409c8bb024aimitakeshi /// just return false, leaving TBB/FBB null. 32827ed8ad2db653f6ac07dcf8bcc05e2409c8bb024aimitakeshi /// 2. If this block ends with only an unconditional branch, it sets TBB to be 3299d2f386dd2885eaffa11fd494ae258bb09fe6397James Dong /// the destination block. 3309d2f386dd2885eaffa11fd494ae258bb09fe6397James Dong /// 3. If this block ends with an conditional branch, it returns the 'true' 33127ed8ad2db653f6ac07dcf8bcc05e2409c8bb024aimitakeshi /// destination in TBB, the 'false' destination in FBB, and a list of 33227ed8ad2db653f6ac07dcf8bcc05e2409c8bb024aimitakeshi /// operands that evaluate the condition. These operands can be passed to 333e943f84129326ab885cc7a69dcfa17f766b72b89Takeshi Aimi /// other TargetInstrInfo methods to create new branches. 334e943f84129326ab885cc7a69dcfa17f766b72b89Takeshi Aimi /// 335e943f84129326ab885cc7a69dcfa17f766b72b89Takeshi Aimi /// Note that RemoveBranch and InsertBranch must be implemented to support 336e943f84129326ab885cc7a69dcfa17f766b72b89Takeshi Aimi /// cases where this method returns success. 337e943f84129326ab885cc7a69dcfa17f766b72b89Takeshi Aimi /// 3389d2f386dd2885eaffa11fd494ae258bb09fe6397James Dong virtual bool AnalyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB, 3399d2f386dd2885eaffa11fd494ae258bb09fe6397James Dong MachineBasicBlock *&FBB, 340e943f84129326ab885cc7a69dcfa17f766b72b89Takeshi Aimi std::vector<MachineOperand> &Cond) const { 341e943f84129326ab885cc7a69dcfa17f766b72b89Takeshi Aimi return true; 342e943f84129326ab885cc7a69dcfa17f766b72b89Takeshi Aimi } 343e943f84129326ab885cc7a69dcfa17f766b72b89Takeshi Aimi 3449d2f386dd2885eaffa11fd494ae258bb09fe6397James Dong /// RemoveBranch - Remove the branching code at the end of the specific MBB. 3459d2f386dd2885eaffa11fd494ae258bb09fe6397James Dong /// this is only invoked in cases where AnalyzeBranch returns success. 346e943f84129326ab885cc7a69dcfa17f766b72b89Takeshi Aimi virtual void RemoveBranch(MachineBasicBlock &MBB) const { 347e943f84129326ab885cc7a69dcfa17f766b72b89Takeshi Aimi assert(0 && "Target didn't implement TargetInstrInfo::RemoveBranch!"); 34827ed8ad2db653f6ac07dcf8bcc05e2409c8bb024aimitakeshi } 34927ed8ad2db653f6ac07dcf8bcc05e2409c8bb024aimitakeshi 35027ed8ad2db653f6ac07dcf8bcc05e2409c8bb024aimitakeshi /// InsertBranch - Insert a branch into the end of the specified 35127ed8ad2db653f6ac07dcf8bcc05e2409c8bb024aimitakeshi /// MachineBasicBlock. This operands to this method are the same as those 3522272ee27d9022d173b6eab45c409b3c3f57f30ecTakeshi Aimi /// returned by AnalyzeBranch. This is invoked in cases where AnalyzeBranch 3532272ee27d9022d173b6eab45c409b3c3f57f30ecTakeshi Aimi /// returns success and when an unconditional branch (TBB is non-null, FBB is 35427ed8ad2db653f6ac07dcf8bcc05e2409c8bb024aimitakeshi /// null, Cond is empty) needs to be inserted. 3552272ee27d9022d173b6eab45c409b3c3f57f30ecTakeshi Aimi virtual void InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB, 35627ed8ad2db653f6ac07dcf8bcc05e2409c8bb024aimitakeshi MachineBasicBlock *FBB, 35727ed8ad2db653f6ac07dcf8bcc05e2409c8bb024aimitakeshi const std::vector<MachineOperand> &Cond) const { 35827ed8ad2db653f6ac07dcf8bcc05e2409c8bb024aimitakeshi assert(0 && "Target didn't implement TargetInstrInfo::InsertBranch!"); 35927ed8ad2db653f6ac07dcf8bcc05e2409c8bb024aimitakeshi } 36027ed8ad2db653f6ac07dcf8bcc05e2409c8bb024aimitakeshi 36127ed8ad2db653f6ac07dcf8bcc05e2409c8bb024aimitakeshi /// BlockHasNoFallThrough - Return true if the specified block does not 36227ed8ad2db653f6ac07dcf8bcc05e2409c8bb024aimitakeshi /// fall-through into its successor block. This is primarily used when a 36327ed8ad2db653f6ac07dcf8bcc05e2409c8bb024aimitakeshi /// branch is unanalyzable. It is useful for things like unconditional 3642272ee27d9022d173b6eab45c409b3c3f57f30ecTakeshi Aimi /// indirect branches (jump tables). 3652272ee27d9022d173b6eab45c409b3c3f57f30ecTakeshi Aimi virtual bool BlockHasNoFallThrough(MachineBasicBlock &MBB) const { 36627ed8ad2db653f6ac07dcf8bcc05e2409c8bb024aimitakeshi return false; 3672272ee27d9022d173b6eab45c409b3c3f57f30ecTakeshi Aimi } 36827ed8ad2db653f6ac07dcf8bcc05e2409c8bb024aimitakeshi 36927ed8ad2db653f6ac07dcf8bcc05e2409c8bb024aimitakeshi /// ReverseBranchCondition - Reverses the branch condition of the specified 37027ed8ad2db653f6ac07dcf8bcc05e2409c8bb024aimitakeshi /// condition list, returning false on success and true if it cannot be 37127ed8ad2db653f6ac07dcf8bcc05e2409c8bb024aimitakeshi /// reversed. 37227ed8ad2db653f6ac07dcf8bcc05e2409c8bb024aimitakeshi virtual bool ReverseBranchCondition(std::vector<MachineOperand> &Cond) const { 37327ed8ad2db653f6ac07dcf8bcc05e2409c8bb024aimitakeshi return true; 37427ed8ad2db653f6ac07dcf8bcc05e2409c8bb024aimitakeshi } 37527ed8ad2db653f6ac07dcf8bcc05e2409c8bb024aimitakeshi 37627ed8ad2db653f6ac07dcf8bcc05e2409c8bb024aimitakeshi /// insertNoop - Insert a noop into the instruction stream at the specified 37727ed8ad2db653f6ac07dcf8bcc05e2409c8bb024aimitakeshi /// point. 37827ed8ad2db653f6ac07dcf8bcc05e2409c8bb024aimitakeshi virtual void insertNoop(MachineBasicBlock &MBB, 37927ed8ad2db653f6ac07dcf8bcc05e2409c8bb024aimitakeshi MachineBasicBlock::iterator MI) const { 3802272ee27d9022d173b6eab45c409b3c3f57f30ecTakeshi Aimi assert(0 && "Target didn't implement insertNoop!"); 38127ed8ad2db653f6ac07dcf8bcc05e2409c8bb024aimitakeshi abort(); 38227ed8ad2db653f6ac07dcf8bcc05e2409c8bb024aimitakeshi } 38327ed8ad2db653f6ac07dcf8bcc05e2409c8bb024aimitakeshi 38427ed8ad2db653f6ac07dcf8bcc05e2409c8bb024aimitakeshi /// getPointerRegClass - Returns a TargetRegisterClass used for pointer 38527ed8ad2db653f6ac07dcf8bcc05e2409c8bb024aimitakeshi /// values. 38627ed8ad2db653f6ac07dcf8bcc05e2409c8bb024aimitakeshi virtual const TargetRegisterClass *getPointerRegClass() const { 3872272ee27d9022d173b6eab45c409b3c3f57f30ecTakeshi Aimi assert(0 && "Target didn't implement getPointerRegClass!"); 3882272ee27d9022d173b6eab45c409b3c3f57f30ecTakeshi Aimi abort(); 38927ed8ad2db653f6ac07dcf8bcc05e2409c8bb024aimitakeshi } 39027ed8ad2db653f6ac07dcf8bcc05e2409c8bb024aimitakeshi}; 39127ed8ad2db653f6ac07dcf8bcc05e2409c8bb024aimitakeshi 39227ed8ad2db653f6ac07dcf8bcc05e2409c8bb024aimitakeshi} // End llvm namespace 39327ed8ad2db653f6ac07dcf8bcc05e2409c8bb024aimitakeshi 39427ed8ad2db653f6ac07dcf8bcc05e2409c8bb024aimitakeshi#endif 39527ed8ad2db653f6ac07dcf8bcc05e2409c8bb024aimitakeshi