TargetInstrInfo.h revision 23066288fdf4867f53f208f9aaf2952b1c049394
1//===-- llvm/Target/TargetInstrInfo.h - Instruction Info --------*- C++ -*-===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This file describes the target machine instruction set to the code generator. 11// 12//===----------------------------------------------------------------------===// 13 14#ifndef LLVM_TARGET_TARGETINSTRINFO_H 15#define LLVM_TARGET_TARGETINSTRINFO_H 16 17#include "llvm/Target/TargetInstrDesc.h" 18#include "llvm/CodeGen/MachineFunction.h" 19 20namespace llvm { 21 22class TargetRegisterClass; 23class LiveVariables; 24class CalleeSavedInfo; 25class SDNode; 26class SelectionDAG; 27 28template<class T> class SmallVectorImpl; 29 30 31//--------------------------------------------------------------------------- 32/// 33/// TargetInstrInfo - Interface to description of machine instruction set 34/// 35class TargetInstrInfo { 36 const TargetInstrDesc *Descriptors; // Raw array to allow static init'n 37 unsigned NumOpcodes; // Number of entries in the desc array 38 39 TargetInstrInfo(const TargetInstrInfo &); // DO NOT IMPLEMENT 40 void operator=(const TargetInstrInfo &); // DO NOT IMPLEMENT 41public: 42 TargetInstrInfo(const TargetInstrDesc *desc, unsigned NumOpcodes); 43 virtual ~TargetInstrInfo(); 44 45 // Invariant opcodes: All instruction sets have these as their low opcodes. 46 enum { 47 PHI = 0, 48 INLINEASM = 1, 49 DBG_LABEL = 2, 50 EH_LABEL = 3, 51 GC_LABEL = 4, 52 DECLARE = 5, 53 EXTRACT_SUBREG = 6, 54 INSERT_SUBREG = 7, 55 IMPLICIT_DEF = 8, 56 SUBREG_TO_REG = 9 57 }; 58 59 unsigned getNumOpcodes() const { return NumOpcodes; } 60 61 /// get - Return the machine instruction descriptor that corresponds to the 62 /// specified instruction opcode. 63 /// 64 const TargetInstrDesc &get(unsigned Opcode) const { 65 assert(Opcode < NumOpcodes && "Invalid opcode!"); 66 return Descriptors[Opcode]; 67 } 68 69 /// isTriviallyReMaterializable - Return true if the instruction is trivially 70 /// rematerializable, meaning it has no side effects and requires no operands 71 /// that aren't always available. 72 bool isTriviallyReMaterializable(const MachineInstr *MI) const { 73 return MI->getDesc().isRematerializable() && 74 isReallyTriviallyReMaterializable(MI); 75 } 76 77protected: 78 /// isReallyTriviallyReMaterializable - For instructions with opcodes for 79 /// which the M_REMATERIALIZABLE flag is set, this function tests whether the 80 /// instruction itself is actually trivially rematerializable, considering 81 /// its operands. This is used for targets that have instructions that are 82 /// only trivially rematerializable for specific uses. This predicate must 83 /// return false if the instruction has any side effects other than 84 /// producing a value, or if it requres any address registers that are not 85 /// always available. 86 virtual bool isReallyTriviallyReMaterializable(const MachineInstr *MI) const { 87 return true; 88 } 89 90public: 91 /// Return true if the instruction is a register to register move 92 /// and leave the source and dest operands in the passed parameters. 93 virtual bool isMoveInstr(const MachineInstr& MI, 94 unsigned& sourceReg, 95 unsigned& destReg) const { 96 return false; 97 } 98 99 /// isLoadFromStackSlot - If the specified machine instruction is a direct 100 /// load from a stack slot, return the virtual or physical register number of 101 /// the destination along with the FrameIndex of the loaded stack slot. If 102 /// not, return 0. This predicate must return 0 if the instruction has 103 /// any side effects other than loading from the stack slot. 104 virtual unsigned isLoadFromStackSlot(MachineInstr *MI, int &FrameIndex) const{ 105 return 0; 106 } 107 108 /// isStoreToStackSlot - If the specified machine instruction is a direct 109 /// store to a stack slot, return the virtual or physical register number of 110 /// the source reg along with the FrameIndex of the loaded stack slot. If 111 /// not, return 0. This predicate must return 0 if the instruction has 112 /// any side effects other than storing to the stack slot. 113 virtual unsigned isStoreToStackSlot(MachineInstr *MI, int &FrameIndex) const { 114 return 0; 115 } 116 117 /// reMaterialize - Re-issue the specified 'original' instruction at the 118 /// specific location targeting a new destination register. 119 virtual void reMaterialize(MachineBasicBlock &MBB, 120 MachineBasicBlock::iterator MI, 121 unsigned DestReg, 122 const MachineInstr *Orig) const = 0; 123 124 /// isInvariantLoad - Return true if the specified instruction (which is 125 /// marked mayLoad) is loading from a location whose value is invariant across 126 /// the function. For example, loading a value from the constant pool or from 127 /// from the argument area of a function if it does not change. This should 128 /// only return true of *all* loads the instruction does are invariant (if it 129 /// does multiple loads). 130 virtual bool isInvariantLoad(MachineInstr *MI) const { 131 return false; 132 } 133 134 /// convertToThreeAddress - This method must be implemented by targets that 135 /// set the M_CONVERTIBLE_TO_3_ADDR flag. When this flag is set, the target 136 /// may be able to convert a two-address instruction into one or more true 137 /// three-address instructions on demand. This allows the X86 target (for 138 /// example) to convert ADD and SHL instructions into LEA instructions if they 139 /// would require register copies due to two-addressness. 140 /// 141 /// This method returns a null pointer if the transformation cannot be 142 /// performed, otherwise it returns the last new instruction. 143 /// 144 virtual MachineInstr * 145 convertToThreeAddress(MachineFunction::iterator &MFI, 146 MachineBasicBlock::iterator &MBBI, LiveVariables *LV) const { 147 return 0; 148 } 149 150 /// commuteInstruction - If a target has any instructions that are commutable, 151 /// but require converting to a different instruction or making non-trivial 152 /// changes to commute them, this method can overloaded to do this. The 153 /// default implementation of this method simply swaps the first two operands 154 /// of MI and returns it. 155 /// 156 /// If a target wants to make more aggressive changes, they can construct and 157 /// return a new machine instruction. If an instruction cannot commute, it 158 /// can also return null. 159 /// 160 /// If NewMI is true, then a new machine instruction must be created. 161 /// 162 virtual MachineInstr *commuteInstruction(MachineInstr *MI, 163 bool NewMI = false) const = 0; 164 165 /// CommuteChangesDestination - Return true if commuting the specified 166 /// instruction will also changes the destination operand. Also return the 167 /// current operand index of the would be new destination register by 168 /// reference. This can happen when the commutable instruction is also a 169 /// two-address instruction. 170 virtual bool CommuteChangesDestination(MachineInstr *MI, 171 unsigned &OpIdx) const = 0; 172 173 /// AnalyzeBranch - Analyze the branching code at the end of MBB, returning 174 /// true if it cannot be understood (e.g. it's a switch dispatch or isn't 175 /// implemented for a target). Upon success, this returns false and returns 176 /// with the following information in various cases: 177 /// 178 /// 1. If this block ends with no branches (it just falls through to its succ) 179 /// just return false, leaving TBB/FBB null. 180 /// 2. If this block ends with only an unconditional branch, it sets TBB to be 181 /// the destination block. 182 /// 3. If this block ends with an conditional branch and it falls through to 183 /// an successor block, it sets TBB to be the branch destination block and a 184 /// list of operands that evaluate the condition. These 185 /// operands can be passed to other TargetInstrInfo methods to create new 186 /// branches. 187 /// 4. If this block ends with an conditional branch and an unconditional 188 /// block, it returns the 'true' destination in TBB, the 'false' destination 189 /// in FBB, and a list of operands that evaluate the condition. These 190 /// operands can be passed to other TargetInstrInfo methods to create new 191 /// branches. 192 /// 193 /// Note that RemoveBranch and InsertBranch must be implemented to support 194 /// cases where this method returns success. 195 /// 196 virtual bool AnalyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB, 197 MachineBasicBlock *&FBB, 198 SmallVectorImpl<MachineOperand> &Cond) const { 199 return true; 200 } 201 202 /// RemoveBranch - Remove the branching code at the end of the specific MBB. 203 /// This is only invoked in cases where AnalyzeBranch returns success. It 204 /// returns the number of instructions that were removed. 205 virtual unsigned RemoveBranch(MachineBasicBlock &MBB) const { 206 assert(0 && "Target didn't implement TargetInstrInfo::RemoveBranch!"); 207 return 0; 208 } 209 210 /// InsertBranch - Insert a branch into the end of the specified 211 /// MachineBasicBlock. This operands to this method are the same as those 212 /// returned by AnalyzeBranch. This is invoked in cases where AnalyzeBranch 213 /// returns success and when an unconditional branch (TBB is non-null, FBB is 214 /// null, Cond is empty) needs to be inserted. It returns the number of 215 /// instructions inserted. 216 virtual unsigned InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB, 217 MachineBasicBlock *FBB, 218 const SmallVectorImpl<MachineOperand> &Cond) const { 219 assert(0 && "Target didn't implement TargetInstrInfo::InsertBranch!"); 220 return 0; 221 } 222 223 /// copyRegToReg - Emit instructions to copy between a pair of registers. It 224 /// returns false if the target does not how to copy between the specified 225 /// registers. 226 virtual bool copyRegToReg(MachineBasicBlock &MBB, 227 MachineBasicBlock::iterator MI, 228 unsigned DestReg, unsigned SrcReg, 229 const TargetRegisterClass *DestRC, 230 const TargetRegisterClass *SrcRC) const { 231 assert(0 && "Target didn't implement TargetInstrInfo::copyRegToReg!"); 232 return false; 233 } 234 235 /// storeRegToStackSlot - Store the specified register of the given register 236 /// class to the specified stack frame index. The store instruction is to be 237 /// added to the given machine basic block before the specified machine 238 /// instruction. If isKill is true, the register operand is the last use and 239 /// must be marked kill. 240 virtual void storeRegToStackSlot(MachineBasicBlock &MBB, 241 MachineBasicBlock::iterator MI, 242 unsigned SrcReg, bool isKill, int FrameIndex, 243 const TargetRegisterClass *RC) const { 244 assert(0 && "Target didn't implement TargetInstrInfo::storeRegToStackSlot!"); 245 } 246 247 /// storeRegToAddr - Store the specified register of the given register class 248 /// to the specified address. The store instruction is to be added to the 249 /// given machine basic block before the specified machine instruction. If 250 /// isKill is true, the register operand is the last use and must be marked 251 /// kill. 252 virtual void storeRegToAddr(MachineFunction &MF, unsigned SrcReg, bool isKill, 253 SmallVectorImpl<MachineOperand> &Addr, 254 const TargetRegisterClass *RC, 255 SmallVectorImpl<MachineInstr*> &NewMIs) const { 256 assert(0 && "Target didn't implement TargetInstrInfo::storeRegToAddr!"); 257 } 258 259 /// loadRegFromStackSlot - Load the specified register of the given register 260 /// class from the specified stack frame index. The load instruction is to be 261 /// added to the given machine basic block before the specified machine 262 /// instruction. 263 virtual void loadRegFromStackSlot(MachineBasicBlock &MBB, 264 MachineBasicBlock::iterator MI, 265 unsigned DestReg, int FrameIndex, 266 const TargetRegisterClass *RC) const { 267 assert(0 && "Target didn't implement TargetInstrInfo::loadRegFromStackSlot!"); 268 } 269 270 /// loadRegFromAddr - Load the specified register of the given register class 271 /// class from the specified address. The load instruction is to be added to 272 /// the given machine basic block before the specified machine instruction. 273 virtual void loadRegFromAddr(MachineFunction &MF, unsigned DestReg, 274 SmallVectorImpl<MachineOperand> &Addr, 275 const TargetRegisterClass *RC, 276 SmallVectorImpl<MachineInstr*> &NewMIs) const { 277 assert(0 && "Target didn't implement TargetInstrInfo::loadRegFromAddr!"); 278 } 279 280 /// spillCalleeSavedRegisters - Issues instruction(s) to spill all callee 281 /// saved registers and returns true if it isn't possible / profitable to do 282 /// so by issuing a series of store instructions via 283 /// storeRegToStackSlot(). Returns false otherwise. 284 virtual bool spillCalleeSavedRegisters(MachineBasicBlock &MBB, 285 MachineBasicBlock::iterator MI, 286 const std::vector<CalleeSavedInfo> &CSI) const { 287 return false; 288 } 289 290 /// restoreCalleeSavedRegisters - Issues instruction(s) to restore all callee 291 /// saved registers and returns true if it isn't possible / profitable to do 292 /// so by issuing a series of load instructions via loadRegToStackSlot(). 293 /// Returns false otherwise. 294 virtual bool restoreCalleeSavedRegisters(MachineBasicBlock &MBB, 295 MachineBasicBlock::iterator MI, 296 const std::vector<CalleeSavedInfo> &CSI) const { 297 return false; 298 } 299 300 /// foldMemoryOperand - Attempt to fold a load or store of the specified stack 301 /// slot into the specified machine instruction for the specified operand(s). 302 /// If this is possible, a new instruction is returned with the specified 303 /// operand folded, otherwise NULL is returned. The client is responsible for 304 /// removing the old instruction and adding the new one in the instruction 305 /// stream. 306 virtual MachineInstr* foldMemoryOperand(MachineFunction &MF, 307 MachineInstr* MI, 308 const SmallVectorImpl<unsigned> &Ops, 309 int FrameIndex) const { 310 return 0; 311 } 312 313 /// foldMemoryOperand - Same as the previous version except it allows folding 314 /// of any load and store from / to any address, not just from a specific 315 /// stack slot. 316 virtual MachineInstr* foldMemoryOperand(MachineFunction &MF, 317 MachineInstr* MI, 318 const SmallVectorImpl<unsigned> &Ops, 319 MachineInstr* LoadMI) const { 320 return 0; 321 } 322 323 /// canFoldMemoryOperand - Returns true if the specified load / store is 324 /// folding is possible. 325 virtual 326 bool canFoldMemoryOperand(const MachineInstr *MI, 327 const SmallVectorImpl<unsigned> &Ops) const { 328 return false; 329 } 330 331 /// unfoldMemoryOperand - Separate a single instruction which folded a load or 332 /// a store or a load and a store into two or more instruction. If this is 333 /// possible, returns true as well as the new instructions by reference. 334 virtual bool unfoldMemoryOperand(MachineFunction &MF, MachineInstr *MI, 335 unsigned Reg, bool UnfoldLoad, bool UnfoldStore, 336 SmallVectorImpl<MachineInstr*> &NewMIs) const{ 337 return false; 338 } 339 340 virtual bool unfoldMemoryOperand(SelectionDAG &DAG, SDNode *N, 341 SmallVectorImpl<SDNode*> &NewNodes) const { 342 return false; 343 } 344 345 /// getOpcodeAfterMemoryUnfold - Returns the opcode of the would be new 346 /// instruction after load / store are unfolded from an instruction of the 347 /// specified opcode. It returns zero if the specified unfolding is not 348 /// possible. 349 virtual unsigned getOpcodeAfterMemoryUnfold(unsigned Opc, 350 bool UnfoldLoad, bool UnfoldStore) const { 351 return 0; 352 } 353 354 /// BlockHasNoFallThrough - Return true if the specified block does not 355 /// fall-through into its successor block. This is primarily used when a 356 /// branch is unanalyzable. It is useful for things like unconditional 357 /// indirect branches (jump tables). 358 virtual bool BlockHasNoFallThrough(const MachineBasicBlock &MBB) const { 359 return false; 360 } 361 362 /// ReverseBranchCondition - Reverses the branch condition of the specified 363 /// condition list, returning false on success and true if it cannot be 364 /// reversed. 365 virtual 366 bool ReverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const { 367 return true; 368 } 369 370 /// insertNoop - Insert a noop into the instruction stream at the specified 371 /// point. 372 virtual void insertNoop(MachineBasicBlock &MBB, 373 MachineBasicBlock::iterator MI) const { 374 assert(0 && "Target didn't implement insertNoop!"); 375 abort(); 376 } 377 378 /// isPredicated - Returns true if the instruction is already predicated. 379 /// 380 virtual bool isPredicated(const MachineInstr *MI) const { 381 return false; 382 } 383 384 /// isUnpredicatedTerminator - Returns true if the instruction is a 385 /// terminator instruction that has not been predicated. 386 virtual bool isUnpredicatedTerminator(const MachineInstr *MI) const; 387 388 /// PredicateInstruction - Convert the instruction into a predicated 389 /// instruction. It returns true if the operation was successful. 390 virtual 391 bool PredicateInstruction(MachineInstr *MI, 392 const SmallVectorImpl<MachineOperand> &Pred) const = 0; 393 394 /// SubsumesPredicate - Returns true if the first specified predicate 395 /// subsumes the second, e.g. GE subsumes GT. 396 virtual 397 bool SubsumesPredicate(const SmallVectorImpl<MachineOperand> &Pred1, 398 const SmallVectorImpl<MachineOperand> &Pred2) const { 399 return false; 400 } 401 402 /// DefinesPredicate - If the specified instruction defines any predicate 403 /// or condition code register(s) used for predication, returns true as well 404 /// as the definition predicate(s) by reference. 405 virtual bool DefinesPredicate(MachineInstr *MI, 406 std::vector<MachineOperand> &Pred) const { 407 return false; 408 } 409 410 /// IgnoreRegisterClassBarriers - Returns true if pre-register allocation 411 /// live interval splitting pass should ignore barriers of the specified 412 /// register class. 413 virtual bool IgnoreRegisterClassBarriers(const TargetRegisterClass *RC) const{ 414 return true; 415 } 416 417 /// getPointerRegClass - Returns a TargetRegisterClass used for pointer 418 /// values. 419 virtual const TargetRegisterClass *getPointerRegClass() const { 420 assert(0 && "Target didn't implement getPointerRegClass!"); 421 abort(); 422 return 0; // Must return a value in order to compile with VS 2005 423 } 424 425 /// GetInstSize - Returns the size of the specified Instruction. 426 /// 427 virtual unsigned GetInstSizeInBytes(const MachineInstr *MI) const { 428 assert(0 && "Target didn't implement TargetInstrInfo::GetInstSize!"); 429 return 0; 430 } 431 432 /// GetFunctionSizeInBytes - Returns the size of the specified MachineFunction. 433 /// 434 virtual unsigned GetFunctionSizeInBytes(const MachineFunction &MF) const = 0; 435}; 436 437/// TargetInstrInfoImpl - This is the default implementation of 438/// TargetInstrInfo, which just provides a couple of default implementations 439/// for various methods. This separated out because it is implemented in 440/// libcodegen, not in libtarget. 441class TargetInstrInfoImpl : public TargetInstrInfo { 442protected: 443 TargetInstrInfoImpl(const TargetInstrDesc *desc, unsigned NumOpcodes) 444 : TargetInstrInfo(desc, NumOpcodes) {} 445public: 446 virtual MachineInstr *commuteInstruction(MachineInstr *MI, 447 bool NewMI = false) const; 448 virtual bool CommuteChangesDestination(MachineInstr *MI, 449 unsigned &OpIdx) const; 450 virtual bool PredicateInstruction(MachineInstr *MI, 451 const SmallVectorImpl<MachineOperand> &Pred) const; 452 virtual void reMaterialize(MachineBasicBlock &MBB, 453 MachineBasicBlock::iterator MI, 454 unsigned DestReg, 455 const MachineInstr *Orig) const; 456 virtual unsigned GetFunctionSizeInBytes(const MachineFunction &MF) const; 457}; 458 459} // End llvm namespace 460 461#endif 462