TargetInstrInfo.h revision 24321d7e23a482cbd0b7502f43e9026f87a3684d
1//===-- llvm/Target/TargetInstrInfo.h - Instruction Info --------*- C++ -*-===//
2//
3//                     The LLVM Compiler Infrastructure
4//
5// This file was developed by the LLVM research group and is distributed under
6// the University of Illinois Open Source License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10// This file describes the target machine instructions to the code generator.
11//
12//===----------------------------------------------------------------------===//
13
14#ifndef LLVM_TARGET_TARGETINSTRINFO_H
15#define LLVM_TARGET_TARGETINSTRINFO_H
16
17#include "llvm/CodeGen/MachineBasicBlock.h"
18#include "llvm/Support/DataTypes.h"
19#include <vector>
20#include <cassert>
21
22namespace llvm {
23
24class MachineInstr;
25class TargetMachine;
26class Value;
27class Type;
28class Instruction;
29class Constant;
30class Function;
31class MachineCodeForInstruction;
32class TargetRegisterClass;
33
34//---------------------------------------------------------------------------
35// Data types used to define information about a single machine instruction
36//---------------------------------------------------------------------------
37
38typedef short MachineOpCode;
39typedef unsigned InstrSchedClass;
40
41//---------------------------------------------------------------------------
42// struct TargetInstrDescriptor:
43//  Predefined information about each machine instruction.
44//  Designed to initialized statically.
45//
46
47const unsigned M_BRANCH_FLAG           = 1 << 0;
48const unsigned M_CALL_FLAG             = 1 << 1;
49const unsigned M_RET_FLAG              = 1 << 2;
50const unsigned M_BARRIER_FLAG          = 1 << 3;
51const unsigned M_DELAY_SLOT_FLAG       = 1 << 4;
52const unsigned M_LOAD_FLAG             = 1 << 5;
53const unsigned M_STORE_FLAG            = 1 << 6;
54
55// M_2_ADDR_FLAG - 3-addr instructions which really work like 2-addr ones.
56const unsigned M_2_ADDR_FLAG           = 1 << 7;
57
58// M_CONVERTIBLE_TO_3_ADDR - This is a M_2_ADDR_FLAG instruction which can be
59// changed into a 3-address instruction if the first two operands cannot be
60// assigned to the same register.  The target must implement the
61// TargetInstrInfo::convertToThreeAddress method for this instruction.
62const unsigned M_CONVERTIBLE_TO_3_ADDR = 1 << 8;
63
64// This M_COMMUTABLE - is a 2- or 3-address instruction (of the form X = op Y,
65// Z), which produces the same result if Y and Z are exchanged.
66const unsigned M_COMMUTABLE            = 1 << 9;
67
68// M_TERMINATOR_FLAG - Is this instruction part of the terminator for a basic
69// block?  Typically this is things like return and branch instructions.
70// Various passes use this to insert code into the bottom of a basic block, but
71// before control flow occurs.
72const unsigned M_TERMINATOR_FLAG       = 1 << 10;
73
74// M_USES_CUSTOM_DAG_SCHED_INSERTION - Set if this instruction requires custom
75// insertion support when the DAG scheduler is inserting it into a machine basic
76// block.
77const unsigned M_USES_CUSTOM_DAG_SCHED_INSERTION = 1 << 11;
78
79// M_VARIABLE_OPS - Set if this instruction can have a variable number of extra
80// operands in addition to the minimum number operands specified.
81const unsigned M_VARIABLE_OPS = 1 << 12;
82
83// Machine operand flags
84// M_LOOK_UP_PTR_REG_CLASS - Set if this operand is a pointer value and it
85// requires a callback to look up its register class.
86const unsigned M_LOOK_UP_PTR_REG_CLASS = 1 << 0;
87
88/// TargetOperandInfo - This holds information about one operand of a machine
89/// instruction, indicating the register class for register operands, etc.
90///
91class TargetOperandInfo {
92public:
93  /// RegClass - This specifies the register class enumeration of the operand
94  /// if the operand is a register.  If not, this contains 0.
95  unsigned short RegClass;
96  unsigned short Flags;
97  /// Currently no other information.
98};
99
100
101class TargetInstrDescriptor {
102public:
103  const char *    Name;          // Assembly language mnemonic for the opcode.
104  unsigned        numOperands;   // Num of args (may be more if variable_ops).
105  InstrSchedClass schedClass;    // enum  identifying instr sched class
106  unsigned        Flags;         // flags identifying machine instr class
107  unsigned        TSFlags;       // Target Specific Flag values
108  const unsigned *ImplicitUses;  // Registers implicitly read by this instr
109  const unsigned *ImplicitDefs;  // Registers implicitly defined by this instr
110  const TargetOperandInfo *OpInfo; // 'numOperands' entries about operands.
111};
112
113
114//---------------------------------------------------------------------------
115///
116/// TargetInstrInfo - Interface to description of machine instructions
117///
118class TargetInstrInfo {
119  const TargetInstrDescriptor* desc;    // raw array to allow static init'n
120  unsigned NumOpcodes;                  // number of entries in the desc array
121  unsigned numRealOpCodes;              // number of non-dummy op codes
122
123  TargetInstrInfo(const TargetInstrInfo &);  // DO NOT IMPLEMENT
124  void operator=(const TargetInstrInfo &);   // DO NOT IMPLEMENT
125public:
126  TargetInstrInfo(const TargetInstrDescriptor *desc, unsigned NumOpcodes);
127  virtual ~TargetInstrInfo();
128
129  // Invariant opcodes: All instruction sets have these as their low opcodes.
130  enum {
131    PHI = 0,
132    INLINEASM = 1
133  };
134
135  unsigned getNumOpcodes() const { return NumOpcodes; }
136
137  /// get - Return the machine instruction descriptor that corresponds to the
138  /// specified instruction opcode.
139  ///
140  const TargetInstrDescriptor& get(MachineOpCode Opcode) const {
141    assert((unsigned)Opcode < NumOpcodes);
142    return desc[Opcode];
143  }
144
145  const char *getName(MachineOpCode Opcode) const {
146    return get(Opcode).Name;
147  }
148
149  int getNumOperands(MachineOpCode Opcode) const {
150    return get(Opcode).numOperands;
151  }
152
153  InstrSchedClass getSchedClass(MachineOpCode Opcode) const {
154    return get(Opcode).schedClass;
155  }
156
157  const unsigned *getImplicitUses(MachineOpCode Opcode) const {
158    return get(Opcode).ImplicitUses;
159  }
160
161  const unsigned *getImplicitDefs(MachineOpCode Opcode) const {
162    return get(Opcode).ImplicitDefs;
163  }
164
165
166  //
167  // Query instruction class flags according to the machine-independent
168  // flags listed above.
169  //
170  bool isReturn(MachineOpCode Opcode) const {
171    return get(Opcode).Flags & M_RET_FLAG;
172  }
173
174  bool isTwoAddrInstr(MachineOpCode Opcode) const {
175    return get(Opcode).Flags & M_2_ADDR_FLAG;
176  }
177  bool isCommutableInstr(MachineOpCode Opcode) const {
178    return get(Opcode).Flags & M_COMMUTABLE;
179  }
180  bool isTerminatorInstr(unsigned Opcode) const {
181    return get(Opcode).Flags & M_TERMINATOR_FLAG;
182  }
183
184  bool isBranch(MachineOpCode Opcode) const {
185    return get(Opcode).Flags & M_BRANCH_FLAG;
186  }
187
188  /// isBarrier - Returns true if the specified instruction stops control flow
189  /// from executing the instruction immediately following it.  Examples include
190  /// unconditional branches and return instructions.
191  bool isBarrier(MachineOpCode Opcode) const {
192    return get(Opcode).Flags & M_BARRIER_FLAG;
193  }
194
195  bool isCall(MachineOpCode Opcode) const {
196    return get(Opcode).Flags & M_CALL_FLAG;
197  }
198  bool isLoad(MachineOpCode Opcode) const {
199    return get(Opcode).Flags & M_LOAD_FLAG;
200  }
201  bool isStore(MachineOpCode Opcode) const {
202    return get(Opcode).Flags & M_STORE_FLAG;
203  }
204
205  /// hasDelaySlot - Returns true if the specified instruction has a delay slot
206  /// which must be filled by the code generator.
207  bool hasDelaySlot(unsigned Opcode) const {
208    return get(Opcode).Flags & M_DELAY_SLOT_FLAG;
209  }
210
211  /// usesCustomDAGSchedInsertionHook - Return true if this instruction requires
212  /// custom insertion support when the DAG scheduler is inserting it into a
213  /// machine basic block.
214  bool usesCustomDAGSchedInsertionHook(unsigned Opcode) const {
215    return get(Opcode).Flags & M_USES_CUSTOM_DAG_SCHED_INSERTION;
216  }
217
218  bool hasVariableOperands(MachineOpCode Opcode) const {
219    return get(Opcode).Flags & M_VARIABLE_OPS;
220  }
221
222  /// getDWARF_LABELOpcode - Return the opcode of the target's DWARF_LABEL
223  /// instruction if it has one.  This is used by codegen passes that update
224  /// DWARF line number info as they modify the code.
225  virtual unsigned getDWARF_LABELOpcode() const {
226    return 0;
227  }
228
229  /// Return true if the instruction is a register to register move
230  /// and leave the source and dest operands in the passed parameters.
231  virtual bool isMoveInstr(const MachineInstr& MI,
232                           unsigned& sourceReg,
233                           unsigned& destReg) const {
234    return false;
235  }
236
237  /// isLoadFromStackSlot - If the specified machine instruction is a direct
238  /// load from a stack slot, return the virtual or physical register number of
239  /// the destination along with the FrameIndex of the loaded stack slot.  If
240  /// not, return 0.  This predicate must return 0 if the instruction has
241  /// any side effects other than loading from the stack slot.
242  virtual unsigned isLoadFromStackSlot(MachineInstr *MI, int &FrameIndex) const{
243    return 0;
244  }
245
246  /// isStoreToStackSlot - If the specified machine instruction is a direct
247  /// store to a stack slot, return the virtual or physical register number of
248  /// the source reg along with the FrameIndex of the loaded stack slot.  If
249  /// not, return 0.  This predicate must return 0 if the instruction has
250  /// any side effects other than storing to the stack slot.
251  virtual unsigned isStoreToStackSlot(MachineInstr *MI, int &FrameIndex) const {
252    return 0;
253  }
254
255  /// convertToThreeAddress - This method must be implemented by targets that
256  /// set the M_CONVERTIBLE_TO_3_ADDR flag.  When this flag is set, the target
257  /// may be able to convert a two-address instruction into a true
258  /// three-address instruction on demand.  This allows the X86 target (for
259  /// example) to convert ADD and SHL instructions into LEA instructions if they
260  /// would require register copies due to two-addressness.
261  ///
262  /// This method returns a null pointer if the transformation cannot be
263  /// performed, otherwise it returns the new instruction.
264  ///
265  virtual MachineInstr *convertToThreeAddress(MachineInstr *TA) const {
266    return 0;
267  }
268
269  /// commuteInstruction - If a target has any instructions that are commutable,
270  /// but require converting to a different instruction or making non-trivial
271  /// changes to commute them, this method can overloaded to do this.  The
272  /// default implementation of this method simply swaps the first two operands
273  /// of MI and returns it.
274  ///
275  /// If a target wants to make more aggressive changes, they can construct and
276  /// return a new machine instruction.  If an instruction cannot commute, it
277  /// can also return null.
278  ///
279  virtual MachineInstr *commuteInstruction(MachineInstr *MI) const;
280
281  /// AnalyzeBranch - Analyze the branching code at the end of MBB, returning
282  /// true if it cannot be understood (e.g. it's a switch dispatch or isn't
283  /// implemented for a target).  Upon success, this returns false and returns
284  /// with the following information in various cases:
285  ///
286  /// 1. If this block ends with no branches (it just falls through to its succ)
287  ///    just return false, leaving TBB/FBB null.
288  /// 2. If this block ends with only an unconditional branch, it sets TBB to be
289  ///    the destination block.
290  /// 3. If this block ends with an conditional branch, it returns the 'true'
291  ///    destination in TBB, the 'false' destination in FBB, and a list of
292  ///    operands that evaluate the condition.  These operands can be passed to
293  ///    other TargetInstrInfo methods to create new branches.
294  ///
295  /// Note that RemoveBranch and InsertBranch must be implemented to support
296  /// cases where this method returns success.
297  ///
298  virtual bool AnalyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB,
299                             MachineBasicBlock *&FBB,
300                             std::vector<MachineOperand> &Cond) const {
301    return true;
302  }
303
304  /// RemoveBranch - Remove the branching code at the end of the specific MBB.
305  /// this is only invoked in cases where AnalyzeBranch returns success.
306  virtual void RemoveBranch(MachineBasicBlock &MBB) const {
307    assert(0 && "Target didn't implement TargetInstrInfo::RemoveBranch!");
308  }
309
310  /// InsertBranch - Insert a branch into the end of the specified
311  /// MachineBasicBlock.  This operands to this method are the same as those
312  /// returned by AnalyzeBranch.  This nis invoked in cases where AnalyzeBranch
313  /// returns success.
314  virtual void InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB,
315                            MachineBasicBlock *FBB,
316                            const std::vector<MachineOperand> &Cond) const {
317    assert(0 && "Target didn't implement TargetInstrInfo::InsertBranch!");
318  }
319
320  /// ReverseBranchCondition - Reverses the branch condition of the specified
321  /// condition list, returning false on success and true if it cannot be
322  /// reversed.
323  virtual bool ReverseBranchCondition(std::vector<MachineOperand> &Cond) const {
324    return true;
325  }
326
327  /// insertNoop - Insert a noop into the instruction stream at the specified
328  /// point.
329  virtual void insertNoop(MachineBasicBlock &MBB,
330                          MachineBasicBlock::iterator MI) const {
331    assert(0 && "Target didn't implement insertNoop!");
332    abort();
333  }
334
335  /// getPointerRegClass - Returns a TargetRegisterClass used for pointer
336  /// values.
337  virtual const TargetRegisterClass *getPointerRegClass() const {
338    assert(0 && "Target didn't implement getPointerRegClass!");
339    abort();
340  }
341};
342
343} // End llvm namespace
344
345#endif
346