TargetInstrInfo.h revision 243a32f96b364811e2f9feadecfefb21b640321f
1//===-- llvm/Target/TargetInstrInfo.h - Instruction Info --------*- C++ -*-===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This file describes the target machine instruction set to the code generator. 11// 12//===----------------------------------------------------------------------===// 13 14#ifndef LLVM_TARGET_TARGETINSTRINFO_H 15#define LLVM_TARGET_TARGETINSTRINFO_H 16 17#include "llvm/Target/TargetInstrDesc.h" 18#include "llvm/CodeGen/MachineFunction.h" 19 20namespace llvm { 21 22class MCAsmInfo; 23class TargetRegisterClass; 24class TargetRegisterInfo; 25class LiveVariables; 26class CalleeSavedInfo; 27class SDNode; 28class SelectionDAG; 29class MachineMemOperand; 30 31template<class T> class SmallVectorImpl; 32 33 34//--------------------------------------------------------------------------- 35/// 36/// TargetInstrInfo - Interface to description of machine instruction set 37/// 38class TargetInstrInfo { 39 const TargetInstrDesc *Descriptors; // Raw array to allow static init'n 40 unsigned NumOpcodes; // Number of entries in the desc array 41 42 TargetInstrInfo(const TargetInstrInfo &); // DO NOT IMPLEMENT 43 void operator=(const TargetInstrInfo &); // DO NOT IMPLEMENT 44public: 45 TargetInstrInfo(const TargetInstrDesc *desc, unsigned NumOpcodes); 46 virtual ~TargetInstrInfo(); 47 48 // Invariant opcodes: All instruction sets have these as their low opcodes. 49 enum { 50 PHI = 0, 51 INLINEASM = 1, 52 DBG_LABEL = 2, 53 EH_LABEL = 3, 54 GC_LABEL = 4, 55 56 /// KILL - This instruction is a noop that is used only to adjust the liveness 57 /// of registers. This can be useful when dealing with sub-registers. 58 KILL = 5, 59 60 /// EXTRACT_SUBREG - This instruction takes two operands: a register 61 /// that has subregisters, and a subregister index. It returns the 62 /// extracted subregister value. This is commonly used to implement 63 /// truncation operations on target architectures which support it. 64 EXTRACT_SUBREG = 6, 65 66 /// INSERT_SUBREG - This instruction takes three operands: a register 67 /// that has subregisters, a register providing an insert value, and a 68 /// subregister index. It returns the value of the first register with 69 /// the value of the second register inserted. The first register is 70 /// often defined by an IMPLICIT_DEF, as is commonly used to implement 71 /// anyext operations on target architectures which support it. 72 INSERT_SUBREG = 7, 73 74 /// IMPLICIT_DEF - This is the MachineInstr-level equivalent of undef. 75 IMPLICIT_DEF = 8, 76 77 /// SUBREG_TO_REG - This instruction is similar to INSERT_SUBREG except 78 /// that the first operand is an immediate integer constant. This constant 79 /// is often zero, as is commonly used to implement zext operations on 80 /// target architectures which support it, such as with x86-64 (with 81 /// zext from i32 to i64 via implicit zero-extension). 82 SUBREG_TO_REG = 9, 83 84 /// COPY_TO_REGCLASS - This instruction is a placeholder for a plain 85 /// register-to-register copy into a specific register class. This is only 86 /// used between instruction selection and MachineInstr creation, before 87 /// virtual registers have been created for all the instructions, and it's 88 /// only needed in cases where the register classes implied by the 89 /// instructions are insufficient. The actual MachineInstrs to perform 90 /// the copy are emitted with the TargetInstrInfo::copyRegToReg hook. 91 COPY_TO_REGCLASS = 10, 92 93 // DEBUG_VALUE - a mapping of the llvm.dbg.value intrinsic 94 DEBUG_VALUE = 11 95 }; 96 97 unsigned getNumOpcodes() const { return NumOpcodes; } 98 99 /// get - Return the machine instruction descriptor that corresponds to the 100 /// specified instruction opcode. 101 /// 102 const TargetInstrDesc &get(unsigned Opcode) const { 103 assert(Opcode < NumOpcodes && "Invalid opcode!"); 104 return Descriptors[Opcode]; 105 } 106 107 /// isTriviallyReMaterializable - Return true if the instruction is trivially 108 /// rematerializable, meaning it has no side effects and requires no operands 109 /// that aren't always available. 110 bool isTriviallyReMaterializable(const MachineInstr *MI, 111 AliasAnalysis *AA = 0) const { 112 return MI->getOpcode() == IMPLICIT_DEF || 113 (MI->getDesc().isRematerializable() && 114 (isReallyTriviallyReMaterializable(MI, AA) || 115 isReallyTriviallyReMaterializableGeneric(MI, AA))); 116 } 117 118protected: 119 /// isReallyTriviallyReMaterializable - For instructions with opcodes for 120 /// which the M_REMATERIALIZABLE flag is set, this hook lets the target 121 /// specify whether the instruction is actually trivially rematerializable, 122 /// taking into consideration its operands. This predicate must return false 123 /// if the instruction has any side effects other than producing a value, or 124 /// if it requres any address registers that are not always available. 125 virtual bool isReallyTriviallyReMaterializable(const MachineInstr *MI, 126 AliasAnalysis *AA) const { 127 return false; 128 } 129 130private: 131 /// isReallyTriviallyReMaterializableGeneric - For instructions with opcodes 132 /// for which the M_REMATERIALIZABLE flag is set and the target hook 133 /// isReallyTriviallyReMaterializable returns false, this function does 134 /// target-independent tests to determine if the instruction is really 135 /// trivially rematerializable. 136 bool isReallyTriviallyReMaterializableGeneric(const MachineInstr *MI, 137 AliasAnalysis *AA) const; 138 139public: 140 /// isMoveInstr - Return true if the instruction is a register to register 141 /// move and return the source and dest operands and their sub-register 142 /// indices by reference. 143 virtual bool isMoveInstr(const MachineInstr& MI, 144 unsigned& SrcReg, unsigned& DstReg, 145 unsigned& SrcSubIdx, unsigned& DstSubIdx) const { 146 return false; 147 } 148 149 /// isCoalescableExtInstr - Return true if the instruction is a "coalescable" 150 /// extension instruction. That is, it's like a copy where it's legal for the 151 /// source to overlap the destination. e.g. X86::MOVSX64rr32. If this returns 152 /// true, then it's expected the pre-extension value is available as a subreg 153 /// of the result register. This also returns the sub-register index in 154 /// SubIdx. 155 virtual bool isCoalescableExtInstr(const MachineInstr &MI, 156 unsigned &SrcReg, unsigned &DstReg, 157 unsigned &SubIdx) const { 158 return false; 159 } 160 161 /// isIdentityCopy - Return true if the instruction is a copy (or 162 /// extract_subreg, insert_subreg, subreg_to_reg) where the source and 163 /// destination registers are the same. 164 bool isIdentityCopy(const MachineInstr &MI) const { 165 unsigned SrcReg, DstReg, SrcSubIdx, DstSubIdx; 166 if (isMoveInstr(MI, SrcReg, DstReg, SrcSubIdx, DstSubIdx) && 167 SrcReg == DstReg) 168 return true; 169 170 if (MI.getOpcode() == TargetInstrInfo::EXTRACT_SUBREG && 171 MI.getOperand(0).getReg() == MI.getOperand(1).getReg()) 172 return true; 173 174 if ((MI.getOpcode() == TargetInstrInfo::INSERT_SUBREG || 175 MI.getOpcode() == TargetInstrInfo::SUBREG_TO_REG) && 176 MI.getOperand(0).getReg() == MI.getOperand(2).getReg()) 177 return true; 178 return false; 179 } 180 181 /// isLoadFromStackSlot - If the specified machine instruction is a direct 182 /// load from a stack slot, return the virtual or physical register number of 183 /// the destination along with the FrameIndex of the loaded stack slot. If 184 /// not, return 0. This predicate must return 0 if the instruction has 185 /// any side effects other than loading from the stack slot. 186 virtual unsigned isLoadFromStackSlot(const MachineInstr *MI, 187 int &FrameIndex) const { 188 return 0; 189 } 190 191 /// isLoadFromStackSlotPostFE - Check for post-frame ptr elimination 192 /// stack locations as well. This uses a heuristic so it isn't 193 /// reliable for correctness. 194 virtual unsigned isLoadFromStackSlotPostFE(const MachineInstr *MI, 195 int &FrameIndex) const { 196 return 0; 197 } 198 199 /// hasLoadFromStackSlot - If the specified machine instruction has 200 /// a load from a stack slot, return true along with the FrameIndex 201 /// of the loaded stack slot and the machine mem operand containing 202 /// the reference. If not, return false. Unlike 203 /// isLoadFromStackSlot, this returns true for any instructions that 204 /// loads from the stack. This is just a hint, as some cases may be 205 /// missed. 206 virtual bool hasLoadFromStackSlot(const MachineInstr *MI, 207 const MachineMemOperand *&MMO, 208 int &FrameIndex) const { 209 return 0; 210 } 211 212 /// isStoreToStackSlot - If the specified machine instruction is a direct 213 /// store to a stack slot, return the virtual or physical register number of 214 /// the source reg along with the FrameIndex of the loaded stack slot. If 215 /// not, return 0. This predicate must return 0 if the instruction has 216 /// any side effects other than storing to the stack slot. 217 virtual unsigned isStoreToStackSlot(const MachineInstr *MI, 218 int &FrameIndex) const { 219 return 0; 220 } 221 222 /// isStoreToStackSlotPostFE - Check for post-frame ptr elimination 223 /// stack locations as well. This uses a heuristic so it isn't 224 /// reliable for correctness. 225 virtual unsigned isStoreToStackSlotPostFE(const MachineInstr *MI, 226 int &FrameIndex) const { 227 return 0; 228 } 229 230 /// hasStoreToStackSlot - If the specified machine instruction has a 231 /// store to a stack slot, return true along with the FrameIndex of 232 /// the loaded stack slot and the machine mem operand containing the 233 /// reference. If not, return false. Unlike isStoreToStackSlot, 234 /// this returns true for any instructions that loads from the 235 /// stack. This is just a hint, as some cases may be missed. 236 virtual bool hasStoreToStackSlot(const MachineInstr *MI, 237 const MachineMemOperand *&MMO, 238 int &FrameIndex) const { 239 return 0; 240 } 241 242 /// reMaterialize - Re-issue the specified 'original' instruction at the 243 /// specific location targeting a new destination register. 244 virtual void reMaterialize(MachineBasicBlock &MBB, 245 MachineBasicBlock::iterator MI, 246 unsigned DestReg, unsigned SubIdx, 247 const MachineInstr *Orig, 248 const TargetRegisterInfo *TRI) const = 0; 249 250 /// duplicate - Create a duplicate of the Orig instruction in MF. This is like 251 /// MachineFunction::CloneMachineInstr(), but the target may update operands 252 /// that are required to be unique. 253 /// 254 /// The instruction must be duplicable as indicated by isNotDuplicable(). 255 virtual MachineInstr *duplicate(MachineInstr *Orig, 256 MachineFunction &MF) const = 0; 257 258 /// convertToThreeAddress - This method must be implemented by targets that 259 /// set the M_CONVERTIBLE_TO_3_ADDR flag. When this flag is set, the target 260 /// may be able to convert a two-address instruction into one or more true 261 /// three-address instructions on demand. This allows the X86 target (for 262 /// example) to convert ADD and SHL instructions into LEA instructions if they 263 /// would require register copies due to two-addressness. 264 /// 265 /// This method returns a null pointer if the transformation cannot be 266 /// performed, otherwise it returns the last new instruction. 267 /// 268 virtual MachineInstr * 269 convertToThreeAddress(MachineFunction::iterator &MFI, 270 MachineBasicBlock::iterator &MBBI, LiveVariables *LV) const { 271 return 0; 272 } 273 274 /// commuteInstruction - If a target has any instructions that are commutable, 275 /// but require converting to a different instruction or making non-trivial 276 /// changes to commute them, this method can overloaded to do this. The 277 /// default implementation of this method simply swaps the first two operands 278 /// of MI and returns it. 279 /// 280 /// If a target wants to make more aggressive changes, they can construct and 281 /// return a new machine instruction. If an instruction cannot commute, it 282 /// can also return null. 283 /// 284 /// If NewMI is true, then a new machine instruction must be created. 285 /// 286 virtual MachineInstr *commuteInstruction(MachineInstr *MI, 287 bool NewMI = false) const = 0; 288 289 /// findCommutedOpIndices - If specified MI is commutable, return the two 290 /// operand indices that would swap value. Return true if the instruction 291 /// is not in a form which this routine understands. 292 virtual bool findCommutedOpIndices(MachineInstr *MI, unsigned &SrcOpIdx1, 293 unsigned &SrcOpIdx2) const = 0; 294 295 /// isIdentical - Return true if two instructions are identical. This differs 296 /// from MachineInstr::isIdenticalTo() in that it does not require the 297 /// virtual destination registers to be the same. This is used by MachineLICM 298 /// and other MI passes to perform CSE. 299 virtual bool isIdentical(const MachineInstr *MI, 300 const MachineInstr *Other, 301 const MachineRegisterInfo *MRI) const = 0; 302 303 /// AnalyzeBranch - Analyze the branching code at the end of MBB, returning 304 /// true if it cannot be understood (e.g. it's a switch dispatch or isn't 305 /// implemented for a target). Upon success, this returns false and returns 306 /// with the following information in various cases: 307 /// 308 /// 1. If this block ends with no branches (it just falls through to its succ) 309 /// just return false, leaving TBB/FBB null. 310 /// 2. If this block ends with only an unconditional branch, it sets TBB to be 311 /// the destination block. 312 /// 3. If this block ends with a conditional branch and it falls through to a 313 /// successor block, it sets TBB to be the branch destination block and a 314 /// list of operands that evaluate the condition. These operands can be 315 /// passed to other TargetInstrInfo methods to create new branches. 316 /// 4. If this block ends with a conditional branch followed by an 317 /// unconditional branch, it returns the 'true' destination in TBB, the 318 /// 'false' destination in FBB, and a list of operands that evaluate the 319 /// condition. These operands can be passed to other TargetInstrInfo 320 /// methods to create new branches. 321 /// 322 /// Note that RemoveBranch and InsertBranch must be implemented to support 323 /// cases where this method returns success. 324 /// 325 /// If AllowModify is true, then this routine is allowed to modify the basic 326 /// block (e.g. delete instructions after the unconditional branch). 327 /// 328 virtual bool AnalyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB, 329 MachineBasicBlock *&FBB, 330 SmallVectorImpl<MachineOperand> &Cond, 331 bool AllowModify = false) const { 332 return true; 333 } 334 335 /// RemoveBranch - Remove the branching code at the end of the specific MBB. 336 /// This is only invoked in cases where AnalyzeBranch returns success. It 337 /// returns the number of instructions that were removed. 338 virtual unsigned RemoveBranch(MachineBasicBlock &MBB) const { 339 assert(0 && "Target didn't implement TargetInstrInfo::RemoveBranch!"); 340 return 0; 341 } 342 343 /// InsertBranch - Insert branch code into the end of the specified 344 /// MachineBasicBlock. The operands to this method are the same as those 345 /// returned by AnalyzeBranch. This is only invoked in cases where 346 /// AnalyzeBranch returns success. It returns the number of instructions 347 /// inserted. 348 /// 349 /// It is also invoked by tail merging to add unconditional branches in 350 /// cases where AnalyzeBranch doesn't apply because there was no original 351 /// branch to analyze. At least this much must be implemented, else tail 352 /// merging needs to be disabled. 353 virtual unsigned InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB, 354 MachineBasicBlock *FBB, 355 const SmallVectorImpl<MachineOperand> &Cond) const { 356 assert(0 && "Target didn't implement TargetInstrInfo::InsertBranch!"); 357 return 0; 358 } 359 360 /// copyRegToReg - Emit instructions to copy between a pair of registers. It 361 /// returns false if the target does not how to copy between the specified 362 /// registers. 363 virtual bool copyRegToReg(MachineBasicBlock &MBB, 364 MachineBasicBlock::iterator MI, 365 unsigned DestReg, unsigned SrcReg, 366 const TargetRegisterClass *DestRC, 367 const TargetRegisterClass *SrcRC) const { 368 assert(0 && "Target didn't implement TargetInstrInfo::copyRegToReg!"); 369 return false; 370 } 371 372 /// storeRegToStackSlot - Store the specified register of the given register 373 /// class to the specified stack frame index. The store instruction is to be 374 /// added to the given machine basic block before the specified machine 375 /// instruction. If isKill is true, the register operand is the last use and 376 /// must be marked kill. 377 virtual void storeRegToStackSlot(MachineBasicBlock &MBB, 378 MachineBasicBlock::iterator MI, 379 unsigned SrcReg, bool isKill, int FrameIndex, 380 const TargetRegisterClass *RC) const { 381 assert(0 && "Target didn't implement TargetInstrInfo::storeRegToStackSlot!"); 382 } 383 384 /// loadRegFromStackSlot - Load the specified register of the given register 385 /// class from the specified stack frame index. The load instruction is to be 386 /// added to the given machine basic block before the specified machine 387 /// instruction. 388 virtual void loadRegFromStackSlot(MachineBasicBlock &MBB, 389 MachineBasicBlock::iterator MI, 390 unsigned DestReg, int FrameIndex, 391 const TargetRegisterClass *RC) const { 392 assert(0 && "Target didn't implement TargetInstrInfo::loadRegFromStackSlot!"); 393 } 394 395 /// spillCalleeSavedRegisters - Issues instruction(s) to spill all callee 396 /// saved registers and returns true if it isn't possible / profitable to do 397 /// so by issuing a series of store instructions via 398 /// storeRegToStackSlot(). Returns false otherwise. 399 virtual bool spillCalleeSavedRegisters(MachineBasicBlock &MBB, 400 MachineBasicBlock::iterator MI, 401 const std::vector<CalleeSavedInfo> &CSI) const { 402 return false; 403 } 404 405 /// restoreCalleeSavedRegisters - Issues instruction(s) to restore all callee 406 /// saved registers and returns true if it isn't possible / profitable to do 407 /// so by issuing a series of load instructions via loadRegToStackSlot(). 408 /// Returns false otherwise. 409 virtual bool restoreCalleeSavedRegisters(MachineBasicBlock &MBB, 410 MachineBasicBlock::iterator MI, 411 const std::vector<CalleeSavedInfo> &CSI) const { 412 return false; 413 } 414 415 /// foldMemoryOperand - Attempt to fold a load or store of the specified stack 416 /// slot into the specified machine instruction for the specified operand(s). 417 /// If this is possible, a new instruction is returned with the specified 418 /// operand folded, otherwise NULL is returned. The client is responsible for 419 /// removing the old instruction and adding the new one in the instruction 420 /// stream. 421 MachineInstr* foldMemoryOperand(MachineFunction &MF, 422 MachineInstr* MI, 423 const SmallVectorImpl<unsigned> &Ops, 424 int FrameIndex) const; 425 426 /// foldMemoryOperand - Same as the previous version except it allows folding 427 /// of any load and store from / to any address, not just from a specific 428 /// stack slot. 429 MachineInstr* foldMemoryOperand(MachineFunction &MF, 430 MachineInstr* MI, 431 const SmallVectorImpl<unsigned> &Ops, 432 MachineInstr* LoadMI) const; 433 434protected: 435 /// foldMemoryOperandImpl - Target-dependent implementation for 436 /// foldMemoryOperand. Target-independent code in foldMemoryOperand will 437 /// take care of adding a MachineMemOperand to the newly created instruction. 438 virtual MachineInstr* foldMemoryOperandImpl(MachineFunction &MF, 439 MachineInstr* MI, 440 const SmallVectorImpl<unsigned> &Ops, 441 int FrameIndex) const { 442 return 0; 443 } 444 445 /// foldMemoryOperandImpl - Target-dependent implementation for 446 /// foldMemoryOperand. Target-independent code in foldMemoryOperand will 447 /// take care of adding a MachineMemOperand to the newly created instruction. 448 virtual MachineInstr* foldMemoryOperandImpl(MachineFunction &MF, 449 MachineInstr* MI, 450 const SmallVectorImpl<unsigned> &Ops, 451 MachineInstr* LoadMI) const { 452 return 0; 453 } 454 455public: 456 /// canFoldMemoryOperand - Returns true for the specified load / store if 457 /// folding is possible. 458 virtual 459 bool canFoldMemoryOperand(const MachineInstr *MI, 460 const SmallVectorImpl<unsigned> &Ops) const { 461 return false; 462 } 463 464 /// unfoldMemoryOperand - Separate a single instruction which folded a load or 465 /// a store or a load and a store into two or more instruction. If this is 466 /// possible, returns true as well as the new instructions by reference. 467 virtual bool unfoldMemoryOperand(MachineFunction &MF, MachineInstr *MI, 468 unsigned Reg, bool UnfoldLoad, bool UnfoldStore, 469 SmallVectorImpl<MachineInstr*> &NewMIs) const{ 470 return false; 471 } 472 473 virtual bool unfoldMemoryOperand(SelectionDAG &DAG, SDNode *N, 474 SmallVectorImpl<SDNode*> &NewNodes) const { 475 return false; 476 } 477 478 /// getOpcodeAfterMemoryUnfold - Returns the opcode of the would be new 479 /// instruction after load / store are unfolded from an instruction of the 480 /// specified opcode. It returns zero if the specified unfolding is not 481 /// possible. If LoadRegIndex is non-null, it is filled in with the operand 482 /// index of the operand which will hold the register holding the loaded 483 /// value. 484 virtual unsigned getOpcodeAfterMemoryUnfold(unsigned Opc, 485 bool UnfoldLoad, bool UnfoldStore, 486 unsigned *LoadRegIndex = 0) const { 487 return 0; 488 } 489 490 /// ReverseBranchCondition - Reverses the branch condition of the specified 491 /// condition list, returning false on success and true if it cannot be 492 /// reversed. 493 virtual 494 bool ReverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const { 495 return true; 496 } 497 498 /// insertNoop - Insert a noop into the instruction stream at the specified 499 /// point. 500 virtual void insertNoop(MachineBasicBlock &MBB, 501 MachineBasicBlock::iterator MI) const; 502 503 /// isPredicated - Returns true if the instruction is already predicated. 504 /// 505 virtual bool isPredicated(const MachineInstr *MI) const { 506 return false; 507 } 508 509 /// isUnpredicatedTerminator - Returns true if the instruction is a 510 /// terminator instruction that has not been predicated. 511 virtual bool isUnpredicatedTerminator(const MachineInstr *MI) const; 512 513 /// PredicateInstruction - Convert the instruction into a predicated 514 /// instruction. It returns true if the operation was successful. 515 virtual 516 bool PredicateInstruction(MachineInstr *MI, 517 const SmallVectorImpl<MachineOperand> &Pred) const = 0; 518 519 /// SubsumesPredicate - Returns true if the first specified predicate 520 /// subsumes the second, e.g. GE subsumes GT. 521 virtual 522 bool SubsumesPredicate(const SmallVectorImpl<MachineOperand> &Pred1, 523 const SmallVectorImpl<MachineOperand> &Pred2) const { 524 return false; 525 } 526 527 /// DefinesPredicate - If the specified instruction defines any predicate 528 /// or condition code register(s) used for predication, returns true as well 529 /// as the definition predicate(s) by reference. 530 virtual bool DefinesPredicate(MachineInstr *MI, 531 std::vector<MachineOperand> &Pred) const { 532 return false; 533 } 534 535 /// isPredicable - Return true if the specified instruction can be predicated. 536 /// By default, this returns true for every instruction with a 537 /// PredicateOperand. 538 virtual bool isPredicable(MachineInstr *MI) const { 539 return MI->getDesc().isPredicable(); 540 } 541 542 /// isSafeToMoveRegClassDefs - Return true if it's safe to move a machine 543 /// instruction that defines the specified register class. 544 virtual bool isSafeToMoveRegClassDefs(const TargetRegisterClass *RC) const { 545 return true; 546 } 547 548 /// GetInstSize - Returns the size of the specified Instruction. 549 /// 550 virtual unsigned GetInstSizeInBytes(const MachineInstr *MI) const { 551 assert(0 && "Target didn't implement TargetInstrInfo::GetInstSize!"); 552 return 0; 553 } 554 555 /// GetFunctionSizeInBytes - Returns the size of the specified 556 /// MachineFunction. 557 /// 558 virtual unsigned GetFunctionSizeInBytes(const MachineFunction &MF) const = 0; 559 560 /// Measure the specified inline asm to determine an approximation of its 561 /// length. 562 virtual unsigned getInlineAsmLength(const char *Str, 563 const MCAsmInfo &MAI) const; 564}; 565 566/// TargetInstrInfoImpl - This is the default implementation of 567/// TargetInstrInfo, which just provides a couple of default implementations 568/// for various methods. This separated out because it is implemented in 569/// libcodegen, not in libtarget. 570class TargetInstrInfoImpl : public TargetInstrInfo { 571protected: 572 TargetInstrInfoImpl(const TargetInstrDesc *desc, unsigned NumOpcodes) 573 : TargetInstrInfo(desc, NumOpcodes) {} 574public: 575 virtual MachineInstr *commuteInstruction(MachineInstr *MI, 576 bool NewMI = false) const; 577 virtual bool findCommutedOpIndices(MachineInstr *MI, unsigned &SrcOpIdx1, 578 unsigned &SrcOpIdx2) const; 579 virtual bool PredicateInstruction(MachineInstr *MI, 580 const SmallVectorImpl<MachineOperand> &Pred) const; 581 virtual void reMaterialize(MachineBasicBlock &MBB, 582 MachineBasicBlock::iterator MI, 583 unsigned DestReg, unsigned SubReg, 584 const MachineInstr *Orig, 585 const TargetRegisterInfo *TRI) const; 586 virtual MachineInstr *duplicate(MachineInstr *Orig, 587 MachineFunction &MF) const; 588 virtual bool isIdentical(const MachineInstr *MI, 589 const MachineInstr *Other, 590 const MachineRegisterInfo *MRI) const; 591 592 virtual unsigned GetFunctionSizeInBytes(const MachineFunction &MF) const; 593}; 594 595} // End llvm namespace 596 597#endif 598