TargetInstrInfo.h revision 33247d537ddce29e65bc324bf8d40a15d2d88c01
1//===-- llvm/Target/TargetInstrInfo.h - Instruction Info --------*- C++ -*-===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file was developed by the LLVM research group and is distributed under 6// the University of Illinois Open Source License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This file describes the target machine instructions to the code generator. 11// 12//===----------------------------------------------------------------------===// 13 14#ifndef LLVM_TARGET_TARGETINSTRINFO_H 15#define LLVM_TARGET_TARGETINSTRINFO_H 16 17#include "llvm/CodeGen/MachineBasicBlock.h" 18#include "llvm/Support/DataTypes.h" 19#include <vector> 20#include <cassert> 21 22namespace llvm { 23 24class MachineInstr; 25class TargetMachine; 26class Value; 27class Type; 28class Instruction; 29class Constant; 30class Function; 31class MachineCodeForInstruction; 32class TargetRegisterClass; 33 34//--------------------------------------------------------------------------- 35// Data types used to define information about a single machine instruction 36//--------------------------------------------------------------------------- 37 38typedef short MachineOpCode; 39typedef unsigned InstrSchedClass; 40 41//--------------------------------------------------------------------------- 42// struct TargetInstrDescriptor: 43// Predefined information about each machine instruction. 44// Designed to initialized statically. 45// 46 47const unsigned M_BRANCH_FLAG = 1 << 0; 48const unsigned M_CALL_FLAG = 1 << 1; 49const unsigned M_RET_FLAG = 1 << 2; 50const unsigned M_BARRIER_FLAG = 1 << 3; 51const unsigned M_DELAY_SLOT_FLAG = 1 << 4; 52const unsigned M_LOAD_FLAG = 1 << 5; 53const unsigned M_STORE_FLAG = 1 << 6; 54 55// M_CONVERTIBLE_TO_3_ADDR - This is a 2-address instruction which can be 56// changed into a 3-address instruction if the first two operands cannot be 57// assigned to the same register. The target must implement the 58// TargetInstrInfo::convertToThreeAddress method for this instruction. 59const unsigned M_CONVERTIBLE_TO_3_ADDR = 1 << 7; 60 61// This M_COMMUTABLE - is a 2- or 3-address instruction (of the form X = op Y, 62// Z), which produces the same result if Y and Z are exchanged. 63const unsigned M_COMMUTABLE = 1 << 8; 64 65// M_TERMINATOR_FLAG - Is this instruction part of the terminator for a basic 66// block? Typically this is things like return and branch instructions. 67// Various passes use this to insert code into the bottom of a basic block, but 68// before control flow occurs. 69const unsigned M_TERMINATOR_FLAG = 1 << 9; 70 71// M_USES_CUSTOM_DAG_SCHED_INSERTION - Set if this instruction requires custom 72// insertion support when the DAG scheduler is inserting it into a machine basic 73// block. 74const unsigned M_USES_CUSTOM_DAG_SCHED_INSERTION = 1 << 10; 75 76// M_VARIABLE_OPS - Set if this instruction can have a variable number of extra 77// operands in addition to the minimum number operands specified. 78const unsigned M_VARIABLE_OPS = 1 << 11; 79 80// M_PREDICATED - Set if this instruction has a predicate that controls its 81// execution. 82const unsigned M_PREDICATED = 1 << 12; 83 84 85// Machine operand flags 86// M_LOOK_UP_PTR_REG_CLASS - Set if this operand is a pointer value and it 87// requires a callback to look up its register class. 88const unsigned M_LOOK_UP_PTR_REG_CLASS = 1 << 0; 89 90/// M_PREDICATE_OPERAND - Set if this is the first operand of a predicate 91/// operand that controls an M_PREDICATED instruction. 92const unsigned M_PREDICATE_OPERAND = 1 << 1; 93 94 95/// TargetOperandInfo - This holds information about one operand of a machine 96/// instruction, indicating the register class for register operands, etc. 97/// 98class TargetOperandInfo { 99public: 100 /// RegClass - This specifies the register class enumeration of the operand 101 /// if the operand is a register. If not, this contains 0. 102 unsigned short RegClass; 103 unsigned short Flags; 104 /// Lower 16 bits are used to specify which constraints are set. The higher 16 105 /// bits are used to specify the value of constraints (4 bits each). 106 unsigned int Constraints; 107 /// Currently no other information. 108}; 109 110 111class TargetInstrDescriptor { 112public: 113 MachineOpCode Opcode; // The opcode. 114 unsigned short numOperands; // Num of args (may be more if variable_ops). 115 const char * Name; // Assembly language mnemonic for the opcode. 116 InstrSchedClass schedClass; // enum identifying instr sched class 117 unsigned Flags; // flags identifying machine instr class 118 unsigned TSFlags; // Target Specific Flag values 119 const unsigned *ImplicitUses; // Registers implicitly read by this instr 120 const unsigned *ImplicitDefs; // Registers implicitly defined by this instr 121 const TargetOperandInfo *OpInfo; // 'numOperands' entries about operands. 122}; 123 124 125//--------------------------------------------------------------------------- 126/// 127/// TargetInstrInfo - Interface to description of machine instructions 128/// 129class TargetInstrInfo { 130 const TargetInstrDescriptor* desc; // raw array to allow static init'n 131 unsigned NumOpcodes; // number of entries in the desc array 132 unsigned numRealOpCodes; // number of non-dummy op codes 133 134 TargetInstrInfo(const TargetInstrInfo &); // DO NOT IMPLEMENT 135 void operator=(const TargetInstrInfo &); // DO NOT IMPLEMENT 136public: 137 TargetInstrInfo(const TargetInstrDescriptor *desc, unsigned NumOpcodes); 138 virtual ~TargetInstrInfo(); 139 140 // Invariant opcodes: All instruction sets have these as their low opcodes. 141 enum { 142 PHI = 0, 143 INLINEASM = 1 144 }; 145 146 unsigned getNumOpcodes() const { return NumOpcodes; } 147 148 /// get - Return the machine instruction descriptor that corresponds to the 149 /// specified instruction opcode. 150 /// 151 const TargetInstrDescriptor& get(MachineOpCode Opcode) const { 152 assert((unsigned)Opcode < NumOpcodes); 153 return desc[Opcode]; 154 } 155 156 const char *getName(MachineOpCode Opcode) const { 157 return get(Opcode).Name; 158 } 159 160 int getNumOperands(MachineOpCode Opcode) const { 161 return get(Opcode).numOperands; 162 } 163 164 InstrSchedClass getSchedClass(MachineOpCode Opcode) const { 165 return get(Opcode).schedClass; 166 } 167 168 const unsigned *getImplicitUses(MachineOpCode Opcode) const { 169 return get(Opcode).ImplicitUses; 170 } 171 172 const unsigned *getImplicitDefs(MachineOpCode Opcode) const { 173 return get(Opcode).ImplicitDefs; 174 } 175 176 177 // 178 // Query instruction class flags according to the machine-independent 179 // flags listed above. 180 // 181 bool isReturn(MachineOpCode Opcode) const { 182 return get(Opcode).Flags & M_RET_FLAG; 183 } 184 185 bool isPredicated(MachineOpCode Opcode) const { 186 return get(Opcode).Flags & M_PREDICATED; 187 } 188 bool isCommutableInstr(MachineOpCode Opcode) const { 189 return get(Opcode).Flags & M_COMMUTABLE; 190 } 191 bool isTerminatorInstr(unsigned Opcode) const { 192 return get(Opcode).Flags & M_TERMINATOR_FLAG; 193 } 194 195 bool isBranch(MachineOpCode Opcode) const { 196 return get(Opcode).Flags & M_BRANCH_FLAG; 197 } 198 199 /// isBarrier - Returns true if the specified instruction stops control flow 200 /// from executing the instruction immediately following it. Examples include 201 /// unconditional branches and return instructions. 202 bool isBarrier(MachineOpCode Opcode) const { 203 return get(Opcode).Flags & M_BARRIER_FLAG; 204 } 205 206 bool isCall(MachineOpCode Opcode) const { 207 return get(Opcode).Flags & M_CALL_FLAG; 208 } 209 bool isLoad(MachineOpCode Opcode) const { 210 return get(Opcode).Flags & M_LOAD_FLAG; 211 } 212 bool isStore(MachineOpCode Opcode) const { 213 return get(Opcode).Flags & M_STORE_FLAG; 214 } 215 216 /// hasDelaySlot - Returns true if the specified instruction has a delay slot 217 /// which must be filled by the code generator. 218 bool hasDelaySlot(unsigned Opcode) const { 219 return get(Opcode).Flags & M_DELAY_SLOT_FLAG; 220 } 221 222 /// usesCustomDAGSchedInsertionHook - Return true if this instruction requires 223 /// custom insertion support when the DAG scheduler is inserting it into a 224 /// machine basic block. 225 bool usesCustomDAGSchedInsertionHook(unsigned Opcode) const { 226 return get(Opcode).Flags & M_USES_CUSTOM_DAG_SCHED_INSERTION; 227 } 228 229 bool hasVariableOperands(MachineOpCode Opcode) const { 230 return get(Opcode).Flags & M_VARIABLE_OPS; 231 } 232 233 // Operand constraints: only "tied_to" for now. 234 enum OperandConstraint { 235 TIED_TO = 0 // Must be allocated the same register as. 236 }; 237 238 /// getOperandConstraint - Returns the value of the specific constraint if 239 /// it is set. Returns -1 if it is not set. 240 int getOperandConstraint(MachineOpCode Opcode, unsigned OpNum, 241 OperandConstraint Constraint) const { 242 assert(OpNum < get(Opcode).numOperands && 243 "Invalid operand # of TargetInstrInfo"); 244 if (get(Opcode).OpInfo[OpNum].Constraints & (1 << Constraint)) { 245 unsigned Pos = 16 + Constraint * 4; 246 return (int)(get(Opcode).OpInfo[OpNum].Constraints >> Pos) & 0xf; 247 } 248 return -1; 249 } 250 251 /// findTiedToSrcOperand - Returns the operand that is tied to the specified 252 /// dest operand. Returns -1 if there isn't one. 253 int findTiedToSrcOperand(MachineOpCode Opcode, unsigned OpNum) const; 254 255 /// getDWARF_LABELOpcode - Return the opcode of the target's DWARF_LABEL 256 /// instruction if it has one. This is used by codegen passes that update 257 /// DWARF line number info as they modify the code. 258 virtual unsigned getDWARF_LABELOpcode() const { 259 return 0; 260 } 261 262 /// Return true if the instruction is a register to register move 263 /// and leave the source and dest operands in the passed parameters. 264 virtual bool isMoveInstr(const MachineInstr& MI, 265 unsigned& sourceReg, 266 unsigned& destReg) const { 267 return false; 268 } 269 270 /// isLoadFromStackSlot - If the specified machine instruction is a direct 271 /// load from a stack slot, return the virtual or physical register number of 272 /// the destination along with the FrameIndex of the loaded stack slot. If 273 /// not, return 0. This predicate must return 0 if the instruction has 274 /// any side effects other than loading from the stack slot. 275 virtual unsigned isLoadFromStackSlot(MachineInstr *MI, int &FrameIndex) const{ 276 return 0; 277 } 278 279 /// isStoreToStackSlot - If the specified machine instruction is a direct 280 /// store to a stack slot, return the virtual or physical register number of 281 /// the source reg along with the FrameIndex of the loaded stack slot. If 282 /// not, return 0. This predicate must return 0 if the instruction has 283 /// any side effects other than storing to the stack slot. 284 virtual unsigned isStoreToStackSlot(MachineInstr *MI, int &FrameIndex) const { 285 return 0; 286 } 287 288 /// convertToThreeAddress - This method must be implemented by targets that 289 /// set the M_CONVERTIBLE_TO_3_ADDR flag. When this flag is set, the target 290 /// may be able to convert a two-address instruction into a true 291 /// three-address instruction on demand. This allows the X86 target (for 292 /// example) to convert ADD and SHL instructions into LEA instructions if they 293 /// would require register copies due to two-addressness. 294 /// 295 /// This method returns a null pointer if the transformation cannot be 296 /// performed, otherwise it returns the new instruction. 297 /// 298 virtual MachineInstr *convertToThreeAddress(MachineInstr *TA) const { 299 return 0; 300 } 301 302 /// commuteInstruction - If a target has any instructions that are commutable, 303 /// but require converting to a different instruction or making non-trivial 304 /// changes to commute them, this method can overloaded to do this. The 305 /// default implementation of this method simply swaps the first two operands 306 /// of MI and returns it. 307 /// 308 /// If a target wants to make more aggressive changes, they can construct and 309 /// return a new machine instruction. If an instruction cannot commute, it 310 /// can also return null. 311 /// 312 virtual MachineInstr *commuteInstruction(MachineInstr *MI) const; 313 314 /// AnalyzeBranch - Analyze the branching code at the end of MBB, returning 315 /// true if it cannot be understood (e.g. it's a switch dispatch or isn't 316 /// implemented for a target). Upon success, this returns false and returns 317 /// with the following information in various cases: 318 /// 319 /// 1. If this block ends with no branches (it just falls through to its succ) 320 /// just return false, leaving TBB/FBB null. 321 /// 2. If this block ends with only an unconditional branch, it sets TBB to be 322 /// the destination block. 323 /// 3. If this block ends with an conditional branch, it returns the 'true' 324 /// destination in TBB, the 'false' destination in FBB, and a list of 325 /// operands that evaluate the condition. These operands can be passed to 326 /// other TargetInstrInfo methods to create new branches. 327 /// 328 /// Note that RemoveBranch and InsertBranch must be implemented to support 329 /// cases where this method returns success. 330 /// 331 virtual bool AnalyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB, 332 MachineBasicBlock *&FBB, 333 std::vector<MachineOperand> &Cond) const { 334 return true; 335 } 336 337 /// RemoveBranch - Remove the branching code at the end of the specific MBB. 338 /// this is only invoked in cases where AnalyzeBranch returns success. 339 virtual void RemoveBranch(MachineBasicBlock &MBB) const { 340 assert(0 && "Target didn't implement TargetInstrInfo::RemoveBranch!"); 341 } 342 343 /// InsertBranch - Insert a branch into the end of the specified 344 /// MachineBasicBlock. This operands to this method are the same as those 345 /// returned by AnalyzeBranch. This is invoked in cases where AnalyzeBranch 346 /// returns success and when an unconditional branch (TBB is non-null, FBB is 347 /// null, Cond is empty) needs to be inserted. 348 virtual void InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB, 349 MachineBasicBlock *FBB, 350 const std::vector<MachineOperand> &Cond) const { 351 assert(0 && "Target didn't implement TargetInstrInfo::InsertBranch!"); 352 } 353 354 /// BlockHasNoFallThrough - Return true if the specified block does not 355 /// fall-through into its successor block. This is primarily used when a 356 /// branch is unanalyzable. It is useful for things like unconditional 357 /// indirect branches (jump tables). 358 virtual bool BlockHasNoFallThrough(MachineBasicBlock &MBB) const { 359 return false; 360 } 361 362 /// ReverseBranchCondition - Reverses the branch condition of the specified 363 /// condition list, returning false on success and true if it cannot be 364 /// reversed. 365 virtual bool ReverseBranchCondition(std::vector<MachineOperand> &Cond) const { 366 return true; 367 } 368 369 /// insertNoop - Insert a noop into the instruction stream at the specified 370 /// point. 371 virtual void insertNoop(MachineBasicBlock &MBB, 372 MachineBasicBlock::iterator MI) const { 373 assert(0 && "Target didn't implement insertNoop!"); 374 abort(); 375 } 376 377 /// getPointerRegClass - Returns a TargetRegisterClass used for pointer 378 /// values. 379 virtual const TargetRegisterClass *getPointerRegClass() const { 380 assert(0 && "Target didn't implement getPointerRegClass!"); 381 abort(); 382 } 383}; 384 385} // End llvm namespace 386 387#endif 388