TargetInstrInfo.h revision 4db3cffe94a5285239cc0056f939c6b74a5ca0b6
1//===-- llvm/Target/TargetInstrInfo.h - Instruction Info --------*- C++ -*-===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This file describes the target machine instruction set to the code generator. 11// 12//===----------------------------------------------------------------------===// 13 14#ifndef LLVM_TARGET_TARGETINSTRINFO_H 15#define LLVM_TARGET_TARGETINSTRINFO_H 16 17#include "llvm/MC/MCInstrInfo.h" 18#include "llvm/CodeGen/MachineFunction.h" 19 20namespace llvm { 21 22class InstrItineraryData; 23class LiveVariables; 24class MCAsmInfo; 25class MachineMemOperand; 26class MachineRegisterInfo; 27class MDNode; 28class MCInst; 29class SDNode; 30class ScheduleHazardRecognizer; 31class SelectionDAG; 32class ScheduleDAG; 33class TargetRegisterClass; 34class TargetRegisterInfo; 35 36template<class T> class SmallVectorImpl; 37 38 39//--------------------------------------------------------------------------- 40/// 41/// TargetInstrInfo - Interface to description of machine instruction set 42/// 43class TargetInstrInfo : public MCInstrInfo { 44 TargetInstrInfo(const TargetInstrInfo &); // DO NOT IMPLEMENT 45 void operator=(const TargetInstrInfo &); // DO NOT IMPLEMENT 46public: 47 TargetInstrInfo(int CFSetupOpcode = -1, int CFDestroyOpcode = -1) 48 : CallFrameSetupOpcode(CFSetupOpcode), 49 CallFrameDestroyOpcode(CFDestroyOpcode) { 50 } 51 52 virtual ~TargetInstrInfo(); 53 54 /// getRegClass - Givem a machine instruction descriptor, returns the register 55 /// class constraint for OpNum, or NULL. 56 const TargetRegisterClass *getRegClass(const MCInstrDesc &TID, 57 unsigned OpNum, 58 const TargetRegisterInfo *TRI) const; 59 60 /// isTriviallyReMaterializable - Return true if the instruction is trivially 61 /// rematerializable, meaning it has no side effects and requires no operands 62 /// that aren't always available. 63 bool isTriviallyReMaterializable(const MachineInstr *MI, 64 AliasAnalysis *AA = 0) const { 65 return MI->getOpcode() == TargetOpcode::IMPLICIT_DEF || 66 (MI->getDesc().isRematerializable() && 67 (isReallyTriviallyReMaterializable(MI, AA) || 68 isReallyTriviallyReMaterializableGeneric(MI, AA))); 69 } 70 71protected: 72 /// isReallyTriviallyReMaterializable - For instructions with opcodes for 73 /// which the M_REMATERIALIZABLE flag is set, this hook lets the target 74 /// specify whether the instruction is actually trivially rematerializable, 75 /// taking into consideration its operands. This predicate must return false 76 /// if the instruction has any side effects other than producing a value, or 77 /// if it requres any address registers that are not always available. 78 virtual bool isReallyTriviallyReMaterializable(const MachineInstr *MI, 79 AliasAnalysis *AA) const { 80 return false; 81 } 82 83private: 84 /// isReallyTriviallyReMaterializableGeneric - For instructions with opcodes 85 /// for which the M_REMATERIALIZABLE flag is set and the target hook 86 /// isReallyTriviallyReMaterializable returns false, this function does 87 /// target-independent tests to determine if the instruction is really 88 /// trivially rematerializable. 89 bool isReallyTriviallyReMaterializableGeneric(const MachineInstr *MI, 90 AliasAnalysis *AA) const; 91 92public: 93 /// getCallFrameSetup/DestroyOpcode - These methods return the opcode of the 94 /// frame setup/destroy instructions if they exist (-1 otherwise). Some 95 /// targets use pseudo instructions in order to abstract away the difference 96 /// between operating with a frame pointer and operating without, through the 97 /// use of these two instructions. 98 /// 99 int getCallFrameSetupOpcode() const { return CallFrameSetupOpcode; } 100 int getCallFrameDestroyOpcode() const { return CallFrameDestroyOpcode; } 101 102 /// isCoalescableExtInstr - Return true if the instruction is a "coalescable" 103 /// extension instruction. That is, it's like a copy where it's legal for the 104 /// source to overlap the destination. e.g. X86::MOVSX64rr32. If this returns 105 /// true, then it's expected the pre-extension value is available as a subreg 106 /// of the result register. This also returns the sub-register index in 107 /// SubIdx. 108 virtual bool isCoalescableExtInstr(const MachineInstr &MI, 109 unsigned &SrcReg, unsigned &DstReg, 110 unsigned &SubIdx) const { 111 return false; 112 } 113 114 /// isLoadFromStackSlot - If the specified machine instruction is a direct 115 /// load from a stack slot, return the virtual or physical register number of 116 /// the destination along with the FrameIndex of the loaded stack slot. If 117 /// not, return 0. This predicate must return 0 if the instruction has 118 /// any side effects other than loading from the stack slot. 119 virtual unsigned isLoadFromStackSlot(const MachineInstr *MI, 120 int &FrameIndex) const { 121 return 0; 122 } 123 124 /// isLoadFromStackSlotPostFE - Check for post-frame ptr elimination 125 /// stack locations as well. This uses a heuristic so it isn't 126 /// reliable for correctness. 127 virtual unsigned isLoadFromStackSlotPostFE(const MachineInstr *MI, 128 int &FrameIndex) const { 129 return 0; 130 } 131 132 /// hasLoadFromStackSlot - If the specified machine instruction has 133 /// a load from a stack slot, return true along with the FrameIndex 134 /// of the loaded stack slot and the machine mem operand containing 135 /// the reference. If not, return false. Unlike 136 /// isLoadFromStackSlot, this returns true for any instructions that 137 /// loads from the stack. This is just a hint, as some cases may be 138 /// missed. 139 virtual bool hasLoadFromStackSlot(const MachineInstr *MI, 140 const MachineMemOperand *&MMO, 141 int &FrameIndex) const { 142 return 0; 143 } 144 145 /// isStoreToStackSlot - If the specified machine instruction is a direct 146 /// store to a stack slot, return the virtual or physical register number of 147 /// the source reg along with the FrameIndex of the loaded stack slot. If 148 /// not, return 0. This predicate must return 0 if the instruction has 149 /// any side effects other than storing to the stack slot. 150 virtual unsigned isStoreToStackSlot(const MachineInstr *MI, 151 int &FrameIndex) const { 152 return 0; 153 } 154 155 /// isStoreToStackSlotPostFE - Check for post-frame ptr elimination 156 /// stack locations as well. This uses a heuristic so it isn't 157 /// reliable for correctness. 158 virtual unsigned isStoreToStackSlotPostFE(const MachineInstr *MI, 159 int &FrameIndex) const { 160 return 0; 161 } 162 163 /// hasStoreToStackSlot - If the specified machine instruction has a 164 /// store to a stack slot, return true along with the FrameIndex of 165 /// the loaded stack slot and the machine mem operand containing the 166 /// reference. If not, return false. Unlike isStoreToStackSlot, 167 /// this returns true for any instructions that stores to the 168 /// stack. This is just a hint, as some cases may be missed. 169 virtual bool hasStoreToStackSlot(const MachineInstr *MI, 170 const MachineMemOperand *&MMO, 171 int &FrameIndex) const { 172 return 0; 173 } 174 175 /// reMaterialize - Re-issue the specified 'original' instruction at the 176 /// specific location targeting a new destination register. 177 /// The register in Orig->getOperand(0).getReg() will be substituted by 178 /// DestReg:SubIdx. Any existing subreg index is preserved or composed with 179 /// SubIdx. 180 virtual void reMaterialize(MachineBasicBlock &MBB, 181 MachineBasicBlock::iterator MI, 182 unsigned DestReg, unsigned SubIdx, 183 const MachineInstr *Orig, 184 const TargetRegisterInfo &TRI) const = 0; 185 186 /// scheduleTwoAddrSource - Schedule the copy / re-mat of the source of the 187 /// two-addrss instruction inserted by two-address pass. 188 virtual void scheduleTwoAddrSource(MachineInstr *SrcMI, 189 MachineInstr *UseMI, 190 const TargetRegisterInfo &TRI) const { 191 // Do nothing. 192 } 193 194 /// duplicate - Create a duplicate of the Orig instruction in MF. This is like 195 /// MachineFunction::CloneMachineInstr(), but the target may update operands 196 /// that are required to be unique. 197 /// 198 /// The instruction must be duplicable as indicated by isNotDuplicable(). 199 virtual MachineInstr *duplicate(MachineInstr *Orig, 200 MachineFunction &MF) const = 0; 201 202 /// convertToThreeAddress - This method must be implemented by targets that 203 /// set the M_CONVERTIBLE_TO_3_ADDR flag. When this flag is set, the target 204 /// may be able to convert a two-address instruction into one or more true 205 /// three-address instructions on demand. This allows the X86 target (for 206 /// example) to convert ADD and SHL instructions into LEA instructions if they 207 /// would require register copies due to two-addressness. 208 /// 209 /// This method returns a null pointer if the transformation cannot be 210 /// performed, otherwise it returns the last new instruction. 211 /// 212 virtual MachineInstr * 213 convertToThreeAddress(MachineFunction::iterator &MFI, 214 MachineBasicBlock::iterator &MBBI, LiveVariables *LV) const { 215 return 0; 216 } 217 218 /// commuteInstruction - If a target has any instructions that are 219 /// commutable but require converting to different instructions or making 220 /// non-trivial changes to commute them, this method can overloaded to do 221 /// that. The default implementation simply swaps the commutable operands. 222 /// If NewMI is false, MI is modified in place and returned; otherwise, a 223 /// new machine instruction is created and returned. Do not call this 224 /// method for a non-commutable instruction, but there may be some cases 225 /// where this method fails and returns null. 226 virtual MachineInstr *commuteInstruction(MachineInstr *MI, 227 bool NewMI = false) const = 0; 228 229 /// findCommutedOpIndices - If specified MI is commutable, return the two 230 /// operand indices that would swap value. Return false if the instruction 231 /// is not in a form which this routine understands. 232 virtual bool findCommutedOpIndices(MachineInstr *MI, unsigned &SrcOpIdx1, 233 unsigned &SrcOpIdx2) const = 0; 234 235 /// produceSameValue - Return true if two machine instructions would produce 236 /// identical values. By default, this is only true when the two instructions 237 /// are deemed identical except for defs. If this function is called when the 238 /// IR is still in SSA form, the caller can pass the MachineRegisterInfo for 239 /// aggressive checks. 240 virtual bool produceSameValue(const MachineInstr *MI0, 241 const MachineInstr *MI1, 242 const MachineRegisterInfo *MRI = 0) const = 0; 243 244 /// AnalyzeBranch - Analyze the branching code at the end of MBB, returning 245 /// true if it cannot be understood (e.g. it's a switch dispatch or isn't 246 /// implemented for a target). Upon success, this returns false and returns 247 /// with the following information in various cases: 248 /// 249 /// 1. If this block ends with no branches (it just falls through to its succ) 250 /// just return false, leaving TBB/FBB null. 251 /// 2. If this block ends with only an unconditional branch, it sets TBB to be 252 /// the destination block. 253 /// 3. If this block ends with a conditional branch and it falls through to a 254 /// successor block, it sets TBB to be the branch destination block and a 255 /// list of operands that evaluate the condition. These operands can be 256 /// passed to other TargetInstrInfo methods to create new branches. 257 /// 4. If this block ends with a conditional branch followed by an 258 /// unconditional branch, it returns the 'true' destination in TBB, the 259 /// 'false' destination in FBB, and a list of operands that evaluate the 260 /// condition. These operands can be passed to other TargetInstrInfo 261 /// methods to create new branches. 262 /// 263 /// Note that RemoveBranch and InsertBranch must be implemented to support 264 /// cases where this method returns success. 265 /// 266 /// If AllowModify is true, then this routine is allowed to modify the basic 267 /// block (e.g. delete instructions after the unconditional branch). 268 /// 269 virtual bool AnalyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB, 270 MachineBasicBlock *&FBB, 271 SmallVectorImpl<MachineOperand> &Cond, 272 bool AllowModify = false) const { 273 return true; 274 } 275 276 /// RemoveBranch - Remove the branching code at the end of the specific MBB. 277 /// This is only invoked in cases where AnalyzeBranch returns success. It 278 /// returns the number of instructions that were removed. 279 virtual unsigned RemoveBranch(MachineBasicBlock &MBB) const { 280 assert(0 && "Target didn't implement TargetInstrInfo::RemoveBranch!"); 281 return 0; 282 } 283 284 /// InsertBranch - Insert branch code into the end of the specified 285 /// MachineBasicBlock. The operands to this method are the same as those 286 /// returned by AnalyzeBranch. This is only invoked in cases where 287 /// AnalyzeBranch returns success. It returns the number of instructions 288 /// inserted. 289 /// 290 /// It is also invoked by tail merging to add unconditional branches in 291 /// cases where AnalyzeBranch doesn't apply because there was no original 292 /// branch to analyze. At least this much must be implemented, else tail 293 /// merging needs to be disabled. 294 virtual unsigned InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB, 295 MachineBasicBlock *FBB, 296 const SmallVectorImpl<MachineOperand> &Cond, 297 DebugLoc DL) const { 298 assert(0 && "Target didn't implement TargetInstrInfo::InsertBranch!"); 299 return 0; 300 } 301 302 /// ReplaceTailWithBranchTo - Delete the instruction OldInst and everything 303 /// after it, replacing it with an unconditional branch to NewDest. This is 304 /// used by the tail merging pass. 305 virtual void ReplaceTailWithBranchTo(MachineBasicBlock::iterator Tail, 306 MachineBasicBlock *NewDest) const = 0; 307 308 /// isLegalToSplitMBBAt - Return true if it's legal to split the given basic 309 /// block at the specified instruction (i.e. instruction would be the start 310 /// of a new basic block). 311 virtual bool isLegalToSplitMBBAt(MachineBasicBlock &MBB, 312 MachineBasicBlock::iterator MBBI) const { 313 return true; 314 } 315 316 /// isProfitableToIfCvt - Return true if it's profitable to predicate 317 /// instructions with accumulated instruction latency of "NumCycles" 318 /// of the specified basic block, where the probability of the instructions 319 /// being executed is given by Probability, and Confidence is a measure 320 /// of our confidence that it will be properly predicted. 321 virtual 322 bool isProfitableToIfCvt(MachineBasicBlock &MBB, unsigned NumCyles, 323 unsigned ExtraPredCycles, 324 float Probability, float Confidence) const { 325 return false; 326 } 327 328 /// isProfitableToIfCvt - Second variant of isProfitableToIfCvt, this one 329 /// checks for the case where two basic blocks from true and false path 330 /// of a if-then-else (diamond) are predicated on mutally exclusive 331 /// predicates, where the probability of the true path being taken is given 332 /// by Probability, and Confidence is a measure of our confidence that it 333 /// will be properly predicted. 334 virtual bool 335 isProfitableToIfCvt(MachineBasicBlock &TMBB, 336 unsigned NumTCycles, unsigned ExtraTCycles, 337 MachineBasicBlock &FMBB, 338 unsigned NumFCycles, unsigned ExtraFCycles, 339 float Probability, float Confidence) const { 340 return false; 341 } 342 343 /// isProfitableToDupForIfCvt - Return true if it's profitable for 344 /// if-converter to duplicate instructions of specified accumulated 345 /// instruction latencies in the specified MBB to enable if-conversion. 346 /// The probability of the instructions being executed is given by 347 /// Probability, and Confidence is a measure of our confidence that it 348 /// will be properly predicted. 349 virtual bool 350 isProfitableToDupForIfCvt(MachineBasicBlock &MBB, unsigned NumCyles, 351 float Probability, float Confidence) const { 352 return false; 353 } 354 355 /// copyPhysReg - Emit instructions to copy a pair of physical registers. 356 virtual void copyPhysReg(MachineBasicBlock &MBB, 357 MachineBasicBlock::iterator MI, DebugLoc DL, 358 unsigned DestReg, unsigned SrcReg, 359 bool KillSrc) const { 360 assert(0 && "Target didn't implement TargetInstrInfo::copyPhysReg!"); 361 } 362 363 /// storeRegToStackSlot - Store the specified register of the given register 364 /// class to the specified stack frame index. The store instruction is to be 365 /// added to the given machine basic block before the specified machine 366 /// instruction. If isKill is true, the register operand is the last use and 367 /// must be marked kill. 368 virtual void storeRegToStackSlot(MachineBasicBlock &MBB, 369 MachineBasicBlock::iterator MI, 370 unsigned SrcReg, bool isKill, int FrameIndex, 371 const TargetRegisterClass *RC, 372 const TargetRegisterInfo *TRI) const { 373 assert(0 && "Target didn't implement TargetInstrInfo::storeRegToStackSlot!"); 374 } 375 376 /// loadRegFromStackSlot - Load the specified register of the given register 377 /// class from the specified stack frame index. The load instruction is to be 378 /// added to the given machine basic block before the specified machine 379 /// instruction. 380 virtual void loadRegFromStackSlot(MachineBasicBlock &MBB, 381 MachineBasicBlock::iterator MI, 382 unsigned DestReg, int FrameIndex, 383 const TargetRegisterClass *RC, 384 const TargetRegisterInfo *TRI) const { 385 assert(0 && "Target didn't implement TargetInstrInfo::loadRegFromStackSlot!"); 386 } 387 388 /// emitFrameIndexDebugValue - Emit a target-dependent form of 389 /// DBG_VALUE encoding the address of a frame index. Addresses would 390 /// normally be lowered the same way as other addresses on the target, 391 /// e.g. in load instructions. For targets that do not support this 392 /// the debug info is simply lost. 393 /// If you add this for a target you should handle this DBG_VALUE in the 394 /// target-specific AsmPrinter code as well; you will probably get invalid 395 /// assembly output if you don't. 396 virtual MachineInstr *emitFrameIndexDebugValue(MachineFunction &MF, 397 int FrameIx, 398 uint64_t Offset, 399 const MDNode *MDPtr, 400 DebugLoc dl) const { 401 return 0; 402 } 403 404 /// foldMemoryOperand - Attempt to fold a load or store of the specified stack 405 /// slot into the specified machine instruction for the specified operand(s). 406 /// If this is possible, a new instruction is returned with the specified 407 /// operand folded, otherwise NULL is returned. 408 /// The new instruction is inserted before MI, and the client is responsible 409 /// for removing the old instruction. 410 MachineInstr* foldMemoryOperand(MachineBasicBlock::iterator MI, 411 const SmallVectorImpl<unsigned> &Ops, 412 int FrameIndex) const; 413 414 /// foldMemoryOperand - Same as the previous version except it allows folding 415 /// of any load and store from / to any address, not just from a specific 416 /// stack slot. 417 MachineInstr* foldMemoryOperand(MachineBasicBlock::iterator MI, 418 const SmallVectorImpl<unsigned> &Ops, 419 MachineInstr* LoadMI) const; 420 421protected: 422 /// foldMemoryOperandImpl - Target-dependent implementation for 423 /// foldMemoryOperand. Target-independent code in foldMemoryOperand will 424 /// take care of adding a MachineMemOperand to the newly created instruction. 425 virtual MachineInstr* foldMemoryOperandImpl(MachineFunction &MF, 426 MachineInstr* MI, 427 const SmallVectorImpl<unsigned> &Ops, 428 int FrameIndex) const { 429 return 0; 430 } 431 432 /// foldMemoryOperandImpl - Target-dependent implementation for 433 /// foldMemoryOperand. Target-independent code in foldMemoryOperand will 434 /// take care of adding a MachineMemOperand to the newly created instruction. 435 virtual MachineInstr* foldMemoryOperandImpl(MachineFunction &MF, 436 MachineInstr* MI, 437 const SmallVectorImpl<unsigned> &Ops, 438 MachineInstr* LoadMI) const { 439 return 0; 440 } 441 442public: 443 /// canFoldMemoryOperand - Returns true for the specified load / store if 444 /// folding is possible. 445 virtual 446 bool canFoldMemoryOperand(const MachineInstr *MI, 447 const SmallVectorImpl<unsigned> &Ops) const =0; 448 449 /// unfoldMemoryOperand - Separate a single instruction which folded a load or 450 /// a store or a load and a store into two or more instruction. If this is 451 /// possible, returns true as well as the new instructions by reference. 452 virtual bool unfoldMemoryOperand(MachineFunction &MF, MachineInstr *MI, 453 unsigned Reg, bool UnfoldLoad, bool UnfoldStore, 454 SmallVectorImpl<MachineInstr*> &NewMIs) const{ 455 return false; 456 } 457 458 virtual bool unfoldMemoryOperand(SelectionDAG &DAG, SDNode *N, 459 SmallVectorImpl<SDNode*> &NewNodes) const { 460 return false; 461 } 462 463 /// getOpcodeAfterMemoryUnfold - Returns the opcode of the would be new 464 /// instruction after load / store are unfolded from an instruction of the 465 /// specified opcode. It returns zero if the specified unfolding is not 466 /// possible. If LoadRegIndex is non-null, it is filled in with the operand 467 /// index of the operand which will hold the register holding the loaded 468 /// value. 469 virtual unsigned getOpcodeAfterMemoryUnfold(unsigned Opc, 470 bool UnfoldLoad, bool UnfoldStore, 471 unsigned *LoadRegIndex = 0) const { 472 return 0; 473 } 474 475 /// areLoadsFromSameBasePtr - This is used by the pre-regalloc scheduler 476 /// to determine if two loads are loading from the same base address. It 477 /// should only return true if the base pointers are the same and the 478 /// only differences between the two addresses are the offset. It also returns 479 /// the offsets by reference. 480 virtual bool areLoadsFromSameBasePtr(SDNode *Load1, SDNode *Load2, 481 int64_t &Offset1, int64_t &Offset2) const { 482 return false; 483 } 484 485 /// shouldScheduleLoadsNear - This is a used by the pre-regalloc scheduler to 486 /// determine (in conjunction with areLoadsFromSameBasePtr) if two loads should 487 /// be scheduled togther. On some targets if two loads are loading from 488 /// addresses in the same cache line, it's better if they are scheduled 489 /// together. This function takes two integers that represent the load offsets 490 /// from the common base address. It returns true if it decides it's desirable 491 /// to schedule the two loads together. "NumLoads" is the number of loads that 492 /// have already been scheduled after Load1. 493 virtual bool shouldScheduleLoadsNear(SDNode *Load1, SDNode *Load2, 494 int64_t Offset1, int64_t Offset2, 495 unsigned NumLoads) const { 496 return false; 497 } 498 499 /// ReverseBranchCondition - Reverses the branch condition of the specified 500 /// condition list, returning false on success and true if it cannot be 501 /// reversed. 502 virtual 503 bool ReverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const { 504 return true; 505 } 506 507 /// insertNoop - Insert a noop into the instruction stream at the specified 508 /// point. 509 virtual void insertNoop(MachineBasicBlock &MBB, 510 MachineBasicBlock::iterator MI) const; 511 512 513 /// getNoopForMachoTarget - Return the noop instruction to use for a noop. 514 virtual void getNoopForMachoTarget(MCInst &NopInst) const { 515 // Default to just using 'nop' string. 516 } 517 518 519 /// isPredicated - Returns true if the instruction is already predicated. 520 /// 521 virtual bool isPredicated(const MachineInstr *MI) const { 522 return false; 523 } 524 525 /// isUnpredicatedTerminator - Returns true if the instruction is a 526 /// terminator instruction that has not been predicated. 527 virtual bool isUnpredicatedTerminator(const MachineInstr *MI) const; 528 529 /// PredicateInstruction - Convert the instruction into a predicated 530 /// instruction. It returns true if the operation was successful. 531 virtual 532 bool PredicateInstruction(MachineInstr *MI, 533 const SmallVectorImpl<MachineOperand> &Pred) const = 0; 534 535 /// SubsumesPredicate - Returns true if the first specified predicate 536 /// subsumes the second, e.g. GE subsumes GT. 537 virtual 538 bool SubsumesPredicate(const SmallVectorImpl<MachineOperand> &Pred1, 539 const SmallVectorImpl<MachineOperand> &Pred2) const { 540 return false; 541 } 542 543 /// DefinesPredicate - If the specified instruction defines any predicate 544 /// or condition code register(s) used for predication, returns true as well 545 /// as the definition predicate(s) by reference. 546 virtual bool DefinesPredicate(MachineInstr *MI, 547 std::vector<MachineOperand> &Pred) const { 548 return false; 549 } 550 551 /// isPredicable - Return true if the specified instruction can be predicated. 552 /// By default, this returns true for every instruction with a 553 /// PredicateOperand. 554 virtual bool isPredicable(MachineInstr *MI) const { 555 return MI->getDesc().isPredicable(); 556 } 557 558 /// isSafeToMoveRegClassDefs - Return true if it's safe to move a machine 559 /// instruction that defines the specified register class. 560 virtual bool isSafeToMoveRegClassDefs(const TargetRegisterClass *RC) const { 561 return true; 562 } 563 564 /// isSchedulingBoundary - Test if the given instruction should be 565 /// considered a scheduling boundary. This primarily includes labels and 566 /// terminators. 567 virtual bool isSchedulingBoundary(const MachineInstr *MI, 568 const MachineBasicBlock *MBB, 569 const MachineFunction &MF) const = 0; 570 571 /// Measure the specified inline asm to determine an approximation of its 572 /// length. 573 virtual unsigned getInlineAsmLength(const char *Str, 574 const MCAsmInfo &MAI) const; 575 576 /// CreateTargetHazardRecognizer - Allocate and return a hazard recognizer to 577 /// use for this target when scheduling the machine instructions before 578 /// register allocation. 579 virtual ScheduleHazardRecognizer* 580 CreateTargetHazardRecognizer(const TargetMachine *TM, 581 const ScheduleDAG *DAG) const = 0; 582 583 /// CreateTargetPostRAHazardRecognizer - Allocate and return a hazard 584 /// recognizer to use for this target when scheduling the machine instructions 585 /// after register allocation. 586 virtual ScheduleHazardRecognizer* 587 CreateTargetPostRAHazardRecognizer(const InstrItineraryData*, 588 const ScheduleDAG *DAG) const = 0; 589 590 /// AnalyzeCompare - For a comparison instruction, return the source register 591 /// in SrcReg and the value it compares against in CmpValue. Return true if 592 /// the comparison instruction can be analyzed. 593 virtual bool AnalyzeCompare(const MachineInstr *MI, 594 unsigned &SrcReg, int &Mask, int &Value) const { 595 return false; 596 } 597 598 /// OptimizeCompareInstr - See if the comparison instruction can be converted 599 /// into something more efficient. E.g., on ARM most instructions can set the 600 /// flags register, obviating the need for a separate CMP. 601 virtual bool OptimizeCompareInstr(MachineInstr *CmpInstr, 602 unsigned SrcReg, int Mask, int Value, 603 const MachineRegisterInfo *MRI) const { 604 return false; 605 } 606 607 /// FoldImmediate - 'Reg' is known to be defined by a move immediate 608 /// instruction, try to fold the immediate into the use instruction. 609 virtual bool FoldImmediate(MachineInstr *UseMI, MachineInstr *DefMI, 610 unsigned Reg, MachineRegisterInfo *MRI) const { 611 return false; 612 } 613 614 /// getNumMicroOps - Return the number of u-operations the given machine 615 /// instruction will be decoded to on the target cpu. 616 virtual unsigned getNumMicroOps(const InstrItineraryData *ItinData, 617 const MachineInstr *MI) const; 618 619 /// isZeroCost - Return true for pseudo instructions that don't consume any 620 /// machine resources in their current form. These are common cases that the 621 /// scheduler should consider free, rather than conservatively handling them 622 /// as instructions with no itinerary. 623 bool isZeroCost(unsigned Opcode) const { 624 return Opcode <= TargetOpcode::COPY; 625 } 626 627 /// getOperandLatency - Compute and return the use operand latency of a given 628 /// pair of def and use. 629 /// In most cases, the static scheduling itinerary was enough to determine the 630 /// operand latency. But it may not be possible for instructions with variable 631 /// number of defs / uses. 632 virtual int getOperandLatency(const InstrItineraryData *ItinData, 633 const MachineInstr *DefMI, unsigned DefIdx, 634 const MachineInstr *UseMI, unsigned UseIdx) const; 635 636 virtual int getOperandLatency(const InstrItineraryData *ItinData, 637 SDNode *DefNode, unsigned DefIdx, 638 SDNode *UseNode, unsigned UseIdx) const; 639 640 /// getInstrLatency - Compute the instruction latency of a given instruction. 641 /// If the instruction has higher cost when predicated, it's returned via 642 /// PredCost. 643 virtual int getInstrLatency(const InstrItineraryData *ItinData, 644 const MachineInstr *MI, 645 unsigned *PredCost = 0) const; 646 647 virtual int getInstrLatency(const InstrItineraryData *ItinData, 648 SDNode *Node) const; 649 650 /// isHighLatencyDef - Return true if this opcode has high latency to its 651 /// result. 652 virtual bool isHighLatencyDef(int opc) const { return false; } 653 654 /// hasHighOperandLatency - Compute operand latency between a def of 'Reg' 655 /// and an use in the current loop, return true if the target considered 656 /// it 'high'. This is used by optimization passes such as machine LICM to 657 /// determine whether it makes sense to hoist an instruction out even in 658 /// high register pressure situation. 659 virtual 660 bool hasHighOperandLatency(const InstrItineraryData *ItinData, 661 const MachineRegisterInfo *MRI, 662 const MachineInstr *DefMI, unsigned DefIdx, 663 const MachineInstr *UseMI, unsigned UseIdx) const { 664 return false; 665 } 666 667 /// hasLowDefLatency - Compute operand latency of a def of 'Reg', return true 668 /// if the target considered it 'low'. 669 virtual 670 bool hasLowDefLatency(const InstrItineraryData *ItinData, 671 const MachineInstr *DefMI, unsigned DefIdx) const; 672 673private: 674 int CallFrameSetupOpcode, CallFrameDestroyOpcode; 675}; 676 677/// TargetInstrInfoImpl - This is the default implementation of 678/// TargetInstrInfo, which just provides a couple of default implementations 679/// for various methods. This separated out because it is implemented in 680/// libcodegen, not in libtarget. 681class TargetInstrInfoImpl : public TargetInstrInfo { 682protected: 683 TargetInstrInfoImpl(int CallFrameSetupOpcode = -1, 684 int CallFrameDestroyOpcode = -1) 685 : TargetInstrInfo(CallFrameSetupOpcode, CallFrameDestroyOpcode) {} 686public: 687 virtual void ReplaceTailWithBranchTo(MachineBasicBlock::iterator OldInst, 688 MachineBasicBlock *NewDest) const; 689 virtual MachineInstr *commuteInstruction(MachineInstr *MI, 690 bool NewMI = false) const; 691 virtual bool findCommutedOpIndices(MachineInstr *MI, unsigned &SrcOpIdx1, 692 unsigned &SrcOpIdx2) const; 693 virtual bool canFoldMemoryOperand(const MachineInstr *MI, 694 const SmallVectorImpl<unsigned> &Ops) const; 695 virtual bool PredicateInstruction(MachineInstr *MI, 696 const SmallVectorImpl<MachineOperand> &Pred) const; 697 virtual void reMaterialize(MachineBasicBlock &MBB, 698 MachineBasicBlock::iterator MI, 699 unsigned DestReg, unsigned SubReg, 700 const MachineInstr *Orig, 701 const TargetRegisterInfo &TRI) const; 702 virtual MachineInstr *duplicate(MachineInstr *Orig, 703 MachineFunction &MF) const; 704 virtual bool produceSameValue(const MachineInstr *MI0, 705 const MachineInstr *MI1, 706 const MachineRegisterInfo *MRI) const; 707 virtual bool isSchedulingBoundary(const MachineInstr *MI, 708 const MachineBasicBlock *MBB, 709 const MachineFunction &MF) const; 710 711 bool usePreRAHazardRecognizer() const; 712 713 virtual ScheduleHazardRecognizer * 714 CreateTargetHazardRecognizer(const TargetMachine*, const ScheduleDAG*) const; 715 716 virtual ScheduleHazardRecognizer * 717 CreateTargetPostRAHazardRecognizer(const InstrItineraryData*, 718 const ScheduleDAG*) const; 719}; 720 721} // End llvm namespace 722 723#endif 724