TargetInstrInfo.h revision 5fa01b9c7a33ecd0e006427ae2a44170cf60422d
1//===-- llvm/Target/MachineInstrInstrInfo.h - Instruction Infor ---*-C++-*-===// 2// 3// This file describes the target machine instructions to the code generator. 4// 5//===----------------------------------------------------------------------===// 6 7#ifndef LLVM_TARGET_MACHINEINSTRINFO_H 8#define LLVM_TARGET_MACHINEINSTRINFO_H 9 10#include "Support/DataTypes.h" 11#include <vector> 12 13class MachineInstrDescriptor; 14class MachineInstr; 15class TargetMachine; 16class Value; 17class Instruction; 18class Constant; 19class Function; 20class MachineCodeForInstruction; 21 22//--------------------------------------------------------------------------- 23// Data types used to define information about a single machine instruction 24//--------------------------------------------------------------------------- 25 26typedef int MachineOpCode; 27typedef unsigned InstrSchedClass; 28 29const MachineOpCode INVALID_MACHINE_OPCODE = -1; 30 31 32//--------------------------------------------------------------------------- 33// struct MachineInstrDescriptor: 34// Predefined information about each machine instruction. 35// Designed to initialized statically. 36// 37// class MachineInstructionInfo 38// Interface to description of machine instructions 39// 40//--------------------------------------------------------------------------- 41 42const unsigned M_NOP_FLAG = 1 << 0; 43const unsigned M_BRANCH_FLAG = 1 << 1; 44const unsigned M_CALL_FLAG = 1 << 2; 45const unsigned M_RET_FLAG = 1 << 3; 46const unsigned M_ARITH_FLAG = 1 << 4; 47const unsigned M_CC_FLAG = 1 << 6; 48const unsigned M_LOGICAL_FLAG = 1 << 6; 49const unsigned M_INT_FLAG = 1 << 7; 50const unsigned M_FLOAT_FLAG = 1 << 8; 51const unsigned M_CONDL_FLAG = 1 << 9; 52const unsigned M_LOAD_FLAG = 1 << 10; 53const unsigned M_PREFETCH_FLAG = 1 << 11; 54const unsigned M_STORE_FLAG = 1 << 12; 55const unsigned M_DUMMY_PHI_FLAG = 1 << 13; 56const unsigned M_PSEUDO_FLAG = 1 << 14; // Pseudo instruction 57// 3-addr instructions which really work like 2-addr ones, eg. X86 add/sub 58const unsigned M_2_ADDR_FLAG = 1 << 15; 59 60struct MachineInstrDescriptor { 61 const char * Name; // Assembly language mnemonic for the opcode. 62 int numOperands; // Number of args; -1 if variable #args 63 int resultPos; // Position of the result; -1 if no result 64 unsigned maxImmedConst; // Largest +ve constant in IMMMED field or 0. 65 bool immedIsSignExtended; // Is IMMED field sign-extended? If so, 66 // smallest -ve value is -(maxImmedConst+1). 67 unsigned numDelaySlots; // Number of delay slots after instruction 68 unsigned latency; // Latency in machine cycles 69 InstrSchedClass schedClass; // enum identifying instr sched class 70 unsigned Flags; // flags identifying machine instr class 71 unsigned TSFlags; // Target Specific Flag values 72 const unsigned *ImplicitUses; // Registers implicitly read by this instr 73 const unsigned *ImplicitDefs; // Registers implicitly defined by this instr 74}; 75 76 77class MachineInstrInfo { 78 const MachineInstrDescriptor* desc; // raw array to allow static init'n 79 unsigned descSize; // number of entries in the desc array 80 unsigned numRealOpCodes; // number of non-dummy op codes 81 82 MachineInstrInfo(const MachineInstrInfo &); // DO NOT IMPLEMENT 83 void operator=(const MachineInstrInfo &); // DO NOT IMPLEMENT 84public: 85 MachineInstrInfo(const MachineInstrDescriptor *desc, unsigned descSize, 86 unsigned numRealOpCodes); 87 virtual ~MachineInstrInfo(); 88 89 // Invariant: All instruction sets use opcode #0 as the PHI instruction and 90 // opcode #1 as the noop instruction. 91 enum { 92 PHI = 0, NOOP = 1 93 }; 94 95 unsigned getNumRealOpCodes() const { return numRealOpCodes; } 96 unsigned getNumTotalOpCodes() const { return descSize; } 97 98 /// get - Return the machine instruction descriptor that corresponds to the 99 /// specified instruction opcode. 100 /// 101 const MachineInstrDescriptor& get(MachineOpCode opCode) const { 102 assert(opCode >= 0 && opCode < (int)descSize); 103 return desc[opCode]; 104 } 105 106 /// print - Print out the specified machine instruction in the appropriate 107 /// target specific assembly language. If this method is not overridden, the 108 /// default implementation uses the crummy machine independant printer. 109 /// 110 virtual void print(const MachineInstr *MI, std::ostream &O, 111 const TargetMachine &TM) const; 112 113 const char *getName(MachineOpCode opCode) const { 114 return get(opCode).Name; 115 } 116 117 int getNumOperands(MachineOpCode opCode) const { 118 return get(opCode).numOperands; 119 } 120 121 int getResultPos(MachineOpCode opCode) const { 122 return get(opCode).resultPos; 123 } 124 125 unsigned getNumDelaySlots(MachineOpCode opCode) const { 126 return get(opCode).numDelaySlots; 127 } 128 129 InstrSchedClass getSchedClass(MachineOpCode opCode) const { 130 return get(opCode).schedClass; 131 } 132 133 // 134 // Query instruction class flags according to the machine-independent 135 // flags listed above. 136 // 137 bool isNop(MachineOpCode opCode) const { 138 return get(opCode).Flags & M_NOP_FLAG; 139 } 140 bool isBranch(MachineOpCode opCode) const { 141 return get(opCode).Flags & M_BRANCH_FLAG; 142 } 143 bool isCall(MachineOpCode opCode) const { 144 return get(opCode).Flags & M_CALL_FLAG; 145 } 146 bool isReturn(MachineOpCode opCode) const { 147 return get(opCode).Flags & M_RET_FLAG; 148 } 149 bool isControlFlow(MachineOpCode opCode) const { 150 return get(opCode).Flags & M_BRANCH_FLAG 151 || get(opCode).Flags & M_CALL_FLAG 152 || get(opCode).Flags & M_RET_FLAG; 153 } 154 bool isArith(MachineOpCode opCode) const { 155 return get(opCode).Flags & M_ARITH_FLAG; 156 } 157 bool isCCInstr(MachineOpCode opCode) const { 158 return get(opCode).Flags & M_CC_FLAG; 159 } 160 bool isLogical(MachineOpCode opCode) const { 161 return get(opCode).Flags & M_LOGICAL_FLAG; 162 } 163 bool isIntInstr(MachineOpCode opCode) const { 164 return get(opCode).Flags & M_INT_FLAG; 165 } 166 bool isFloatInstr(MachineOpCode opCode) const { 167 return get(opCode).Flags & M_FLOAT_FLAG; 168 } 169 bool isConditional(MachineOpCode opCode) const { 170 return get(opCode).Flags & M_CONDL_FLAG; 171 } 172 bool isLoad(MachineOpCode opCode) const { 173 return get(opCode).Flags & M_LOAD_FLAG; 174 } 175 bool isPrefetch(MachineOpCode opCode) const { 176 return get(opCode).Flags & M_PREFETCH_FLAG; 177 } 178 bool isLoadOrPrefetch(MachineOpCode opCode) const { 179 return get(opCode).Flags & M_LOAD_FLAG 180 || get(opCode).Flags & M_PREFETCH_FLAG; 181 } 182 bool isStore(MachineOpCode opCode) const { 183 return get(opCode).Flags & M_STORE_FLAG; 184 } 185 bool isMemoryAccess(MachineOpCode opCode) const { 186 return get(opCode).Flags & M_LOAD_FLAG 187 || get(opCode).Flags & M_PREFETCH_FLAG 188 || get(opCode).Flags & M_STORE_FLAG; 189 } 190 bool isDummyPhiInstr(const MachineOpCode opCode) const { 191 return get(opCode).Flags & M_DUMMY_PHI_FLAG; 192 } 193 bool isPseudoInstr(const MachineOpCode opCode) const { 194 return get(opCode).Flags & M_PSEUDO_FLAG; 195 } 196 bool isTwoAddrInstr(const MachineOpCode opCode) const { 197 return get(opCode).Flags & M_2_ADDR_FLAG; 198 } 199 200 // Check if an instruction can be issued before its operands are ready, 201 // or if a subsequent instruction that uses its result can be issued 202 // before the results are ready. 203 // Default to true since most instructions on many architectures allow this. 204 // 205 virtual bool hasOperandInterlock(MachineOpCode opCode) const { 206 return true; 207 } 208 209 virtual bool hasResultInterlock(MachineOpCode opCode) const { 210 return true; 211 } 212 213 // 214 // Latencies for individual instructions and instruction pairs 215 // 216 virtual int minLatency(MachineOpCode opCode) const { 217 return get(opCode).latency; 218 } 219 220 virtual int maxLatency(MachineOpCode opCode) const { 221 return get(opCode).latency; 222 } 223 224 // 225 // Which operand holds an immediate constant? Returns -1 if none 226 // 227 virtual int getImmedConstantPos(MachineOpCode opCode) const { 228 return -1; // immediate position is machine specific, so say -1 == "none" 229 } 230 231 // Check if the specified constant fits in the immediate field 232 // of this machine instruction 233 // 234 virtual bool constantFitsInImmedField(MachineOpCode opCode, 235 int64_t intValue) const; 236 237 // Return the largest +ve constant that can be held in the IMMMED field 238 // of this machine instruction. 239 // isSignExtended is set to true if the value is sign-extended before use 240 // (this is true for all immediate fields in SPARC instructions). 241 // Return 0 if the instruction has no IMMED field. 242 // 243 virtual uint64_t maxImmedConstant(MachineOpCode opCode, 244 bool &isSignExtended) const { 245 isSignExtended = get(opCode).immedIsSignExtended; 246 return get(opCode).maxImmedConst; 247 } 248 249 //------------------------------------------------------------------------- 250 // Queries about representation of LLVM quantities (e.g., constants) 251 //------------------------------------------------------------------------- 252 253 /// ConstantTypeMustBeLoaded - Test if this type of constant must be loaded 254 /// from memory into a register, i.e., cannot be set bitwise in register and 255 /// cannot use immediate fields of instructions. Note that this only makes 256 /// sense for primitive types. 257 /// 258 virtual bool ConstantTypeMustBeLoaded(const Constant* CV) const; 259 260 // Test if this constant may not fit in the immediate field of the 261 // machine instructions (probably) generated for this instruction. 262 // 263 virtual bool ConstantMayNotFitInImmedField(const Constant* CV, 264 const Instruction* I) const { 265 return true; // safe but very conservative 266 } 267 268 //------------------------------------------------------------------------- 269 // Code generation support for creating individual machine instructions 270 // 271 // WARNING: These methods are Sparc specific 272 // 273 //------------------------------------------------------------------------- 274 275 // Get certain common op codes for the current target. this and all the 276 // Create* methods below should be moved to a machine code generation class 277 // 278 virtual MachineOpCode getNOPOpCode() const { abort(); } 279 280 // Create an instruction sequence to put the constant `val' into 281 // the virtual register `dest'. `val' may be a Constant or a 282 // GlobalValue, viz., the constant address of a global variable or function. 283 // The generated instructions are returned in `mvec'. 284 // Any temp. registers (TmpInstruction) created are recorded in mcfi. 285 // Symbolic constants or constants that must be accessed from memory 286 // are added to the constant pool via MachineFunction::get(F). 287 // 288 virtual void CreateCodeToLoadConst(const TargetMachine& target, 289 Function* F, 290 Value* val, 291 Instruction* dest, 292 std::vector<MachineInstr*>& mvec, 293 MachineCodeForInstruction& mcfi) const { 294 abort(); 295 } 296 297 // Create an instruction sequence to copy an integer value `val' 298 // to a floating point value `dest' by copying to memory and back. 299 // val must be an integral type. dest must be a Float or Double. 300 // The generated instructions are returned in `mvec'. 301 // Any temp. registers (TmpInstruction) created are recorded in mcfi. 302 // Any stack space required is allocated via mcff. 303 // 304 virtual void CreateCodeToCopyIntToFloat(const TargetMachine& target, 305 Function* F, 306 Value* val, 307 Instruction* dest, 308 std::vector<MachineInstr*>& mvec, 309 MachineCodeForInstruction& MI) const { 310 abort(); 311 } 312 313 // Similarly, create an instruction sequence to copy an FP value 314 // `val' to an integer value `dest' by copying to memory and back. 315 // The generated instructions are returned in `mvec'. 316 // Any temp. registers (TmpInstruction) created are recorded in mcfi. 317 // Any stack space required is allocated via mcff. 318 // 319 virtual void CreateCodeToCopyFloatToInt(const TargetMachine& target, 320 Function* F, 321 Value* val, 322 Instruction* dest, 323 std::vector<MachineInstr*>& mvec, 324 MachineCodeForInstruction& MI) const { 325 abort(); 326 } 327 328 // Create instruction(s) to copy src to dest, for arbitrary types 329 // The generated instructions are returned in `mvec'. 330 // Any temp. registers (TmpInstruction) created are recorded in mcfi. 331 // Any stack space required is allocated via mcff. 332 // 333 virtual void CreateCopyInstructionsByType(const TargetMachine& target, 334 Function* F, 335 Value* src, 336 Instruction* dest, 337 std::vector<MachineInstr*>& mvec, 338 MachineCodeForInstruction& MI) const { 339 abort(); 340 } 341 342 // Create instruction sequence to produce a sign-extended register value 343 // from an arbitrary sized value (sized in bits, not bytes). 344 // The generated instructions are appended to `mvec'. 345 // Any temp. registers (TmpInstruction) created are recorded in mcfi. 346 // Any stack space required is allocated via mcff. 347 // 348 virtual void CreateSignExtensionInstructions(const TargetMachine& target, 349 Function* F, 350 Value* srcVal, 351 Value* destVal, 352 unsigned numLowBits, 353 std::vector<MachineInstr*>& mvec, 354 MachineCodeForInstruction& MI) const { 355 abort(); 356 } 357 358 // Create instruction sequence to produce a zero-extended register value 359 // from an arbitrary sized value (sized in bits, not bytes). 360 // The generated instructions are appended to `mvec'. 361 // Any temp. registers (TmpInstruction) created are recorded in mcfi. 362 // Any stack space required is allocated via mcff. 363 // 364 virtual void CreateZeroExtensionInstructions(const TargetMachine& target, 365 Function* F, 366 Value* srcVal, 367 Value* destVal, 368 unsigned srcSizeInBits, 369 std::vector<MachineInstr*>& mvec, 370 MachineCodeForInstruction& mcfi) const { 371 abort(); 372 } 373}; 374 375#endif 376