TargetInstrInfo.h revision 63be493b52e3558f2c579fef78d194c76c99eb8b
1//===-- llvm/Target/TargetInstrInfo.h - Instruction Info --------*- C++ -*-===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This file describes the target machine instruction set to the code generator. 11// 12//===----------------------------------------------------------------------===// 13 14#ifndef LLVM_TARGET_TARGETINSTRINFO_H 15#define LLVM_TARGET_TARGETINSTRINFO_H 16 17#include "llvm/Target/TargetInstrDesc.h" 18#include "llvm/CodeGen/MachineFunction.h" 19 20namespace llvm { 21 22class MCAsmInfo; 23class TargetRegisterClass; 24class TargetRegisterInfo; 25class LiveVariables; 26class CalleeSavedInfo; 27class SDNode; 28class SelectionDAG; 29class MachineMemOperand; 30 31template<class T> class SmallVectorImpl; 32 33 34//--------------------------------------------------------------------------- 35/// 36/// TargetInstrInfo - Interface to description of machine instruction set 37/// 38class TargetInstrInfo { 39 const TargetInstrDesc *Descriptors; // Raw array to allow static init'n 40 unsigned NumOpcodes; // Number of entries in the desc array 41 42 TargetInstrInfo(const TargetInstrInfo &); // DO NOT IMPLEMENT 43 void operator=(const TargetInstrInfo &); // DO NOT IMPLEMENT 44public: 45 TargetInstrInfo(const TargetInstrDesc *desc, unsigned NumOpcodes); 46 virtual ~TargetInstrInfo(); 47 48 // Invariant opcodes: All instruction sets have these as their low opcodes. 49 enum { 50 PHI = 0, 51 INLINEASM = 1, 52 DBG_LABEL = 2, 53 EH_LABEL = 3, 54 GC_LABEL = 4, 55 56 /// KILL - This instruction is a noop that is used only to adjust the liveness 57 /// of registers. This can be useful when dealing with sub-registers. 58 KILL = 5, 59 60 /// EXTRACT_SUBREG - This instruction takes two operands: a register 61 /// that has subregisters, and a subregister index. It returns the 62 /// extracted subregister value. This is commonly used to implement 63 /// truncation operations on target architectures which support it. 64 EXTRACT_SUBREG = 6, 65 66 /// INSERT_SUBREG - This instruction takes three operands: a register 67 /// that has subregisters, a register providing an insert value, and a 68 /// subregister index. It returns the value of the first register with 69 /// the value of the second register inserted. The first register is 70 /// often defined by an IMPLICIT_DEF, as is commonly used to implement 71 /// anyext operations on target architectures which support it. 72 INSERT_SUBREG = 7, 73 74 /// IMPLICIT_DEF - This is the MachineInstr-level equivalent of undef. 75 IMPLICIT_DEF = 8, 76 77 /// SUBREG_TO_REG - This instruction is similar to INSERT_SUBREG except 78 /// that the first operand is an immediate integer constant. This constant 79 /// is often zero, as is commonly used to implement zext operations on 80 /// target architectures which support it, such as with x86-64 (with 81 /// zext from i32 to i64 via implicit zero-extension). 82 SUBREG_TO_REG = 9, 83 84 /// COPY_TO_REGCLASS - This instruction is a placeholder for a plain 85 /// register-to-register copy into a specific register class. This is only 86 /// used between instruction selection and MachineInstr creation, before 87 /// virtual registers have been created for all the instructions, and it's 88 /// only needed in cases where the register classes implied by the 89 /// instructions are insufficient. The actual MachineInstrs to perform 90 /// the copy are emitted with the TargetInstrInfo::copyRegToReg hook. 91 COPY_TO_REGCLASS = 10 92 }; 93 94 unsigned getNumOpcodes() const { return NumOpcodes; } 95 96 /// get - Return the machine instruction descriptor that corresponds to the 97 /// specified instruction opcode. 98 /// 99 const TargetInstrDesc &get(unsigned Opcode) const { 100 assert(Opcode < NumOpcodes && "Invalid opcode!"); 101 return Descriptors[Opcode]; 102 } 103 104 /// isTriviallyReMaterializable - Return true if the instruction is trivially 105 /// rematerializable, meaning it has no side effects and requires no operands 106 /// that aren't always available. 107 bool isTriviallyReMaterializable(const MachineInstr *MI, 108 AliasAnalysis *AA = 0) const { 109 return MI->getOpcode() == IMPLICIT_DEF || 110 (MI->getDesc().isRematerializable() && 111 (isReallyTriviallyReMaterializable(MI, AA) || 112 isReallyTriviallyReMaterializableGeneric(MI, AA))); 113 } 114 115protected: 116 /// isReallyTriviallyReMaterializable - For instructions with opcodes for 117 /// which the M_REMATERIALIZABLE flag is set, this hook lets the target 118 /// specify whether the instruction is actually trivially rematerializable, 119 /// taking into consideration its operands. This predicate must return false 120 /// if the instruction has any side effects other than producing a value, or 121 /// if it requres any address registers that are not always available. 122 virtual bool isReallyTriviallyReMaterializable(const MachineInstr *MI, 123 AliasAnalysis *AA) const { 124 return false; 125 } 126 127private: 128 /// isReallyTriviallyReMaterializableGeneric - For instructions with opcodes 129 /// for which the M_REMATERIALIZABLE flag is set and the target hook 130 /// isReallyTriviallyReMaterializable returns false, this function does 131 /// target-independent tests to determine if the instruction is really 132 /// trivially rematerializable. 133 bool isReallyTriviallyReMaterializableGeneric(const MachineInstr *MI, 134 AliasAnalysis *AA) const; 135 136public: 137 /// isMoveInstr - Return true if the instruction is a register to register 138 /// move and return the source and dest operands and their sub-register 139 /// indices by reference. 140 virtual bool isMoveInstr(const MachineInstr& MI, 141 unsigned& SrcReg, unsigned& DstReg, 142 unsigned& SrcSubIdx, unsigned& DstSubIdx) const { 143 return false; 144 } 145 146 /// isIdentityCopy - Return true if the instruction is a copy (or 147 /// extract_subreg, insert_subreg, subreg_to_reg) where the source and 148 /// destination registers are the same. 149 bool isIdentityCopy(const MachineInstr &MI) const { 150 unsigned SrcReg, DstReg, SrcSubIdx, DstSubIdx; 151 if (isMoveInstr(MI, SrcReg, DstReg, SrcSubIdx, DstSubIdx) && 152 SrcReg == DstReg) 153 return true; 154 155 if (MI.getOpcode() == TargetInstrInfo::EXTRACT_SUBREG && 156 MI.getOperand(0).getReg() == MI.getOperand(1).getReg()) 157 return true; 158 159 if ((MI.getOpcode() == TargetInstrInfo::INSERT_SUBREG || 160 MI.getOpcode() == TargetInstrInfo::SUBREG_TO_REG) && 161 MI.getOperand(0).getReg() == MI.getOperand(2).getReg()) 162 return true; 163 return false; 164 } 165 166 /// isLoadFromStackSlot - If the specified machine instruction is a direct 167 /// load from a stack slot, return the virtual or physical register number of 168 /// the destination along with the FrameIndex of the loaded stack slot. If 169 /// not, return 0. This predicate must return 0 if the instruction has 170 /// any side effects other than loading from the stack slot. 171 virtual unsigned isLoadFromStackSlot(const MachineInstr *MI, 172 int &FrameIndex) const { 173 return 0; 174 } 175 176 /// isLoadFromStackSlotPostFE - Check for post-frame ptr elimination 177 /// stack locations as well. This uses a heuristic so it isn't 178 /// reliable for correctness. 179 virtual unsigned isLoadFromStackSlotPostFE(const MachineInstr *MI, 180 int &FrameIndex) const { 181 return 0; 182 } 183 184 /// hasLoadFromStackSlot - If the specified machine instruction has 185 /// a load from a stack slot, return true along with the FrameIndex 186 /// of the loaded stack slot and the machine mem operand containing 187 /// the reference. If not, return false. Unlike 188 /// isLoadFromStackSlot, this returns true for any instructions that 189 /// loads from the stack. This is just a hint, as some cases may be 190 /// missed. 191 virtual bool hasLoadFromStackSlot(const MachineInstr *MI, 192 const MachineMemOperand *&MMO, 193 int &FrameIndex) const { 194 return 0; 195 } 196 197 /// isStoreToStackSlot - If the specified machine instruction is a direct 198 /// store to a stack slot, return the virtual or physical register number of 199 /// the source reg along with the FrameIndex of the loaded stack slot. If 200 /// not, return 0. This predicate must return 0 if the instruction has 201 /// any side effects other than storing to the stack slot. 202 virtual unsigned isStoreToStackSlot(const MachineInstr *MI, 203 int &FrameIndex) const { 204 return 0; 205 } 206 207 /// isStoreToStackSlotPostFE - Check for post-frame ptr elimination 208 /// stack locations as well. This uses a heuristic so it isn't 209 /// reliable for correctness. 210 virtual unsigned isStoreToStackSlotPostFE(const MachineInstr *MI, 211 int &FrameIndex) const { 212 return 0; 213 } 214 215 /// hasStoreToStackSlot - If the specified machine instruction has a 216 /// store to a stack slot, return true along with the FrameIndex of 217 /// the loaded stack slot and the machine mem operand containing the 218 /// reference. If not, return false. Unlike isStoreToStackSlot, 219 /// this returns true for any instructions that loads from the 220 /// stack. This is just a hint, as some cases may be missed. 221 virtual bool hasStoreToStackSlot(const MachineInstr *MI, 222 const MachineMemOperand *&MMO, 223 int &FrameIndex) const { 224 return 0; 225 } 226 227 /// reMaterialize - Re-issue the specified 'original' instruction at the 228 /// specific location targeting a new destination register. 229 virtual void reMaterialize(MachineBasicBlock &MBB, 230 MachineBasicBlock::iterator MI, 231 unsigned DestReg, unsigned SubIdx, 232 const MachineInstr *Orig, 233 const TargetRegisterInfo *TRI) const = 0; 234 235 /// convertToThreeAddress - This method must be implemented by targets that 236 /// set the M_CONVERTIBLE_TO_3_ADDR flag. When this flag is set, the target 237 /// may be able to convert a two-address instruction into one or more true 238 /// three-address instructions on demand. This allows the X86 target (for 239 /// example) to convert ADD and SHL instructions into LEA instructions if they 240 /// would require register copies due to two-addressness. 241 /// 242 /// This method returns a null pointer if the transformation cannot be 243 /// performed, otherwise it returns the last new instruction. 244 /// 245 virtual MachineInstr * 246 convertToThreeAddress(MachineFunction::iterator &MFI, 247 MachineBasicBlock::iterator &MBBI, LiveVariables *LV) const { 248 return 0; 249 } 250 251 /// commuteInstruction - If a target has any instructions that are commutable, 252 /// but require converting to a different instruction or making non-trivial 253 /// changes to commute them, this method can overloaded to do this. The 254 /// default implementation of this method simply swaps the first two operands 255 /// of MI and returns it. 256 /// 257 /// If a target wants to make more aggressive changes, they can construct and 258 /// return a new machine instruction. If an instruction cannot commute, it 259 /// can also return null. 260 /// 261 /// If NewMI is true, then a new machine instruction must be created. 262 /// 263 virtual MachineInstr *commuteInstruction(MachineInstr *MI, 264 bool NewMI = false) const = 0; 265 266 /// findCommutedOpIndices - If specified MI is commutable, return the two 267 /// operand indices that would swap value. Return true if the instruction 268 /// is not in a form which this routine understands. 269 virtual bool findCommutedOpIndices(MachineInstr *MI, unsigned &SrcOpIdx1, 270 unsigned &SrcOpIdx2) const = 0; 271 272 /// isIdentical - Return true if two instructions are identical. This differs 273 /// from MachineInstr::isIdenticalTo() in that it does not require the 274 /// virtual destination registers to be the same. This is used by MachineLICM 275 /// and other MI passes to perform CSE. 276 virtual bool isIdentical(const MachineInstr *MI, 277 const MachineInstr *Other, 278 const MachineRegisterInfo *MRI) const = 0; 279 280 /// AnalyzeBranch - Analyze the branching code at the end of MBB, returning 281 /// true if it cannot be understood (e.g. it's a switch dispatch or isn't 282 /// implemented for a target). Upon success, this returns false and returns 283 /// with the following information in various cases: 284 /// 285 /// 1. If this block ends with no branches (it just falls through to its succ) 286 /// just return false, leaving TBB/FBB null. 287 /// 2. If this block ends with only an unconditional branch, it sets TBB to be 288 /// the destination block. 289 /// 3. If this block ends with an conditional branch and it falls through to 290 /// a successor block, it sets TBB to be the branch destination block and 291 /// a list of operands that evaluate the condition. These 292 /// operands can be passed to other TargetInstrInfo methods to create new 293 /// branches. 294 /// 4. If this block ends with a conditional branch followed by an 295 /// unconditional branch, it returns the 'true' destination in TBB, the 296 /// 'false' destination in FBB, and a list of operands that evaluate the 297 /// condition. These operands can be passed to other TargetInstrInfo 298 /// methods to create new branches. 299 /// 300 /// Note that RemoveBranch and InsertBranch must be implemented to support 301 /// cases where this method returns success. 302 /// 303 /// If AllowModify is true, then this routine is allowed to modify the basic 304 /// block (e.g. delete instructions after the unconditional branch). 305 /// 306 virtual bool AnalyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB, 307 MachineBasicBlock *&FBB, 308 SmallVectorImpl<MachineOperand> &Cond, 309 bool AllowModify = false) const { 310 return true; 311 } 312 313 /// RemoveBranch - Remove the branching code at the end of the specific MBB. 314 /// This is only invoked in cases where AnalyzeBranch returns success. It 315 /// returns the number of instructions that were removed. 316 virtual unsigned RemoveBranch(MachineBasicBlock &MBB) const { 317 assert(0 && "Target didn't implement TargetInstrInfo::RemoveBranch!"); 318 return 0; 319 } 320 321 /// InsertBranch - Insert branch code into the end of the specified 322 /// MachineBasicBlock. The operands to this method are the same as those 323 /// returned by AnalyzeBranch. This is only invoked in cases where 324 /// AnalyzeBranch returns success. It returns the number of instructions 325 /// inserted. 326 /// 327 /// It is also invoked by tail merging to add unconditional branches in 328 /// cases where AnalyzeBranch doesn't apply because there was no original 329 /// branch to analyze. At least this much must be implemented, else tail 330 /// merging needs to be disabled. 331 virtual unsigned InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB, 332 MachineBasicBlock *FBB, 333 const SmallVectorImpl<MachineOperand> &Cond) const { 334 assert(0 && "Target didn't implement TargetInstrInfo::InsertBranch!"); 335 return 0; 336 } 337 338 /// copyRegToReg - Emit instructions to copy between a pair of registers. It 339 /// returns false if the target does not how to copy between the specified 340 /// registers. 341 virtual bool copyRegToReg(MachineBasicBlock &MBB, 342 MachineBasicBlock::iterator MI, 343 unsigned DestReg, unsigned SrcReg, 344 const TargetRegisterClass *DestRC, 345 const TargetRegisterClass *SrcRC) const { 346 assert(0 && "Target didn't implement TargetInstrInfo::copyRegToReg!"); 347 return false; 348 } 349 350 /// storeRegToStackSlot - Store the specified register of the given register 351 /// class to the specified stack frame index. The store instruction is to be 352 /// added to the given machine basic block before the specified machine 353 /// instruction. If isKill is true, the register operand is the last use and 354 /// must be marked kill. 355 virtual void storeRegToStackSlot(MachineBasicBlock &MBB, 356 MachineBasicBlock::iterator MI, 357 unsigned SrcReg, bool isKill, int FrameIndex, 358 const TargetRegisterClass *RC) const { 359 assert(0 && "Target didn't implement TargetInstrInfo::storeRegToStackSlot!"); 360 } 361 362 /// loadRegFromStackSlot - Load the specified register of the given register 363 /// class from the specified stack frame index. The load instruction is to be 364 /// added to the given machine basic block before the specified machine 365 /// instruction. 366 virtual void loadRegFromStackSlot(MachineBasicBlock &MBB, 367 MachineBasicBlock::iterator MI, 368 unsigned DestReg, int FrameIndex, 369 const TargetRegisterClass *RC) const { 370 assert(0 && "Target didn't implement TargetInstrInfo::loadRegFromStackSlot!"); 371 } 372 373 /// spillCalleeSavedRegisters - Issues instruction(s) to spill all callee 374 /// saved registers and returns true if it isn't possible / profitable to do 375 /// so by issuing a series of store instructions via 376 /// storeRegToStackSlot(). Returns false otherwise. 377 virtual bool spillCalleeSavedRegisters(MachineBasicBlock &MBB, 378 MachineBasicBlock::iterator MI, 379 const std::vector<CalleeSavedInfo> &CSI) const { 380 return false; 381 } 382 383 /// restoreCalleeSavedRegisters - Issues instruction(s) to restore all callee 384 /// saved registers and returns true if it isn't possible / profitable to do 385 /// so by issuing a series of load instructions via loadRegToStackSlot(). 386 /// Returns false otherwise. 387 virtual bool restoreCalleeSavedRegisters(MachineBasicBlock &MBB, 388 MachineBasicBlock::iterator MI, 389 const std::vector<CalleeSavedInfo> &CSI) const { 390 return false; 391 } 392 393 /// foldMemoryOperand - Attempt to fold a load or store of the specified stack 394 /// slot into the specified machine instruction for the specified operand(s). 395 /// If this is possible, a new instruction is returned with the specified 396 /// operand folded, otherwise NULL is returned. The client is responsible for 397 /// removing the old instruction and adding the new one in the instruction 398 /// stream. 399 MachineInstr* foldMemoryOperand(MachineFunction &MF, 400 MachineInstr* MI, 401 const SmallVectorImpl<unsigned> &Ops, 402 int FrameIndex) const; 403 404 /// foldMemoryOperand - Same as the previous version except it allows folding 405 /// of any load and store from / to any address, not just from a specific 406 /// stack slot. 407 MachineInstr* foldMemoryOperand(MachineFunction &MF, 408 MachineInstr* MI, 409 const SmallVectorImpl<unsigned> &Ops, 410 MachineInstr* LoadMI) const; 411 412protected: 413 /// foldMemoryOperandImpl - Target-dependent implementation for 414 /// foldMemoryOperand. Target-independent code in foldMemoryOperand will 415 /// take care of adding a MachineMemOperand to the newly created instruction. 416 virtual MachineInstr* foldMemoryOperandImpl(MachineFunction &MF, 417 MachineInstr* MI, 418 const SmallVectorImpl<unsigned> &Ops, 419 int FrameIndex) const { 420 return 0; 421 } 422 423 /// foldMemoryOperandImpl - Target-dependent implementation for 424 /// foldMemoryOperand. Target-independent code in foldMemoryOperand will 425 /// take care of adding a MachineMemOperand to the newly created instruction. 426 virtual MachineInstr* foldMemoryOperandImpl(MachineFunction &MF, 427 MachineInstr* MI, 428 const SmallVectorImpl<unsigned> &Ops, 429 MachineInstr* LoadMI) const { 430 return 0; 431 } 432 433public: 434 /// canFoldMemoryOperand - Returns true for the specified load / store if 435 /// folding is possible. 436 virtual 437 bool canFoldMemoryOperand(const MachineInstr *MI, 438 const SmallVectorImpl<unsigned> &Ops) const { 439 return false; 440 } 441 442 /// unfoldMemoryOperand - Separate a single instruction which folded a load or 443 /// a store or a load and a store into two or more instruction. If this is 444 /// possible, returns true as well as the new instructions by reference. 445 virtual bool unfoldMemoryOperand(MachineFunction &MF, MachineInstr *MI, 446 unsigned Reg, bool UnfoldLoad, bool UnfoldStore, 447 SmallVectorImpl<MachineInstr*> &NewMIs) const{ 448 return false; 449 } 450 451 virtual bool unfoldMemoryOperand(SelectionDAG &DAG, SDNode *N, 452 SmallVectorImpl<SDNode*> &NewNodes) const { 453 return false; 454 } 455 456 /// getOpcodeAfterMemoryUnfold - Returns the opcode of the would be new 457 /// instruction after load / store are unfolded from an instruction of the 458 /// specified opcode. It returns zero if the specified unfolding is not 459 /// possible. If LoadRegIndex is non-null, it is filled in with the operand 460 /// index of the operand which will hold the register holding the loaded 461 /// value. 462 virtual unsigned getOpcodeAfterMemoryUnfold(unsigned Opc, 463 bool UnfoldLoad, bool UnfoldStore, 464 unsigned *LoadRegIndex = 0) const { 465 return 0; 466 } 467 468 /// BlockHasNoFallThrough - Return true if the specified block does not 469 /// fall-through into its successor block. This is primarily used when a 470 /// branch is unanalyzable. It is useful for things like unconditional 471 /// indirect branches (jump tables). 472 virtual bool BlockHasNoFallThrough(const MachineBasicBlock &MBB) const { 473 return false; 474 } 475 476 /// ReverseBranchCondition - Reverses the branch condition of the specified 477 /// condition list, returning false on success and true if it cannot be 478 /// reversed. 479 virtual 480 bool ReverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const { 481 return true; 482 } 483 484 /// insertNoop - Insert a noop into the instruction stream at the specified 485 /// point. 486 virtual void insertNoop(MachineBasicBlock &MBB, 487 MachineBasicBlock::iterator MI) const; 488 489 /// isPredicated - Returns true if the instruction is already predicated. 490 /// 491 virtual bool isPredicated(const MachineInstr *MI) const { 492 return false; 493 } 494 495 /// isUnpredicatedTerminator - Returns true if the instruction is a 496 /// terminator instruction that has not been predicated. 497 virtual bool isUnpredicatedTerminator(const MachineInstr *MI) const; 498 499 /// PredicateInstruction - Convert the instruction into a predicated 500 /// instruction. It returns true if the operation was successful. 501 virtual 502 bool PredicateInstruction(MachineInstr *MI, 503 const SmallVectorImpl<MachineOperand> &Pred) const = 0; 504 505 /// SubsumesPredicate - Returns true if the first specified predicate 506 /// subsumes the second, e.g. GE subsumes GT. 507 virtual 508 bool SubsumesPredicate(const SmallVectorImpl<MachineOperand> &Pred1, 509 const SmallVectorImpl<MachineOperand> &Pred2) const { 510 return false; 511 } 512 513 /// DefinesPredicate - If the specified instruction defines any predicate 514 /// or condition code register(s) used for predication, returns true as well 515 /// as the definition predicate(s) by reference. 516 virtual bool DefinesPredicate(MachineInstr *MI, 517 std::vector<MachineOperand> &Pred) const { 518 return false; 519 } 520 521 /// isPredicable - Return true if the specified instruction can be predicated. 522 /// By default, this returns true for every instruction with a 523 /// PredicateOperand. 524 virtual bool isPredicable(MachineInstr *MI) const { 525 return MI->getDesc().isPredicable(); 526 } 527 528 /// isSafeToMoveRegClassDefs - Return true if it's safe to move a machine 529 /// instruction that defines the specified register class. 530 virtual bool isSafeToMoveRegClassDefs(const TargetRegisterClass *RC) const { 531 return true; 532 } 533 534 /// GetInstSize - Returns the size of the specified Instruction. 535 /// 536 virtual unsigned GetInstSizeInBytes(const MachineInstr *MI) const { 537 assert(0 && "Target didn't implement TargetInstrInfo::GetInstSize!"); 538 return 0; 539 } 540 541 /// GetFunctionSizeInBytes - Returns the size of the specified 542 /// MachineFunction. 543 /// 544 virtual unsigned GetFunctionSizeInBytes(const MachineFunction &MF) const = 0; 545 546 /// Measure the specified inline asm to determine an approximation of its 547 /// length. 548 virtual unsigned getInlineAsmLength(const char *Str, 549 const MCAsmInfo &MAI) const; 550}; 551 552/// TargetInstrInfoImpl - This is the default implementation of 553/// TargetInstrInfo, which just provides a couple of default implementations 554/// for various methods. This separated out because it is implemented in 555/// libcodegen, not in libtarget. 556class TargetInstrInfoImpl : public TargetInstrInfo { 557protected: 558 TargetInstrInfoImpl(const TargetInstrDesc *desc, unsigned NumOpcodes) 559 : TargetInstrInfo(desc, NumOpcodes) {} 560public: 561 virtual MachineInstr *commuteInstruction(MachineInstr *MI, 562 bool NewMI = false) const; 563 virtual bool findCommutedOpIndices(MachineInstr *MI, unsigned &SrcOpIdx1, 564 unsigned &SrcOpIdx2) const; 565 virtual bool PredicateInstruction(MachineInstr *MI, 566 const SmallVectorImpl<MachineOperand> &Pred) const; 567 virtual void reMaterialize(MachineBasicBlock &MBB, 568 MachineBasicBlock::iterator MI, 569 unsigned DestReg, unsigned SubReg, 570 const MachineInstr *Orig, 571 const TargetRegisterInfo *TRI) const; 572 virtual bool isIdentical(const MachineInstr *MI, 573 const MachineInstr *Other, 574 const MachineRegisterInfo *MRI) const; 575 576 virtual unsigned GetFunctionSizeInBytes(const MachineFunction &MF) const; 577}; 578 579} // End llvm namespace 580 581#endif 582