TargetInstrInfo.h revision 6cee630070b1a7183ed56a8404e812629f5ca538
1//===-- llvm/Target/TargetInstrInfo.h - Instruction Info --------*- C++ -*-===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file was developed by the LLVM research group and is distributed under 6// the University of Illinois Open Source License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This file describes the target machine instructions to the code generator. 11// 12//===----------------------------------------------------------------------===// 13 14#ifndef LLVM_TARGET_TARGETINSTRINFO_H 15#define LLVM_TARGET_TARGETINSTRINFO_H 16 17#include "llvm/CodeGen/MachineBasicBlock.h" 18#include "llvm/Support/DataTypes.h" 19#include <vector> 20#include <cassert> 21 22namespace llvm { 23 24class MachineInstr; 25class TargetMachine; 26class Value; 27class Type; 28class Instruction; 29class Constant; 30class Function; 31class MachineCodeForInstruction; 32class TargetRegisterClass; 33 34//--------------------------------------------------------------------------- 35// Data types used to define information about a single machine instruction 36//--------------------------------------------------------------------------- 37 38typedef short MachineOpCode; 39typedef unsigned InstrSchedClass; 40 41//--------------------------------------------------------------------------- 42// struct TargetInstrDescriptor: 43// Predefined information about each machine instruction. 44// Designed to initialized statically. 45// 46 47const unsigned M_NOP_FLAG = 1 << 0; 48const unsigned M_BRANCH_FLAG = 1 << 1; 49const unsigned M_CALL_FLAG = 1 << 2; 50const unsigned M_RET_FLAG = 1 << 3; 51const unsigned M_BARRIER_FLAG = 1 << 4; 52const unsigned M_DELAY_SLOT_FLAG = 1 << 5; 53const unsigned M_CC_FLAG = 1 << 6; 54const unsigned M_LOAD_FLAG = 1 << 7; 55const unsigned M_STORE_FLAG = 1 << 8; 56 57// M_2_ADDR_FLAG - 3-addr instructions which really work like 2-addr ones. 58const unsigned M_2_ADDR_FLAG = 1 << 9; 59 60// M_CONVERTIBLE_TO_3_ADDR - This is a M_2_ADDR_FLAG instruction which can be 61// changed into a 3-address instruction if the first two operands cannot be 62// assigned to the same register. The target must implement the 63// TargetInstrInfo::convertToThreeAddress method for this instruction. 64const unsigned M_CONVERTIBLE_TO_3_ADDR = 1 << 10; 65 66// This M_COMMUTABLE - is a 2- or 3-address instruction (of the form X = op Y, 67// Z), which produces the same result if Y and Z are exchanged. 68const unsigned M_COMMUTABLE = 1 << 11; 69 70// M_TERMINATOR_FLAG - Is this instruction part of the terminator for a basic 71// block? Typically this is things like return and branch instructions. 72// Various passes use this to insert code into the bottom of a basic block, but 73// before control flow occurs. 74const unsigned M_TERMINATOR_FLAG = 1 << 12; 75 76// M_USES_CUSTOM_DAG_SCHED_INSERTION - Set if this instruction requires custom 77// insertion support when the DAG scheduler is inserting it into a machine basic 78// block. 79const unsigned M_USES_CUSTOM_DAG_SCHED_INSERTION = 1 << 13; 80 81/// TargetOperandInfo - This holds information about one operand of a machine 82/// instruction, indicating the register class for register operands, etc. 83/// 84class TargetOperandInfo { 85public: 86 /// RegClass - This specifies the register class of the operand if the 87 /// operand is a register. If not, this contains null. 88 const TargetRegisterClass *RegClass; 89 90 /// Currently no other information. 91}; 92 93 94class TargetInstrDescriptor { 95public: 96 const char * Name; // Assembly language mnemonic for the opcode. 97 int numOperands; // Number of args; -1 if variable #args 98 int resultPos; // Position of the result; -1 if no result 99 unsigned maxImmedConst; // Largest +ve constant in IMMED field or 0. 100 bool immedIsSignExtended; // Is IMMED field sign-extended? If so, 101 // smallest -ve value is -(maxImmedConst+1). 102 unsigned numDelaySlots; // Number of delay slots after instruction 103 unsigned latency; // Latency in machine cycles 104 InstrSchedClass schedClass; // enum identifying instr sched class 105 unsigned Flags; // flags identifying machine instr class 106 unsigned TSFlags; // Target Specific Flag values 107 const unsigned *ImplicitUses; // Registers implicitly read by this instr 108 const unsigned *ImplicitDefs; // Registers implicitly defined by this instr 109 const TargetOperandInfo *OpInfo; // 'numOperands' entries about operands. 110}; 111 112 113//--------------------------------------------------------------------------- 114/// 115/// TargetInstrInfo - Interface to description of machine instructions 116/// 117class TargetInstrInfo { 118 const TargetInstrDescriptor* desc; // raw array to allow static init'n 119 unsigned NumOpcodes; // number of entries in the desc array 120 unsigned numRealOpCodes; // number of non-dummy op codes 121 122 TargetInstrInfo(const TargetInstrInfo &); // DO NOT IMPLEMENT 123 void operator=(const TargetInstrInfo &); // DO NOT IMPLEMENT 124public: 125 TargetInstrInfo(const TargetInstrDescriptor *desc, unsigned NumOpcodes); 126 virtual ~TargetInstrInfo(); 127 128 // Invariant: All instruction sets use opcode #0 as the PHI instruction 129 enum { PHI = 0 }; 130 131 unsigned getNumOpcodes() const { return NumOpcodes; } 132 133 /// get - Return the machine instruction descriptor that corresponds to the 134 /// specified instruction opcode. 135 /// 136 const TargetInstrDescriptor& get(MachineOpCode Opcode) const { 137 assert((unsigned)Opcode < NumOpcodes); 138 return desc[Opcode]; 139 } 140 141 const char *getName(MachineOpCode Opcode) const { 142 return get(Opcode).Name; 143 } 144 145 int getNumOperands(MachineOpCode Opcode) const { 146 return get(Opcode).numOperands; 147 } 148 149 InstrSchedClass getSchedClass(MachineOpCode Opcode) const { 150 return get(Opcode).schedClass; 151 } 152 153 const unsigned *getImplicitUses(MachineOpCode Opcode) const { 154 return get(Opcode).ImplicitUses; 155 } 156 157 const unsigned *getImplicitDefs(MachineOpCode Opcode) const { 158 return get(Opcode).ImplicitDefs; 159 } 160 161 162 // 163 // Query instruction class flags according to the machine-independent 164 // flags listed above. 165 // 166 bool isReturn(MachineOpCode Opcode) const { 167 return get(Opcode).Flags & M_RET_FLAG; 168 } 169 170 bool isTwoAddrInstr(MachineOpCode Opcode) const { 171 return get(Opcode).Flags & M_2_ADDR_FLAG; 172 } 173 bool isTerminatorInstr(unsigned Opcode) const { 174 return get(Opcode).Flags & M_TERMINATOR_FLAG; 175 } 176 177 bool isBranch(MachineOpCode Opcode) const { 178 return get(Opcode).Flags & M_BRANCH_FLAG; 179 } 180 181 /// isBarrier - Returns true if the specified instruction stops control flow 182 /// from executing the instruction immediately following it. Examples include 183 /// unconditional branches and return instructions. 184 bool isBarrier(MachineOpCode Opcode) const { 185 return get(Opcode).Flags & M_BARRIER_FLAG; 186 } 187 188 bool isCall(MachineOpCode Opcode) const { 189 return get(Opcode).Flags & M_CALL_FLAG; 190 } 191 bool isLoad(MachineOpCode Opcode) const { 192 return get(Opcode).Flags & M_LOAD_FLAG; 193 } 194 bool isStore(MachineOpCode Opcode) const { 195 return get(Opcode).Flags & M_STORE_FLAG; 196 } 197 198 /// usesCustomDAGSchedInsertionHook - Return true if this instruction requires 199 /// custom insertion support when the DAG scheduler is inserting it into a 200 /// machine basic block. 201 bool usesCustomDAGSchedInsertionHook(unsigned Opcode) const { 202 return get(Opcode).Flags & M_USES_CUSTOM_DAG_SCHED_INSERTION; 203 } 204 205 /// Return true if the instruction is a register to register move 206 /// and leave the source and dest operands in the passed parameters. 207 virtual bool isMoveInstr(const MachineInstr& MI, 208 unsigned& sourceReg, 209 unsigned& destReg) const { 210 return false; 211 } 212 213 /// convertToThreeAddress - This method must be implemented by targets that 214 /// set the M_CONVERTIBLE_TO_3_ADDR flag. When this flag is set, the target 215 /// may be able to convert a two-address instruction into a true 216 /// three-address instruction on demand. This allows the X86 target (for 217 /// example) to convert ADD and SHL instructions into LEA instructions if they 218 /// would require register copies due to two-addressness. 219 /// 220 /// This method returns a null pointer if the transformation cannot be 221 /// performed, otherwise it returns the new instruction. 222 /// 223 virtual MachineInstr *convertToThreeAddress(MachineInstr *TA) const { 224 return 0; 225 } 226 227 /// commuteInstruction - If a target has any instructions that are commutable, 228 /// but require converting to a different instruction or making non-trivial 229 /// changes to commute them, this method can overloaded to do this. The 230 /// default implementation of this method simply swaps the first two operands 231 /// of MI and returns it. 232 /// 233 /// If a target wants to make more aggressive changes, they can construct and 234 /// return a new machine instruction. If an instruction cannot commute, it 235 /// can also return null. 236 /// 237 virtual MachineInstr *commuteInstruction(MachineInstr *MI) const; 238 239 /// Insert a goto (unconditional branch) sequence to TMBB, at the 240 /// end of MBB 241 virtual void insertGoto(MachineBasicBlock& MBB, 242 MachineBasicBlock& TMBB) const { 243 assert(0 && "Target didn't implement insertGoto!"); 244 } 245 246 /// Reverses the branch condition of the MachineInstr pointed by 247 /// MI. The instruction is replaced and the new MI is returned. 248 virtual MachineBasicBlock::iterator 249 reverseBranchCondition(MachineBasicBlock::iterator MI) const { 250 assert(0 && "Target didn't implement reverseBranchCondition!"); 251 abort(); 252 return MI; 253 } 254 255 256 //------------------------------------------------------------------------- 257 // Code generation support for creating individual machine instructions 258 // 259 // WARNING: These methods are Sparc specific 260 // 261 // DO NOT USE ANY OF THESE METHODS THEY ARE DEPRECATED! 262 // 263 //------------------------------------------------------------------------- 264 265 unsigned getNumDelaySlots(MachineOpCode Opcode) const { 266 return get(Opcode).numDelaySlots; 267 } 268 bool isCCInstr(MachineOpCode Opcode) const { 269 return get(Opcode).Flags & M_CC_FLAG; 270 } 271 bool isNop(MachineOpCode Opcode) const { 272 return get(Opcode).Flags & M_NOP_FLAG; 273 } 274 275 /// hasDelaySlot - Returns true if the specified instruction has a delay slot 276 /// which must be filled by the code generator. 277 bool hasDelaySlot(unsigned Opcode) const { 278 return get(Opcode).Flags & M_DELAY_SLOT_FLAG; 279 } 280 281 virtual bool hasResultInterlock(MachineOpCode Opcode) const { 282 return true; 283 } 284 285 // 286 // Latencies for individual instructions and instruction pairs 287 // 288 virtual int minLatency(MachineOpCode Opcode) const { 289 return get(Opcode).latency; 290 } 291 292 virtual int maxLatency(MachineOpCode Opcode) const { 293 return get(Opcode).latency; 294 } 295 296 // 297 // Which operand holds an immediate constant? Returns -1 if none 298 // 299 virtual int getImmedConstantPos(MachineOpCode Opcode) const { 300 return -1; // immediate position is machine specific, so say -1 == "none" 301 } 302 303 // Check if the specified constant fits in the immediate field 304 // of this machine instruction 305 // 306 virtual bool constantFitsInImmedField(MachineOpCode Opcode, 307 int64_t intValue) const; 308 309 // Return the largest positive constant that can be held in the IMMED field 310 // of this machine instruction. 311 // isSignExtended is set to true if the value is sign-extended before use 312 // (this is true for all immediate fields in SPARC instructions). 313 // Return 0 if the instruction has no IMMED field. 314 // 315 virtual uint64_t maxImmedConstant(MachineOpCode Opcode, 316 bool &isSignExtended) const { 317 isSignExtended = get(Opcode).immedIsSignExtended; 318 return get(Opcode).maxImmedConst; 319 } 320}; 321 322} // End llvm namespace 323 324#endif 325