TargetInstrInfo.h revision 834b08af8d3d8fc6c76ac6ca40674565689e8d7f
1//===-- llvm/Target/TargetInstrInfo.h - Instruction Info --------*- C++ -*-===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This file describes the target machine instruction set to the code generator. 11// 12//===----------------------------------------------------------------------===// 13 14#ifndef LLVM_TARGET_TARGETINSTRINFO_H 15#define LLVM_TARGET_TARGETINSTRINFO_H 16 17#include "llvm/Target/TargetInstrDesc.h" 18#include "llvm/CodeGen/MachineFunction.h" 19 20namespace llvm { 21 22class MCAsmInfo; 23class TargetRegisterClass; 24class TargetRegisterInfo; 25class LiveVariables; 26class CalleeSavedInfo; 27class SDNode; 28class SelectionDAG; 29 30template<class T> class SmallVectorImpl; 31 32 33//--------------------------------------------------------------------------- 34/// 35/// TargetInstrInfo - Interface to description of machine instruction set 36/// 37class TargetInstrInfo { 38 const TargetInstrDesc *Descriptors; // Raw array to allow static init'n 39 unsigned NumOpcodes; // Number of entries in the desc array 40 41 TargetInstrInfo(const TargetInstrInfo &); // DO NOT IMPLEMENT 42 void operator=(const TargetInstrInfo &); // DO NOT IMPLEMENT 43public: 44 TargetInstrInfo(const TargetInstrDesc *desc, unsigned NumOpcodes); 45 virtual ~TargetInstrInfo(); 46 47 // Invariant opcodes: All instruction sets have these as their low opcodes. 48 enum { 49 PHI = 0, 50 INLINEASM = 1, 51 DBG_LABEL = 2, 52 EH_LABEL = 3, 53 GC_LABEL = 4, 54 55 /// KILL - This instruction is a noop that is used only to adjust the liveness 56 /// of registers. This can be useful when dealing with sub-registers. 57 KILL = 5, 58 59 /// EXTRACT_SUBREG - This instruction takes two operands: a register 60 /// that has subregisters, and a subregister index. It returns the 61 /// extracted subregister value. This is commonly used to implement 62 /// truncation operations on target architectures which support it. 63 EXTRACT_SUBREG = 6, 64 65 /// INSERT_SUBREG - This instruction takes three operands: a register 66 /// that has subregisters, a register providing an insert value, and a 67 /// subregister index. It returns the value of the first register with 68 /// the value of the second register inserted. The first register is 69 /// often defined by an IMPLICIT_DEF, as is commonly used to implement 70 /// anyext operations on target architectures which support it. 71 INSERT_SUBREG = 7, 72 73 /// IMPLICIT_DEF - This is the MachineInstr-level equivalent of undef. 74 IMPLICIT_DEF = 8, 75 76 /// SUBREG_TO_REG - This instruction is similar to INSERT_SUBREG except 77 /// that the first operand is an immediate integer constant. This constant 78 /// is often zero, as is commonly used to implement zext operations on 79 /// target architectures which support it, such as with x86-64 (with 80 /// zext from i32 to i64 via implicit zero-extension). 81 SUBREG_TO_REG = 9, 82 83 /// COPY_TO_REGCLASS - This instruction is a placeholder for a plain 84 /// register-to-register copy into a specific register class. This is only 85 /// used between instruction selection and MachineInstr creation, before 86 /// virtual registers have been created for all the instructions, and it's 87 /// only needed in cases where the register classes implied by the 88 /// instructions are insufficient. The actual MachineInstrs to perform 89 /// the copy are emitted with the TargetInstrInfo::copyRegToReg hook. 90 COPY_TO_REGCLASS = 10 91 }; 92 93 unsigned getNumOpcodes() const { return NumOpcodes; } 94 95 /// get - Return the machine instruction descriptor that corresponds to the 96 /// specified instruction opcode. 97 /// 98 const TargetInstrDesc &get(unsigned Opcode) const { 99 assert(Opcode < NumOpcodes && "Invalid opcode!"); 100 return Descriptors[Opcode]; 101 } 102 103 /// isTriviallyReMaterializable - Return true if the instruction is trivially 104 /// rematerializable, meaning it has no side effects and requires no operands 105 /// that aren't always available. 106 bool isTriviallyReMaterializable(const MachineInstr *MI, 107 AliasAnalysis *AA = 0) const { 108 return MI->getOpcode() == IMPLICIT_DEF || 109 (MI->getDesc().isRematerializable() && 110 (isReallyTriviallyReMaterializable(MI, AA) || 111 isReallyTriviallyReMaterializableGeneric(MI, AA))); 112 } 113 114protected: 115 /// isReallyTriviallyReMaterializable - For instructions with opcodes for 116 /// which the M_REMATERIALIZABLE flag is set, this hook lets the target 117 /// specify whether the instruction is actually trivially rematerializable, 118 /// taking into consideration its operands. This predicate must return false 119 /// if the instruction has any side effects other than producing a value, or 120 /// if it requres any address registers that are not always available. 121 virtual bool isReallyTriviallyReMaterializable(const MachineInstr *MI, 122 AliasAnalysis *AA) const { 123 return false; 124 } 125 126private: 127 /// isReallyTriviallyReMaterializableGeneric - For instructions with opcodes 128 /// for which the M_REMATERIALIZABLE flag is set and the target hook 129 /// isReallyTriviallyReMaterializable returns false, this function does 130 /// target-independent tests to determine if the instruction is really 131 /// trivially rematerializable. 132 bool isReallyTriviallyReMaterializableGeneric(const MachineInstr *MI, 133 AliasAnalysis *AA) const; 134 135public: 136 /// isMoveInstr - Return true if the instruction is a register to register 137 /// move and return the source and dest operands and their sub-register 138 /// indices by reference. 139 virtual bool isMoveInstr(const MachineInstr& MI, 140 unsigned& SrcReg, unsigned& DstReg, 141 unsigned& SrcSubIdx, unsigned& DstSubIdx) const { 142 return false; 143 } 144 145 /// isIdentityCopy - Return true if the instruction is a copy (or 146 /// extract_subreg, insert_subreg, subreg_to_reg) where the source and 147 /// destination registers are the same. 148 bool isIdentityCopy(const MachineInstr &MI) const { 149 unsigned SrcReg, DstReg, SrcSubIdx, DstSubIdx; 150 if (isMoveInstr(MI, SrcReg, DstReg, SrcSubIdx, DstSubIdx) && 151 SrcReg == DstReg) 152 return true; 153 154 if (MI.getOpcode() == TargetInstrInfo::EXTRACT_SUBREG && 155 MI.getOperand(0).getReg() == MI.getOperand(1).getReg()) 156 return true; 157 158 if ((MI.getOpcode() == TargetInstrInfo::INSERT_SUBREG || 159 MI.getOpcode() == TargetInstrInfo::SUBREG_TO_REG) && 160 MI.getOperand(0).getReg() == MI.getOperand(2).getReg()) 161 return true; 162 return false; 163 } 164 165 /// isLoadFromStackSlot - If the specified machine instruction is a direct 166 /// load from a stack slot, return the virtual or physical register number of 167 /// the destination along with the FrameIndex of the loaded stack slot. If 168 /// not, return 0. This predicate must return 0 if the instruction has 169 /// any side effects other than loading from the stack slot. 170 virtual unsigned isLoadFromStackSlot(const MachineInstr *MI, 171 int &FrameIndex) const { 172 return 0; 173 } 174 175 /// isLoadFromStackSlotPostFE - Check for post-frame ptr elimination 176 /// stack locations as well. This uses a heuristic so it isn't 177 /// reliable for correctness. 178 virtual unsigned isLoadFromStackSlotPostFE(const MachineInstr *MI, 179 int &FrameIndex) const { 180 return 0; 181 } 182 183 /// hasLoadFromStackSlot - If the specified machine instruction has 184 /// a load from a stack slot, return true along with the FrameIndex 185 /// of the loaded stack slot. If not, return false. Unlike 186 /// isLoadFromStackSlot, this returns true for any instructions that 187 /// loads from the stack. This is just a hint, as some cases may be 188 /// missed. 189 virtual bool hasLoadFromStackSlot(const MachineInstr *MI, 190 int &FrameIndex) const { 191 return 0; 192 } 193 194 /// isStoreToStackSlot - If the specified machine instruction is a direct 195 /// store to a stack slot, return the virtual or physical register number of 196 /// the source reg along with the FrameIndex of the loaded stack slot. If 197 /// not, return 0. This predicate must return 0 if the instruction has 198 /// any side effects other than storing to the stack slot. 199 virtual unsigned isStoreToStackSlot(const MachineInstr *MI, 200 int &FrameIndex) const { 201 return 0; 202 } 203 204 /// isStoreToStackSlotPostFE - Check for post-frame ptr elimination 205 /// stack locations as well. This uses a heuristic so it isn't 206 /// reliable for correctness. 207 virtual unsigned isStoreToStackSlotPostFE(const MachineInstr *MI, 208 int &FrameIndex) const { 209 return 0; 210 } 211 212 /// hasStoreToStackSlot - If the specified machine instruction has a 213 /// store to a stack slot, return true along with the FrameIndex of 214 /// the loaded stack slot. If not, return false. Unlike 215 /// isStoreToStackSlot, this returns true for any instructions that 216 /// loads from the stack. This is just a hint, as some cases may be 217 /// missed. 218 virtual bool hasStoreToStackSlot(const MachineInstr *MI, 219 int &FrameIndex) const { 220 return 0; 221 } 222 223 /// reMaterialize - Re-issue the specified 'original' instruction at the 224 /// specific location targeting a new destination register. 225 virtual void reMaterialize(MachineBasicBlock &MBB, 226 MachineBasicBlock::iterator MI, 227 unsigned DestReg, unsigned SubIdx, 228 const MachineInstr *Orig, 229 const TargetRegisterInfo *TRI) const = 0; 230 231 /// convertToThreeAddress - This method must be implemented by targets that 232 /// set the M_CONVERTIBLE_TO_3_ADDR flag. When this flag is set, the target 233 /// may be able to convert a two-address instruction into one or more true 234 /// three-address instructions on demand. This allows the X86 target (for 235 /// example) to convert ADD and SHL instructions into LEA instructions if they 236 /// would require register copies due to two-addressness. 237 /// 238 /// This method returns a null pointer if the transformation cannot be 239 /// performed, otherwise it returns the last new instruction. 240 /// 241 virtual MachineInstr * 242 convertToThreeAddress(MachineFunction::iterator &MFI, 243 MachineBasicBlock::iterator &MBBI, LiveVariables *LV) const { 244 return 0; 245 } 246 247 /// commuteInstruction - If a target has any instructions that are commutable, 248 /// but require converting to a different instruction or making non-trivial 249 /// changes to commute them, this method can overloaded to do this. The 250 /// default implementation of this method simply swaps the first two operands 251 /// of MI and returns it. 252 /// 253 /// If a target wants to make more aggressive changes, they can construct and 254 /// return a new machine instruction. If an instruction cannot commute, it 255 /// can also return null. 256 /// 257 /// If NewMI is true, then a new machine instruction must be created. 258 /// 259 virtual MachineInstr *commuteInstruction(MachineInstr *MI, 260 bool NewMI = false) const = 0; 261 262 /// findCommutedOpIndices - If specified MI is commutable, return the two 263 /// operand indices that would swap value. Return true if the instruction 264 /// is not in a form which this routine understands. 265 virtual bool findCommutedOpIndices(MachineInstr *MI, unsigned &SrcOpIdx1, 266 unsigned &SrcOpIdx2) const = 0; 267 268 /// isIdentical - Return true if two instructions are identical. This differs 269 /// from MachineInstr::isIdenticalTo() in that it does not require the 270 /// virtual destination registers to be the same. This is used by MachineLICM 271 /// and other MI passes to perform CSE. 272 virtual bool isIdentical(const MachineInstr *MI, 273 const MachineInstr *Other, 274 const MachineRegisterInfo *MRI) const = 0; 275 276 /// AnalyzeBranch - Analyze the branching code at the end of MBB, returning 277 /// true if it cannot be understood (e.g. it's a switch dispatch or isn't 278 /// implemented for a target). Upon success, this returns false and returns 279 /// with the following information in various cases: 280 /// 281 /// 1. If this block ends with no branches (it just falls through to its succ) 282 /// just return false, leaving TBB/FBB null. 283 /// 2. If this block ends with only an unconditional branch, it sets TBB to be 284 /// the destination block. 285 /// 3. If this block ends with an conditional branch and it falls through to 286 /// a successor block, it sets TBB to be the branch destination block and 287 /// a list of operands that evaluate the condition. These 288 /// operands can be passed to other TargetInstrInfo methods to create new 289 /// branches. 290 /// 4. If this block ends with a conditional branch followed by an 291 /// unconditional branch, it returns the 'true' destination in TBB, the 292 /// 'false' destination in FBB, and a list of operands that evaluate the 293 /// condition. These operands can be passed to other TargetInstrInfo 294 /// methods to create new branches. 295 /// 296 /// Note that RemoveBranch and InsertBranch must be implemented to support 297 /// cases where this method returns success. 298 /// 299 /// If AllowModify is true, then this routine is allowed to modify the basic 300 /// block (e.g. delete instructions after the unconditional branch). 301 /// 302 virtual bool AnalyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB, 303 MachineBasicBlock *&FBB, 304 SmallVectorImpl<MachineOperand> &Cond, 305 bool AllowModify = false) const { 306 return true; 307 } 308 309 /// RemoveBranch - Remove the branching code at the end of the specific MBB. 310 /// This is only invoked in cases where AnalyzeBranch returns success. It 311 /// returns the number of instructions that were removed. 312 virtual unsigned RemoveBranch(MachineBasicBlock &MBB) const { 313 assert(0 && "Target didn't implement TargetInstrInfo::RemoveBranch!"); 314 return 0; 315 } 316 317 /// InsertBranch - Insert branch code into the end of the specified 318 /// MachineBasicBlock. The operands to this method are the same as those 319 /// returned by AnalyzeBranch. This is only invoked in cases where 320 /// AnalyzeBranch returns success. It returns the number of instructions 321 /// inserted. 322 /// 323 /// It is also invoked by tail merging to add unconditional branches in 324 /// cases where AnalyzeBranch doesn't apply because there was no original 325 /// branch to analyze. At least this much must be implemented, else tail 326 /// merging needs to be disabled. 327 virtual unsigned InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB, 328 MachineBasicBlock *FBB, 329 const SmallVectorImpl<MachineOperand> &Cond) const { 330 assert(0 && "Target didn't implement TargetInstrInfo::InsertBranch!"); 331 return 0; 332 } 333 334 /// copyRegToReg - Emit instructions to copy between a pair of registers. It 335 /// returns false if the target does not how to copy between the specified 336 /// registers. 337 virtual bool copyRegToReg(MachineBasicBlock &MBB, 338 MachineBasicBlock::iterator MI, 339 unsigned DestReg, unsigned SrcReg, 340 const TargetRegisterClass *DestRC, 341 const TargetRegisterClass *SrcRC) const { 342 assert(0 && "Target didn't implement TargetInstrInfo::copyRegToReg!"); 343 return false; 344 } 345 346 /// storeRegToStackSlot - Store the specified register of the given register 347 /// class to the specified stack frame index. The store instruction is to be 348 /// added to the given machine basic block before the specified machine 349 /// instruction. If isKill is true, the register operand is the last use and 350 /// must be marked kill. 351 virtual void storeRegToStackSlot(MachineBasicBlock &MBB, 352 MachineBasicBlock::iterator MI, 353 unsigned SrcReg, bool isKill, int FrameIndex, 354 const TargetRegisterClass *RC) const { 355 assert(0 && "Target didn't implement TargetInstrInfo::storeRegToStackSlot!"); 356 } 357 358 /// loadRegFromStackSlot - Load the specified register of the given register 359 /// class from the specified stack frame index. The load instruction is to be 360 /// added to the given machine basic block before the specified machine 361 /// instruction. 362 virtual void loadRegFromStackSlot(MachineBasicBlock &MBB, 363 MachineBasicBlock::iterator MI, 364 unsigned DestReg, int FrameIndex, 365 const TargetRegisterClass *RC) const { 366 assert(0 && "Target didn't implement TargetInstrInfo::loadRegFromStackSlot!"); 367 } 368 369 /// spillCalleeSavedRegisters - Issues instruction(s) to spill all callee 370 /// saved registers and returns true if it isn't possible / profitable to do 371 /// so by issuing a series of store instructions via 372 /// storeRegToStackSlot(). Returns false otherwise. 373 virtual bool spillCalleeSavedRegisters(MachineBasicBlock &MBB, 374 MachineBasicBlock::iterator MI, 375 const std::vector<CalleeSavedInfo> &CSI) const { 376 return false; 377 } 378 379 /// restoreCalleeSavedRegisters - Issues instruction(s) to restore all callee 380 /// saved registers and returns true if it isn't possible / profitable to do 381 /// so by issuing a series of load instructions via loadRegToStackSlot(). 382 /// Returns false otherwise. 383 virtual bool restoreCalleeSavedRegisters(MachineBasicBlock &MBB, 384 MachineBasicBlock::iterator MI, 385 const std::vector<CalleeSavedInfo> &CSI) const { 386 return false; 387 } 388 389 /// foldMemoryOperand - Attempt to fold a load or store of the specified stack 390 /// slot into the specified machine instruction for the specified operand(s). 391 /// If this is possible, a new instruction is returned with the specified 392 /// operand folded, otherwise NULL is returned. The client is responsible for 393 /// removing the old instruction and adding the new one in the instruction 394 /// stream. 395 MachineInstr* foldMemoryOperand(MachineFunction &MF, 396 MachineInstr* MI, 397 const SmallVectorImpl<unsigned> &Ops, 398 int FrameIndex) const; 399 400 /// foldMemoryOperand - Same as the previous version except it allows folding 401 /// of any load and store from / to any address, not just from a specific 402 /// stack slot. 403 MachineInstr* foldMemoryOperand(MachineFunction &MF, 404 MachineInstr* MI, 405 const SmallVectorImpl<unsigned> &Ops, 406 MachineInstr* LoadMI) const; 407 408protected: 409 /// foldMemoryOperandImpl - Target-dependent implementation for 410 /// foldMemoryOperand. Target-independent code in foldMemoryOperand will 411 /// take care of adding a MachineMemOperand to the newly created instruction. 412 virtual MachineInstr* foldMemoryOperandImpl(MachineFunction &MF, 413 MachineInstr* MI, 414 const SmallVectorImpl<unsigned> &Ops, 415 int FrameIndex) const { 416 return 0; 417 } 418 419 /// foldMemoryOperandImpl - Target-dependent implementation for 420 /// foldMemoryOperand. Target-independent code in foldMemoryOperand will 421 /// take care of adding a MachineMemOperand to the newly created instruction. 422 virtual MachineInstr* foldMemoryOperandImpl(MachineFunction &MF, 423 MachineInstr* MI, 424 const SmallVectorImpl<unsigned> &Ops, 425 MachineInstr* LoadMI) const { 426 return 0; 427 } 428 429public: 430 /// canFoldMemoryOperand - Returns true for the specified load / store if 431 /// folding is possible. 432 virtual 433 bool canFoldMemoryOperand(const MachineInstr *MI, 434 const SmallVectorImpl<unsigned> &Ops) const { 435 return false; 436 } 437 438 /// unfoldMemoryOperand - Separate a single instruction which folded a load or 439 /// a store or a load and a store into two or more instruction. If this is 440 /// possible, returns true as well as the new instructions by reference. 441 virtual bool unfoldMemoryOperand(MachineFunction &MF, MachineInstr *MI, 442 unsigned Reg, bool UnfoldLoad, bool UnfoldStore, 443 SmallVectorImpl<MachineInstr*> &NewMIs) const{ 444 return false; 445 } 446 447 virtual bool unfoldMemoryOperand(SelectionDAG &DAG, SDNode *N, 448 SmallVectorImpl<SDNode*> &NewNodes) const { 449 return false; 450 } 451 452 /// getOpcodeAfterMemoryUnfold - Returns the opcode of the would be new 453 /// instruction after load / store are unfolded from an instruction of the 454 /// specified opcode. It returns zero if the specified unfolding is not 455 /// possible. If LoadRegIndex is non-null, it is filled in with the operand 456 /// index of the operand which will hold the register holding the loaded 457 /// value. 458 virtual unsigned getOpcodeAfterMemoryUnfold(unsigned Opc, 459 bool UnfoldLoad, bool UnfoldStore, 460 unsigned *LoadRegIndex = 0) const { 461 return 0; 462 } 463 464 /// BlockHasNoFallThrough - Return true if the specified block does not 465 /// fall-through into its successor block. This is primarily used when a 466 /// branch is unanalyzable. It is useful for things like unconditional 467 /// indirect branches (jump tables). 468 virtual bool BlockHasNoFallThrough(const MachineBasicBlock &MBB) const { 469 return false; 470 } 471 472 /// ReverseBranchCondition - Reverses the branch condition of the specified 473 /// condition list, returning false on success and true if it cannot be 474 /// reversed. 475 virtual 476 bool ReverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const { 477 return true; 478 } 479 480 /// insertNoop - Insert a noop into the instruction stream at the specified 481 /// point. 482 virtual void insertNoop(MachineBasicBlock &MBB, 483 MachineBasicBlock::iterator MI) const; 484 485 /// isPredicated - Returns true if the instruction is already predicated. 486 /// 487 virtual bool isPredicated(const MachineInstr *MI) const { 488 return false; 489 } 490 491 /// isUnpredicatedTerminator - Returns true if the instruction is a 492 /// terminator instruction that has not been predicated. 493 virtual bool isUnpredicatedTerminator(const MachineInstr *MI) const; 494 495 /// PredicateInstruction - Convert the instruction into a predicated 496 /// instruction. It returns true if the operation was successful. 497 virtual 498 bool PredicateInstruction(MachineInstr *MI, 499 const SmallVectorImpl<MachineOperand> &Pred) const = 0; 500 501 /// SubsumesPredicate - Returns true if the first specified predicate 502 /// subsumes the second, e.g. GE subsumes GT. 503 virtual 504 bool SubsumesPredicate(const SmallVectorImpl<MachineOperand> &Pred1, 505 const SmallVectorImpl<MachineOperand> &Pred2) const { 506 return false; 507 } 508 509 /// DefinesPredicate - If the specified instruction defines any predicate 510 /// or condition code register(s) used for predication, returns true as well 511 /// as the definition predicate(s) by reference. 512 virtual bool DefinesPredicate(MachineInstr *MI, 513 std::vector<MachineOperand> &Pred) const { 514 return false; 515 } 516 517 /// isSafeToMoveRegClassDefs - Return true if it's safe to move a machine 518 /// instruction that defines the specified register class. 519 virtual bool isSafeToMoveRegClassDefs(const TargetRegisterClass *RC) const { 520 return true; 521 } 522 523 /// GetInstSize - Returns the size of the specified Instruction. 524 /// 525 virtual unsigned GetInstSizeInBytes(const MachineInstr *MI) const { 526 assert(0 && "Target didn't implement TargetInstrInfo::GetInstSize!"); 527 return 0; 528 } 529 530 /// GetFunctionSizeInBytes - Returns the size of the specified 531 /// MachineFunction. 532 /// 533 virtual unsigned GetFunctionSizeInBytes(const MachineFunction &MF) const = 0; 534 535 /// Measure the specified inline asm to determine an approximation of its 536 /// length. 537 virtual unsigned getInlineAsmLength(const char *Str, 538 const MCAsmInfo &MAI) const; 539 540 /// TailDuplicationLimit - Returns the limit on the number of instructions 541 /// in basic block MBB beyond which it will not be tail-duplicated. 542 virtual unsigned TailDuplicationLimit(const MachineBasicBlock &MBB, 543 unsigned DefaultLimit) const { 544 return DefaultLimit; 545 } 546}; 547 548/// TargetInstrInfoImpl - This is the default implementation of 549/// TargetInstrInfo, which just provides a couple of default implementations 550/// for various methods. This separated out because it is implemented in 551/// libcodegen, not in libtarget. 552class TargetInstrInfoImpl : public TargetInstrInfo { 553protected: 554 TargetInstrInfoImpl(const TargetInstrDesc *desc, unsigned NumOpcodes) 555 : TargetInstrInfo(desc, NumOpcodes) {} 556public: 557 virtual MachineInstr *commuteInstruction(MachineInstr *MI, 558 bool NewMI = false) const; 559 virtual bool findCommutedOpIndices(MachineInstr *MI, unsigned &SrcOpIdx1, 560 unsigned &SrcOpIdx2) const; 561 virtual bool PredicateInstruction(MachineInstr *MI, 562 const SmallVectorImpl<MachineOperand> &Pred) const; 563 virtual void reMaterialize(MachineBasicBlock &MBB, 564 MachineBasicBlock::iterator MI, 565 unsigned DestReg, unsigned SubReg, 566 const MachineInstr *Orig, 567 const TargetRegisterInfo *TRI) const; 568 virtual bool isIdentical(const MachineInstr *MI, 569 const MachineInstr *Other, 570 const MachineRegisterInfo *MRI) const; 571 572 virtual unsigned GetFunctionSizeInBytes(const MachineFunction &MF) const; 573}; 574 575} // End llvm namespace 576 577#endif 578