TargetInstrInfo.h revision 85de1e5bade2f3755e47ed6fd43c92fcf99ff08b
1//===-- llvm/Target/TargetInstrInfo.h - Instruction Info --------*- C++ -*-===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This file describes the target machine instruction set to the code generator. 11// 12//===----------------------------------------------------------------------===// 13 14#ifndef LLVM_TARGET_TARGETINSTRINFO_H 15#define LLVM_TARGET_TARGETINSTRINFO_H 16 17#include "llvm/Target/TargetInstrDesc.h" 18#include "llvm/CodeGen/MachineFunction.h" 19 20namespace llvm { 21 22class MCAsmInfo; 23class TargetRegisterClass; 24class TargetRegisterInfo; 25class LiveVariables; 26class CalleeSavedInfo; 27class SDNode; 28class SelectionDAG; 29class MachineMemOperand; 30 31template<class T> class SmallVectorImpl; 32 33 34//--------------------------------------------------------------------------- 35/// 36/// TargetInstrInfo - Interface to description of machine instruction set 37/// 38class TargetInstrInfo { 39 const TargetInstrDesc *Descriptors; // Raw array to allow static init'n 40 unsigned NumOpcodes; // Number of entries in the desc array 41 42 TargetInstrInfo(const TargetInstrInfo &); // DO NOT IMPLEMENT 43 void operator=(const TargetInstrInfo &); // DO NOT IMPLEMENT 44public: 45 TargetInstrInfo(const TargetInstrDesc *desc, unsigned NumOpcodes); 46 virtual ~TargetInstrInfo(); 47 48 // Invariant opcodes: All instruction sets have these as their low opcodes. 49 enum { 50 PHI = 0, 51 INLINEASM = 1, 52 DBG_LABEL = 2, 53 EH_LABEL = 3, 54 GC_LABEL = 4, 55 56 /// KILL - This instruction is a noop that is used only to adjust the liveness 57 /// of registers. This can be useful when dealing with sub-registers. 58 KILL = 5, 59 60 /// EXTRACT_SUBREG - This instruction takes two operands: a register 61 /// that has subregisters, and a subregister index. It returns the 62 /// extracted subregister value. This is commonly used to implement 63 /// truncation operations on target architectures which support it. 64 EXTRACT_SUBREG = 6, 65 66 /// INSERT_SUBREG - This instruction takes three operands: a register 67 /// that has subregisters, a register providing an insert value, and a 68 /// subregister index. It returns the value of the first register with 69 /// the value of the second register inserted. The first register is 70 /// often defined by an IMPLICIT_DEF, as is commonly used to implement 71 /// anyext operations on target architectures which support it. 72 INSERT_SUBREG = 7, 73 74 /// IMPLICIT_DEF - This is the MachineInstr-level equivalent of undef. 75 IMPLICIT_DEF = 8, 76 77 /// SUBREG_TO_REG - This instruction is similar to INSERT_SUBREG except 78 /// that the first operand is an immediate integer constant. This constant 79 /// is often zero, as is commonly used to implement zext operations on 80 /// target architectures which support it, such as with x86-64 (with 81 /// zext from i32 to i64 via implicit zero-extension). 82 SUBREG_TO_REG = 9, 83 84 /// COPY_TO_REGCLASS - This instruction is a placeholder for a plain 85 /// register-to-register copy into a specific register class. This is only 86 /// used between instruction selection and MachineInstr creation, before 87 /// virtual registers have been created for all the instructions, and it's 88 /// only needed in cases where the register classes implied by the 89 /// instructions are insufficient. The actual MachineInstrs to perform 90 /// the copy are emitted with the TargetInstrInfo::copyRegToReg hook. 91 COPY_TO_REGCLASS = 10 92 }; 93 94 unsigned getNumOpcodes() const { return NumOpcodes; } 95 96 /// get - Return the machine instruction descriptor that corresponds to the 97 /// specified instruction opcode. 98 /// 99 const TargetInstrDesc &get(unsigned Opcode) const { 100 assert(Opcode < NumOpcodes && "Invalid opcode!"); 101 return Descriptors[Opcode]; 102 } 103 104 /// isTriviallyReMaterializable - Return true if the instruction is trivially 105 /// rematerializable, meaning it has no side effects and requires no operands 106 /// that aren't always available. 107 bool isTriviallyReMaterializable(const MachineInstr *MI, 108 AliasAnalysis *AA = 0) const { 109 return MI->getOpcode() == IMPLICIT_DEF || 110 (MI->getDesc().isRematerializable() && 111 (isReallyTriviallyReMaterializable(MI, AA) || 112 isReallyTriviallyReMaterializableGeneric(MI, AA))); 113 } 114 115protected: 116 /// isReallyTriviallyReMaterializable - For instructions with opcodes for 117 /// which the M_REMATERIALIZABLE flag is set, this hook lets the target 118 /// specify whether the instruction is actually trivially rematerializable, 119 /// taking into consideration its operands. This predicate must return false 120 /// if the instruction has any side effects other than producing a value, or 121 /// if it requres any address registers that are not always available. 122 virtual bool isReallyTriviallyReMaterializable(const MachineInstr *MI, 123 AliasAnalysis *AA) const { 124 return false; 125 } 126 127private: 128 /// isReallyTriviallyReMaterializableGeneric - For instructions with opcodes 129 /// for which the M_REMATERIALIZABLE flag is set and the target hook 130 /// isReallyTriviallyReMaterializable returns false, this function does 131 /// target-independent tests to determine if the instruction is really 132 /// trivially rematerializable. 133 bool isReallyTriviallyReMaterializableGeneric(const MachineInstr *MI, 134 AliasAnalysis *AA) const; 135 136public: 137 /// isMoveInstr - Return true if the instruction is a register to register 138 /// move and return the source and dest operands and their sub-register 139 /// indices by reference. 140 virtual bool isMoveInstr(const MachineInstr& MI, 141 unsigned& SrcReg, unsigned& DstReg, 142 unsigned& SrcSubIdx, unsigned& DstSubIdx) const { 143 return false; 144 } 145 146 /// isIdentityCopy - Return true if the instruction is a copy (or 147 /// extract_subreg, insert_subreg, subreg_to_reg) where the source and 148 /// destination registers are the same. 149 bool isIdentityCopy(const MachineInstr &MI) const { 150 unsigned SrcReg, DstReg, SrcSubIdx, DstSubIdx; 151 if (isMoveInstr(MI, SrcReg, DstReg, SrcSubIdx, DstSubIdx) && 152 SrcReg == DstReg) 153 return true; 154 155 if (MI.getOpcode() == TargetInstrInfo::EXTRACT_SUBREG && 156 MI.getOperand(0).getReg() == MI.getOperand(1).getReg()) 157 return true; 158 159 if ((MI.getOpcode() == TargetInstrInfo::INSERT_SUBREG || 160 MI.getOpcode() == TargetInstrInfo::SUBREG_TO_REG) && 161 MI.getOperand(0).getReg() == MI.getOperand(2).getReg()) 162 return true; 163 return false; 164 } 165 166 /// isLoadFromStackSlot - If the specified machine instruction is a direct 167 /// load from a stack slot, return the virtual or physical register number of 168 /// the destination along with the FrameIndex of the loaded stack slot. If 169 /// not, return 0. This predicate must return 0 if the instruction has 170 /// any side effects other than loading from the stack slot. 171 virtual unsigned isLoadFromStackSlot(const MachineInstr *MI, 172 int &FrameIndex) const { 173 return 0; 174 } 175 176 /// isLoadFromStackSlotPostFE - Check for post-frame ptr elimination 177 /// stack locations as well. This uses a heuristic so it isn't 178 /// reliable for correctness. 179 virtual unsigned isLoadFromStackSlotPostFE(const MachineInstr *MI, 180 int &FrameIndex) const { 181 return 0; 182 } 183 184 /// hasLoadFromStackSlot - If the specified machine instruction has 185 /// a load from a stack slot, return true along with the FrameIndex 186 /// of the loaded stack slot and the machine mem operand containing 187 /// the reference. If not, return false. Unlike 188 /// isLoadFromStackSlot, this returns true for any instructions that 189 /// loads from the stack. This is just a hint, as some cases may be 190 /// missed. 191 virtual bool hasLoadFromStackSlot(const MachineInstr *MI, 192 const MachineMemOperand *&MMO, 193 int &FrameIndex) const { 194 return 0; 195 } 196 197 /// isStoreToStackSlot - If the specified machine instruction is a direct 198 /// store to a stack slot, return the virtual or physical register number of 199 /// the source reg along with the FrameIndex of the loaded stack slot. If 200 /// not, return 0. This predicate must return 0 if the instruction has 201 /// any side effects other than storing to the stack slot. 202 virtual unsigned isStoreToStackSlot(const MachineInstr *MI, 203 int &FrameIndex) const { 204 return 0; 205 } 206 207 /// isStoreToStackSlotPostFE - Check for post-frame ptr elimination 208 /// stack locations as well. This uses a heuristic so it isn't 209 /// reliable for correctness. 210 virtual unsigned isStoreToStackSlotPostFE(const MachineInstr *MI, 211 int &FrameIndex) const { 212 return 0; 213 } 214 215 /// hasStoreToStackSlot - If the specified machine instruction has a 216 /// store to a stack slot, return true along with the FrameIndex of 217 /// the loaded stack slot and the machine mem operand containing the 218 /// reference. If not, return false. Unlike isStoreToStackSlot, 219 /// this returns true for any instructions that loads from the 220 /// stack. This is just a hint, as some cases may be missed. 221 virtual bool hasStoreToStackSlot(const MachineInstr *MI, 222 const MachineMemOperand *&MMO, 223 int &FrameIndex) const { 224 return 0; 225 } 226 227 /// reMaterialize - Re-issue the specified 'original' instruction at the 228 /// specific location targeting a new destination register. 229 virtual void reMaterialize(MachineBasicBlock &MBB, 230 MachineBasicBlock::iterator MI, 231 unsigned DestReg, unsigned SubIdx, 232 const MachineInstr *Orig, 233 const TargetRegisterInfo *TRI) const = 0; 234 235 /// convertToThreeAddress - This method must be implemented by targets that 236 /// set the M_CONVERTIBLE_TO_3_ADDR flag. When this flag is set, the target 237 /// may be able to convert a two-address instruction into one or more true 238 /// three-address instructions on demand. This allows the X86 target (for 239 /// example) to convert ADD and SHL instructions into LEA instructions if they 240 /// would require register copies due to two-addressness. 241 /// 242 /// This method returns a null pointer if the transformation cannot be 243 /// performed, otherwise it returns the last new instruction. 244 /// 245 virtual MachineInstr * 246 convertToThreeAddress(MachineFunction::iterator &MFI, 247 MachineBasicBlock::iterator &MBBI, LiveVariables *LV) const { 248 return 0; 249 } 250 251 /// commuteInstruction - If a target has any instructions that are commutable, 252 /// but require converting to a different instruction or making non-trivial 253 /// changes to commute them, this method can overloaded to do this. The 254 /// default implementation of this method simply swaps the first two operands 255 /// of MI and returns it. 256 /// 257 /// If a target wants to make more aggressive changes, they can construct and 258 /// return a new machine instruction. If an instruction cannot commute, it 259 /// can also return null. 260 /// 261 /// If NewMI is true, then a new machine instruction must be created. 262 /// 263 virtual MachineInstr *commuteInstruction(MachineInstr *MI, 264 bool NewMI = false) const = 0; 265 266 /// findCommutedOpIndices - If specified MI is commutable, return the two 267 /// operand indices that would swap value. Return true if the instruction 268 /// is not in a form which this routine understands. 269 virtual bool findCommutedOpIndices(MachineInstr *MI, unsigned &SrcOpIdx1, 270 unsigned &SrcOpIdx2) const = 0; 271 272 /// isIdentical - Return true if two instructions are identical. This differs 273 /// from MachineInstr::isIdenticalTo() in that it does not require the 274 /// virtual destination registers to be the same. This is used by MachineLICM 275 /// and other MI passes to perform CSE. 276 virtual bool isIdentical(const MachineInstr *MI, 277 const MachineInstr *Other, 278 const MachineRegisterInfo *MRI) const = 0; 279 280 /// AnalyzeBranch - Analyze the branching code at the end of MBB, returning 281 /// true if it cannot be understood (e.g. it's a switch dispatch or isn't 282 /// implemented for a target). Upon success, this returns false and returns 283 /// with the following information in various cases: 284 /// 285 /// 1. If this block ends with no branches (it just falls through to its succ) 286 /// just return false, leaving TBB/FBB null. 287 /// 2. If this block ends with only an unconditional branch, it sets TBB to be 288 /// the destination block. 289 /// 3. If this block ends with a conditional branch and it falls through to a 290 /// successor block, it sets TBB to be the branch destination block and a 291 /// list of operands that evaluate the condition. These operands can be 292 /// passed to other TargetInstrInfo methods to create new branches. 293 /// 4. If this block ends with a conditional branch followed by an 294 /// unconditional branch, it returns the 'true' destination in TBB, the 295 /// 'false' destination in FBB, and a list of operands that evaluate the 296 /// condition. These operands can be passed to other TargetInstrInfo 297 /// methods to create new branches. 298 /// 299 /// Note that RemoveBranch and InsertBranch must be implemented to support 300 /// cases where this method returns success. 301 /// 302 /// If AllowModify is true, then this routine is allowed to modify the basic 303 /// block (e.g. delete instructions after the unconditional branch). 304 /// 305 virtual bool AnalyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB, 306 MachineBasicBlock *&FBB, 307 SmallVectorImpl<MachineOperand> &Cond, 308 bool AllowModify = false) const { 309 return true; 310 } 311 312 /// RemoveBranch - Remove the branching code at the end of the specific MBB. 313 /// This is only invoked in cases where AnalyzeBranch returns success. It 314 /// returns the number of instructions that were removed. 315 virtual unsigned RemoveBranch(MachineBasicBlock &MBB) const { 316 assert(0 && "Target didn't implement TargetInstrInfo::RemoveBranch!"); 317 return 0; 318 } 319 320 /// InsertBranch - Insert branch code into the end of the specified 321 /// MachineBasicBlock. The operands to this method are the same as those 322 /// returned by AnalyzeBranch. This is only invoked in cases where 323 /// AnalyzeBranch returns success. It returns the number of instructions 324 /// inserted. 325 /// 326 /// It is also invoked by tail merging to add unconditional branches in 327 /// cases where AnalyzeBranch doesn't apply because there was no original 328 /// branch to analyze. At least this much must be implemented, else tail 329 /// merging needs to be disabled. 330 virtual unsigned InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB, 331 MachineBasicBlock *FBB, 332 const SmallVectorImpl<MachineOperand> &Cond) const { 333 assert(0 && "Target didn't implement TargetInstrInfo::InsertBranch!"); 334 return 0; 335 } 336 337 /// copyRegToReg - Emit instructions to copy between a pair of registers. It 338 /// returns false if the target does not how to copy between the specified 339 /// registers. 340 virtual bool copyRegToReg(MachineBasicBlock &MBB, 341 MachineBasicBlock::iterator MI, 342 unsigned DestReg, unsigned SrcReg, 343 const TargetRegisterClass *DestRC, 344 const TargetRegisterClass *SrcRC) const { 345 assert(0 && "Target didn't implement TargetInstrInfo::copyRegToReg!"); 346 return false; 347 } 348 349 /// storeRegToStackSlot - Store the specified register of the given register 350 /// class to the specified stack frame index. The store instruction is to be 351 /// added to the given machine basic block before the specified machine 352 /// instruction. If isKill is true, the register operand is the last use and 353 /// must be marked kill. 354 virtual void storeRegToStackSlot(MachineBasicBlock &MBB, 355 MachineBasicBlock::iterator MI, 356 unsigned SrcReg, bool isKill, int FrameIndex, 357 const TargetRegisterClass *RC) const { 358 assert(0 && "Target didn't implement TargetInstrInfo::storeRegToStackSlot!"); 359 } 360 361 /// loadRegFromStackSlot - Load the specified register of the given register 362 /// class from the specified stack frame index. The load instruction is to be 363 /// added to the given machine basic block before the specified machine 364 /// instruction. 365 virtual void loadRegFromStackSlot(MachineBasicBlock &MBB, 366 MachineBasicBlock::iterator MI, 367 unsigned DestReg, int FrameIndex, 368 const TargetRegisterClass *RC) const { 369 assert(0 && "Target didn't implement TargetInstrInfo::loadRegFromStackSlot!"); 370 } 371 372 /// spillCalleeSavedRegisters - Issues instruction(s) to spill all callee 373 /// saved registers and returns true if it isn't possible / profitable to do 374 /// so by issuing a series of store instructions via 375 /// storeRegToStackSlot(). Returns false otherwise. 376 virtual bool spillCalleeSavedRegisters(MachineBasicBlock &MBB, 377 MachineBasicBlock::iterator MI, 378 const std::vector<CalleeSavedInfo> &CSI) const { 379 return false; 380 } 381 382 /// restoreCalleeSavedRegisters - Issues instruction(s) to restore all callee 383 /// saved registers and returns true if it isn't possible / profitable to do 384 /// so by issuing a series of load instructions via loadRegToStackSlot(). 385 /// Returns false otherwise. 386 virtual bool restoreCalleeSavedRegisters(MachineBasicBlock &MBB, 387 MachineBasicBlock::iterator MI, 388 const std::vector<CalleeSavedInfo> &CSI) const { 389 return false; 390 } 391 392 /// foldMemoryOperand - Attempt to fold a load or store of the specified stack 393 /// slot into the specified machine instruction for the specified operand(s). 394 /// If this is possible, a new instruction is returned with the specified 395 /// operand folded, otherwise NULL is returned. The client is responsible for 396 /// removing the old instruction and adding the new one in the instruction 397 /// stream. 398 MachineInstr* foldMemoryOperand(MachineFunction &MF, 399 MachineInstr* MI, 400 const SmallVectorImpl<unsigned> &Ops, 401 int FrameIndex) const; 402 403 /// foldMemoryOperand - Same as the previous version except it allows folding 404 /// of any load and store from / to any address, not just from a specific 405 /// stack slot. 406 MachineInstr* foldMemoryOperand(MachineFunction &MF, 407 MachineInstr* MI, 408 const SmallVectorImpl<unsigned> &Ops, 409 MachineInstr* LoadMI) const; 410 411protected: 412 /// foldMemoryOperandImpl - Target-dependent implementation for 413 /// foldMemoryOperand. Target-independent code in foldMemoryOperand will 414 /// take care of adding a MachineMemOperand to the newly created instruction. 415 virtual MachineInstr* foldMemoryOperandImpl(MachineFunction &MF, 416 MachineInstr* MI, 417 const SmallVectorImpl<unsigned> &Ops, 418 int FrameIndex) const { 419 return 0; 420 } 421 422 /// foldMemoryOperandImpl - Target-dependent implementation for 423 /// foldMemoryOperand. Target-independent code in foldMemoryOperand will 424 /// take care of adding a MachineMemOperand to the newly created instruction. 425 virtual MachineInstr* foldMemoryOperandImpl(MachineFunction &MF, 426 MachineInstr* MI, 427 const SmallVectorImpl<unsigned> &Ops, 428 MachineInstr* LoadMI) const { 429 return 0; 430 } 431 432public: 433 /// canFoldMemoryOperand - Returns true for the specified load / store if 434 /// folding is possible. 435 virtual 436 bool canFoldMemoryOperand(const MachineInstr *MI, 437 const SmallVectorImpl<unsigned> &Ops) const { 438 return false; 439 } 440 441 /// unfoldMemoryOperand - Separate a single instruction which folded a load or 442 /// a store or a load and a store into two or more instruction. If this is 443 /// possible, returns true as well as the new instructions by reference. 444 virtual bool unfoldMemoryOperand(MachineFunction &MF, MachineInstr *MI, 445 unsigned Reg, bool UnfoldLoad, bool UnfoldStore, 446 SmallVectorImpl<MachineInstr*> &NewMIs) const{ 447 return false; 448 } 449 450 virtual bool unfoldMemoryOperand(SelectionDAG &DAG, SDNode *N, 451 SmallVectorImpl<SDNode*> &NewNodes) const { 452 return false; 453 } 454 455 /// getOpcodeAfterMemoryUnfold - Returns the opcode of the would be new 456 /// instruction after load / store are unfolded from an instruction of the 457 /// specified opcode. It returns zero if the specified unfolding is not 458 /// possible. If LoadRegIndex is non-null, it is filled in with the operand 459 /// index of the operand which will hold the register holding the loaded 460 /// value. 461 virtual unsigned getOpcodeAfterMemoryUnfold(unsigned Opc, 462 bool UnfoldLoad, bool UnfoldStore, 463 unsigned *LoadRegIndex = 0) const { 464 return 0; 465 } 466 467 /// ReverseBranchCondition - Reverses the branch condition of the specified 468 /// condition list, returning false on success and true if it cannot be 469 /// reversed. 470 virtual 471 bool ReverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const { 472 return true; 473 } 474 475 /// insertNoop - Insert a noop into the instruction stream at the specified 476 /// point. 477 virtual void insertNoop(MachineBasicBlock &MBB, 478 MachineBasicBlock::iterator MI) const; 479 480 /// isPredicated - Returns true if the instruction is already predicated. 481 /// 482 virtual bool isPredicated(const MachineInstr *MI) const { 483 return false; 484 } 485 486 /// isUnpredicatedTerminator - Returns true if the instruction is a 487 /// terminator instruction that has not been predicated. 488 virtual bool isUnpredicatedTerminator(const MachineInstr *MI) const; 489 490 /// PredicateInstruction - Convert the instruction into a predicated 491 /// instruction. It returns true if the operation was successful. 492 virtual 493 bool PredicateInstruction(MachineInstr *MI, 494 const SmallVectorImpl<MachineOperand> &Pred) const = 0; 495 496 /// SubsumesPredicate - Returns true if the first specified predicate 497 /// subsumes the second, e.g. GE subsumes GT. 498 virtual 499 bool SubsumesPredicate(const SmallVectorImpl<MachineOperand> &Pred1, 500 const SmallVectorImpl<MachineOperand> &Pred2) const { 501 return false; 502 } 503 504 /// DefinesPredicate - If the specified instruction defines any predicate 505 /// or condition code register(s) used for predication, returns true as well 506 /// as the definition predicate(s) by reference. 507 virtual bool DefinesPredicate(MachineInstr *MI, 508 std::vector<MachineOperand> &Pred) const { 509 return false; 510 } 511 512 /// isPredicable - Return true if the specified instruction can be predicated. 513 /// By default, this returns true for every instruction with a 514 /// PredicateOperand. 515 virtual bool isPredicable(MachineInstr *MI) const { 516 return MI->getDesc().isPredicable(); 517 } 518 519 /// isSafeToMoveRegClassDefs - Return true if it's safe to move a machine 520 /// instruction that defines the specified register class. 521 virtual bool isSafeToMoveRegClassDefs(const TargetRegisterClass *RC) const { 522 return true; 523 } 524 525 /// GetInstSize - Returns the size of the specified Instruction. 526 /// 527 virtual unsigned GetInstSizeInBytes(const MachineInstr *MI) const { 528 assert(0 && "Target didn't implement TargetInstrInfo::GetInstSize!"); 529 return 0; 530 } 531 532 /// GetFunctionSizeInBytes - Returns the size of the specified 533 /// MachineFunction. 534 /// 535 virtual unsigned GetFunctionSizeInBytes(const MachineFunction &MF) const = 0; 536 537 /// Measure the specified inline asm to determine an approximation of its 538 /// length. 539 virtual unsigned getInlineAsmLength(const char *Str, 540 const MCAsmInfo &MAI) const; 541}; 542 543/// TargetInstrInfoImpl - This is the default implementation of 544/// TargetInstrInfo, which just provides a couple of default implementations 545/// for various methods. This separated out because it is implemented in 546/// libcodegen, not in libtarget. 547class TargetInstrInfoImpl : public TargetInstrInfo { 548protected: 549 TargetInstrInfoImpl(const TargetInstrDesc *desc, unsigned NumOpcodes) 550 : TargetInstrInfo(desc, NumOpcodes) {} 551public: 552 virtual MachineInstr *commuteInstruction(MachineInstr *MI, 553 bool NewMI = false) const; 554 virtual bool findCommutedOpIndices(MachineInstr *MI, unsigned &SrcOpIdx1, 555 unsigned &SrcOpIdx2) const; 556 virtual bool PredicateInstruction(MachineInstr *MI, 557 const SmallVectorImpl<MachineOperand> &Pred) const; 558 virtual void reMaterialize(MachineBasicBlock &MBB, 559 MachineBasicBlock::iterator MI, 560 unsigned DestReg, unsigned SubReg, 561 const MachineInstr *Orig, 562 const TargetRegisterInfo *TRI) const; 563 virtual bool isIdentical(const MachineInstr *MI, 564 const MachineInstr *Other, 565 const MachineRegisterInfo *MRI) const; 566 567 virtual unsigned GetFunctionSizeInBytes(const MachineFunction &MF) const; 568}; 569 570} // End llvm namespace 571 572#endif 573