TargetInstrInfo.h revision 9a8e4121aa4121100fb562134c098aeb38f70b37
1//===-- llvm/Target/InstrInfo.h - Target Instruction Information --*-C++-*-==// 2// 3// This file describes the target machine instructions to the code generator. 4// 5//===---------------------------------------------------------------------===// 6 7#ifndef LLVM_TARGET_MACHINEINSTRINFO_H 8#define LLVM_TARGET_MACHINEINSTRINFO_H 9 10#include "Support/NonCopyable.h" 11#include "Support/DataTypes.h" 12#include "llvm/Constant.h" 13#include "llvm/DerivedTypes.h" 14 15class MachineInstrDescriptor; 16class MachineInstr; 17class TargetMachine; 18class Value; 19class Instruction; 20class Function; 21class MachineCodeForInstruction; 22 23//--------------------------------------------------------------------------- 24// Data types used to define information about a single machine instruction 25//--------------------------------------------------------------------------- 26 27typedef int MachineOpCode; 28typedef unsigned InstrSchedClass; 29 30const MachineOpCode INVALID_MACHINE_OPCODE = -1; 31 32 33// Global variable holding an array of descriptors for machine instructions. 34// The actual object needs to be created separately for each target machine. 35// This variable is initialized and reset by class MachineInstrInfo. 36// 37// FIXME: This should be a property of the target so that more than one target 38// at a time can be active... 39// 40extern const MachineInstrDescriptor *TargetInstrDescriptors; 41 42 43//--------------------------------------------------------------------------- 44// struct MachineInstrDescriptor: 45// Predefined information about each machine instruction. 46// Designed to initialized statically. 47// 48// class MachineInstructionInfo 49// Interface to description of machine instructions 50// 51//--------------------------------------------------------------------------- 52 53 54const unsigned M_NOP_FLAG = 1 << 0; 55const unsigned M_BRANCH_FLAG = 1 << 1; 56const unsigned M_CALL_FLAG = 1 << 2; 57const unsigned M_RET_FLAG = 1 << 3; 58const unsigned M_ARITH_FLAG = 1 << 4; 59const unsigned M_CC_FLAG = 1 << 6; 60const unsigned M_LOGICAL_FLAG = 1 << 6; 61const unsigned M_INT_FLAG = 1 << 7; 62const unsigned M_FLOAT_FLAG = 1 << 8; 63const unsigned M_CONDL_FLAG = 1 << 9; 64const unsigned M_LOAD_FLAG = 1 << 10; 65const unsigned M_PREFETCH_FLAG = 1 << 11; 66const unsigned M_STORE_FLAG = 1 << 12; 67const unsigned M_DUMMY_PHI_FLAG = 1 << 13; 68const unsigned M_PSEUDO_FLAG = 1 << 14; 69 70 71struct MachineInstrDescriptor { 72 const char * opCodeString; // Assembly language mnemonic for the opcode. 73 int numOperands; // Number of args; -1 if variable #args 74 int resultPos; // Position of the result; -1 if no result 75 unsigned maxImmedConst; // Largest +ve constant in IMMMED field or 0. 76 bool immedIsSignExtended; // Is IMMED field sign-extended? If so, 77 // smallest -ve value is -(maxImmedConst+1). 78 unsigned numDelaySlots; // Number of delay slots after instruction 79 unsigned latency; // Latency in machine cycles 80 InstrSchedClass schedClass; // enum identifying instr sched class 81 unsigned iclass; // flags identifying machine instr class 82}; 83 84 85class MachineInstrInfo : public NonCopyableV { 86public: 87 const TargetMachine& target; 88 89protected: 90 const MachineInstrDescriptor* desc; // raw array to allow static init'n 91 unsigned descSize; // number of entries in the desc array 92 unsigned numRealOpCodes; // number of non-dummy op codes 93 94public: 95 MachineInstrInfo(const TargetMachine& tgt, 96 const MachineInstrDescriptor *desc, unsigned descSize, 97 unsigned numRealOpCodes); 98 virtual ~MachineInstrInfo(); 99 100 unsigned getNumRealOpCodes() const { return numRealOpCodes; } 101 unsigned getNumTotalOpCodes() const { return descSize; } 102 103 const MachineInstrDescriptor& getDescriptor(MachineOpCode opCode) const { 104 assert(opCode >= 0 && opCode < (int)descSize); 105 return desc[opCode]; 106 } 107 108 int getNumOperands(MachineOpCode opCode) const { 109 return getDescriptor(opCode).numOperands; 110 } 111 112 int getResultPos(MachineOpCode opCode) const { 113 return getDescriptor(opCode).resultPos; 114 } 115 116 unsigned getNumDelaySlots(MachineOpCode opCode) const { 117 return getDescriptor(opCode).numDelaySlots; 118 } 119 120 InstrSchedClass getSchedClass(MachineOpCode opCode) const { 121 return getDescriptor(opCode).schedClass; 122 } 123 124 // 125 // Query instruction class flags according to the machine-independent 126 // flags listed above. 127 // 128 unsigned getIClass(MachineOpCode opCode) const { 129 return getDescriptor(opCode).iclass; 130 } 131 bool isNop(MachineOpCode opCode) const { 132 return getDescriptor(opCode).iclass & M_NOP_FLAG; 133 } 134 bool isBranch(MachineOpCode opCode) const { 135 return getDescriptor(opCode).iclass & M_BRANCH_FLAG; 136 } 137 bool isCall(MachineOpCode opCode) const { 138 return getDescriptor(opCode).iclass & M_CALL_FLAG; 139 } 140 bool isReturn(MachineOpCode opCode) const { 141 return getDescriptor(opCode).iclass & M_RET_FLAG; 142 } 143 bool isControlFlow(MachineOpCode opCode) const { 144 return getDescriptor(opCode).iclass & M_BRANCH_FLAG 145 || getDescriptor(opCode).iclass & M_CALL_FLAG 146 || getDescriptor(opCode).iclass & M_RET_FLAG; 147 } 148 bool isArith(MachineOpCode opCode) const { 149 return getDescriptor(opCode).iclass & M_ARITH_FLAG; 150 } 151 bool isCCInstr(MachineOpCode opCode) const { 152 return getDescriptor(opCode).iclass & M_CC_FLAG; 153 } 154 bool isLogical(MachineOpCode opCode) const { 155 return getDescriptor(opCode).iclass & M_LOGICAL_FLAG; 156 } 157 bool isIntInstr(MachineOpCode opCode) const { 158 return getDescriptor(opCode).iclass & M_INT_FLAG; 159 } 160 bool isFloatInstr(MachineOpCode opCode) const { 161 return getDescriptor(opCode).iclass & M_FLOAT_FLAG; 162 } 163 bool isConditional(MachineOpCode opCode) const { 164 return getDescriptor(opCode).iclass & M_CONDL_FLAG; 165 } 166 bool isLoad(MachineOpCode opCode) const { 167 return getDescriptor(opCode).iclass & M_LOAD_FLAG; 168 } 169 bool isPrefetch(MachineOpCode opCode) const { 170 return getDescriptor(opCode).iclass & M_PREFETCH_FLAG; 171 } 172 bool isLoadOrPrefetch(MachineOpCode opCode) const { 173 return getDescriptor(opCode).iclass & M_LOAD_FLAG 174 || getDescriptor(opCode).iclass & M_PREFETCH_FLAG; 175 } 176 bool isStore(MachineOpCode opCode) const { 177 return getDescriptor(opCode).iclass & M_STORE_FLAG; 178 } 179 bool isMemoryAccess(MachineOpCode opCode) const { 180 return getDescriptor(opCode).iclass & M_LOAD_FLAG 181 || getDescriptor(opCode).iclass & M_PREFETCH_FLAG 182 || getDescriptor(opCode).iclass & M_STORE_FLAG; 183 } 184 bool isDummyPhiInstr(const MachineOpCode opCode) const { 185 return getDescriptor(opCode).iclass & M_DUMMY_PHI_FLAG; 186 } 187 bool isPseudoInstr(const MachineOpCode opCode) const { 188 return getDescriptor(opCode).iclass & M_PSEUDO_FLAG; 189 } 190 191 // Check if an instruction can be issued before its operands are ready, 192 // or if a subsequent instruction that uses its result can be issued 193 // before the results are ready. 194 // Default to true since most instructions on many architectures allow this. 195 // 196 virtual bool hasOperandInterlock(MachineOpCode opCode) const { 197 return true; 198 } 199 200 virtual bool hasResultInterlock(MachineOpCode opCode) const { 201 return true; 202 } 203 204 // 205 // Latencies for individual instructions and instruction pairs 206 // 207 virtual int minLatency(MachineOpCode opCode) const { 208 return getDescriptor(opCode).latency; 209 } 210 211 virtual int maxLatency(MachineOpCode opCode) const { 212 return getDescriptor(opCode).latency; 213 } 214 215 // 216 // Which operand holds an immediate constant? Returns -1 if none 217 // 218 virtual int getImmedConstantPos(MachineOpCode opCode) const { 219 return -1; // immediate position is machine specific, so say -1 == "none" 220 } 221 222 // Check if the specified constant fits in the immediate field 223 // of this machine instruction 224 // 225 virtual bool constantFitsInImmedField(MachineOpCode opCode, 226 int64_t intValue) const; 227 228 // Return the largest +ve constant that can be held in the IMMMED field 229 // of this machine instruction. 230 // isSignExtended is set to true if the value is sign-extended before use 231 // (this is true for all immediate fields in SPARC instructions). 232 // Return 0 if the instruction has no IMMED field. 233 // 234 virtual uint64_t maxImmedConstant(MachineOpCode opCode, 235 bool &isSignExtended) const { 236 isSignExtended = getDescriptor(opCode).immedIsSignExtended; 237 return getDescriptor(opCode).maxImmedConst; 238 } 239 240 //------------------------------------------------------------------------- 241 // Queries about representation of LLVM quantities (e.g., constants) 242 //------------------------------------------------------------------------- 243 244 // Test if this type of constant must be loaded from memory into 245 // a register, i.e., cannot be set bitwise in register and cannot 246 // use immediate fields of instructions. Note that this only makes 247 // sense for primitive types. 248 virtual bool ConstantTypeMustBeLoaded(const Constant* CV) const { 249 assert(CV->getType()->isPrimitiveType() || isa<PointerType>(CV->getType())); 250 return !(CV->getType()->isIntegral() || isa<PointerType>(CV->getType())); 251 } 252 253 // Test if this constant may not fit in the immediate field of the 254 // machine instructions (probably) generated for this instruction. 255 // 256 virtual bool ConstantMayNotFitInImmedField(const Constant* CV, 257 const Instruction* I) const { 258 return true; // safe but very conservative 259 } 260 261 //------------------------------------------------------------------------- 262 // Code generation support for creating individual machine instructions 263 //------------------------------------------------------------------------- 264 265 // Get certain common op codes for the current target. this and all the 266 // Create* methods below should be moved to a machine code generation class 267 // 268 virtual MachineOpCode getNOPOpCode() const = 0; 269 270 // Create an instruction sequence to put the constant `val' into 271 // the virtual register `dest'. `val' may be a Constant or a 272 // GlobalValue, viz., the constant address of a global variable or function. 273 // The generated instructions are returned in `mvec'. 274 // Any temp. registers (TmpInstruction) created are recorded in mcfi. 275 // Symbolic constants or constants that must be accessed from memory 276 // are added to the constant pool via MachineFunction::get(F). 277 // 278 virtual void CreateCodeToLoadConst(const TargetMachine& target, 279 Function* F, 280 Value* val, 281 Instruction* dest, 282 std::vector<MachineInstr*>& mvec, 283 MachineCodeForInstruction& mcfi) const=0; 284 285 // Create an instruction sequence to copy an integer value `val' 286 // to a floating point value `dest' by copying to memory and back. 287 // val must be an integral type. dest must be a Float or Double. 288 // The generated instructions are returned in `mvec'. 289 // Any temp. registers (TmpInstruction) created are recorded in mcfi. 290 // Any stack space required is allocated via mcff. 291 // 292 virtual void CreateCodeToCopyIntToFloat(const TargetMachine& target, 293 Function* F, 294 Value* val, 295 Instruction* dest, 296 std::vector<MachineInstr*>& mvec, 297 MachineCodeForInstruction& mcfi)const=0; 298 299 // Similarly, create an instruction sequence to copy an FP value 300 // `val' to an integer value `dest' by copying to memory and back. 301 // The generated instructions are returned in `mvec'. 302 // Any temp. registers (TmpInstruction) created are recorded in mcfi. 303 // Any stack space required is allocated via mcff. 304 // 305 virtual void CreateCodeToCopyFloatToInt(const TargetMachine& target, 306 Function* F, 307 Value* val, 308 Instruction* dest, 309 std::vector<MachineInstr*>& mvec, 310 MachineCodeForInstruction& mcfi)const=0; 311 312 // Create instruction(s) to copy src to dest, for arbitrary types 313 // The generated instructions are returned in `mvec'. 314 // Any temp. registers (TmpInstruction) created are recorded in mcfi. 315 // Any stack space required is allocated via mcff. 316 // 317 virtual void CreateCopyInstructionsByType(const TargetMachine& target, 318 Function* F, 319 Value* src, 320 Instruction* dest, 321 std::vector<MachineInstr*>& mvec, 322 MachineCodeForInstruction& mcfi)const=0; 323 324 // Create instruction sequence to produce a sign-extended register value 325 // from an arbitrary sized value (sized in bits, not bytes). 326 // The generated instructions are appended to `mvec'. 327 // Any temp. registers (TmpInstruction) created are recorded in mcfi. 328 // Any stack space required is allocated via mcff. 329 // 330 virtual void CreateSignExtensionInstructions(const TargetMachine& target, 331 Function* F, 332 Value* srcVal, 333 Value* destVal, 334 unsigned numLowBits, 335 std::vector<MachineInstr*>& mvec, 336 MachineCodeForInstruction& mcfi) const=0; 337 338 // Create instruction sequence to produce a zero-extended register value 339 // from an arbitrary sized value (sized in bits, not bytes). 340 // The generated instructions are appended to `mvec'. 341 // Any temp. registers (TmpInstruction) created are recorded in mcfi. 342 // Any stack space required is allocated via mcff. 343 // 344 virtual void CreateZeroExtensionInstructions(const TargetMachine& target, 345 Function* F, 346 Value* srcVal, 347 Value* destVal, 348 unsigned srcSizeInBits, 349 std::vector<MachineInstr*>& mvec, 350 MachineCodeForInstruction& mcfi) const=0; 351}; 352 353#endif 354