TargetInstrInfo.h revision 9fe2009956fc40f3aea46fb3c38dcfb61c4aca46
1c66662664c44f34f891f39e4e416f766c7347f3cEnrico Granata//===-- llvm/Target/TargetInstrInfo.h - Instruction Info --------*- C++ -*-===// 2c66662664c44f34f891f39e4e416f766c7347f3cEnrico Granata// 3c66662664c44f34f891f39e4e416f766c7347f3cEnrico Granata// The LLVM Compiler Infrastructure 4c66662664c44f34f891f39e4e416f766c7347f3cEnrico Granata// 5c66662664c44f34f891f39e4e416f766c7347f3cEnrico Granata// This file is distributed under the University of Illinois Open Source 6c66662664c44f34f891f39e4e416f766c7347f3cEnrico Granata// License. See LICENSE.TXT for details. 7c66662664c44f34f891f39e4e416f766c7347f3cEnrico Granata// 8c66662664c44f34f891f39e4e416f766c7347f3cEnrico Granata//===----------------------------------------------------------------------===// 9c66662664c44f34f891f39e4e416f766c7347f3cEnrico Granata// 10c66662664c44f34f891f39e4e416f766c7347f3cEnrico Granata// This file describes the target machine instruction set to the code generator. 11c66662664c44f34f891f39e4e416f766c7347f3cEnrico Granata// 12c66662664c44f34f891f39e4e416f766c7347f3cEnrico Granata//===----------------------------------------------------------------------===// 13c66662664c44f34f891f39e4e416f766c7347f3cEnrico Granata 14c66662664c44f34f891f39e4e416f766c7347f3cEnrico Granata#ifndef LLVM_TARGET_TARGETINSTRINFO_H 15c66662664c44f34f891f39e4e416f766c7347f3cEnrico Granata#define LLVM_TARGET_TARGETINSTRINFO_H 16c66662664c44f34f891f39e4e416f766c7347f3cEnrico Granata 17c66662664c44f34f891f39e4e416f766c7347f3cEnrico Granata#include "llvm/Target/TargetInstrDesc.h" 18c66662664c44f34f891f39e4e416f766c7347f3cEnrico Granata#include "llvm/CodeGen/MachineFunction.h" 19c66662664c44f34f891f39e4e416f766c7347f3cEnrico Granata 20c66662664c44f34f891f39e4e416f766c7347f3cEnrico Granatanamespace llvm { 21c66662664c44f34f891f39e4e416f766c7347f3cEnrico Granata 22c66662664c44f34f891f39e4e416f766c7347f3cEnrico Granataclass InstrItineraryData; 23884288bcb6824452a3c64eb772c0976501acc47aMatt Kopecclass LiveVariables; 24884288bcb6824452a3c64eb772c0976501acc47aMatt Kopecclass MCAsmInfo; 25884288bcb6824452a3c64eb772c0976501acc47aMatt Kopecclass MachineMemOperand; 26e15e58facd4814a2be1cc1aa385e9f9125b92993Greg Claytonclass MachineRegisterInfo; 27e15e58facd4814a2be1cc1aa385e9f9125b92993Greg Claytonclass MDNode; 28b2e953d1d753bc725ea78f573c150493b99e2205Filipe Cabecinhasclass MCInst; 2952ebc0aab1fdecb634801deceeddd71a14c2148cGreg Claytonclass SDNode; 30c66662664c44f34f891f39e4e416f766c7347f3cEnrico Granataclass ScheduleHazardRecognizer; 31c66662664c44f34f891f39e4e416f766c7347f3cEnrico Granataclass SelectionDAG; 32c66662664c44f34f891f39e4e416f766c7347f3cEnrico Granataclass ScheduleDAG; 33c66662664c44f34f891f39e4e416f766c7347f3cEnrico Granataclass TargetRegisterClass; 3452ebc0aab1fdecb634801deceeddd71a14c2148cGreg Claytonclass TargetRegisterInfo; 3552ebc0aab1fdecb634801deceeddd71a14c2148cGreg Clayton 3652ebc0aab1fdecb634801deceeddd71a14c2148cGreg Claytontemplate<class T> class SmallVectorImpl; 3752ebc0aab1fdecb634801deceeddd71a14c2148cGreg Clayton 3852ebc0aab1fdecb634801deceeddd71a14c2148cGreg Clayton 39c66662664c44f34f891f39e4e416f766c7347f3cEnrico Granata//--------------------------------------------------------------------------- 4052ebc0aab1fdecb634801deceeddd71a14c2148cGreg Clayton/// 4152ebc0aab1fdecb634801deceeddd71a14c2148cGreg Clayton/// TargetInstrInfo - Interface to description of machine instruction set 42c66662664c44f34f891f39e4e416f766c7347f3cEnrico Granata/// 43c66662664c44f34f891f39e4e416f766c7347f3cEnrico Granataclass TargetInstrInfo { 44e15e58facd4814a2be1cc1aa385e9f9125b92993Greg Clayton const TargetInstrDesc *Descriptors; // Raw array to allow static init'n 45e15e58facd4814a2be1cc1aa385e9f9125b92993Greg Clayton unsigned NumOpcodes; // Number of entries in the desc array 46e15e58facd4814a2be1cc1aa385e9f9125b92993Greg Clayton 47e15e58facd4814a2be1cc1aa385e9f9125b92993Greg Clayton TargetInstrInfo(const TargetInstrInfo &); // DO NOT IMPLEMENT 48e15e58facd4814a2be1cc1aa385e9f9125b92993Greg Clayton void operator=(const TargetInstrInfo &); // DO NOT IMPLEMENT 499565e9dde3e33483f127815b10d6e9d5b8f46049Greg Claytonpublic: 50e15e58facd4814a2be1cc1aa385e9f9125b92993Greg Clayton TargetInstrInfo(const TargetInstrDesc *desc, unsigned NumOpcodes); 51e15e58facd4814a2be1cc1aa385e9f9125b92993Greg Clayton virtual ~TargetInstrInfo(); 529565e9dde3e33483f127815b10d6e9d5b8f46049Greg Clayton 53e15e58facd4814a2be1cc1aa385e9f9125b92993Greg Clayton unsigned getNumOpcodes() const { return NumOpcodes; } 54e15e58facd4814a2be1cc1aa385e9f9125b92993Greg Clayton 55e15e58facd4814a2be1cc1aa385e9f9125b92993Greg Clayton /// get - Return the machine instruction descriptor that corresponds to the 569565e9dde3e33483f127815b10d6e9d5b8f46049Greg Clayton /// specified instruction opcode. 57e15e58facd4814a2be1cc1aa385e9f9125b92993Greg Clayton /// 589565e9dde3e33483f127815b10d6e9d5b8f46049Greg Clayton const TargetInstrDesc &get(unsigned Opcode) const { 59e15e58facd4814a2be1cc1aa385e9f9125b92993Greg Clayton assert(Opcode < NumOpcodes && "Invalid opcode!"); 609565e9dde3e33483f127815b10d6e9d5b8f46049Greg Clayton return Descriptors[Opcode]; 61e15e58facd4814a2be1cc1aa385e9f9125b92993Greg Clayton } 629565e9dde3e33483f127815b10d6e9d5b8f46049Greg Clayton 63e15e58facd4814a2be1cc1aa385e9f9125b92993Greg Clayton /// isTriviallyReMaterializable - Return true if the instruction is trivially 64e15e58facd4814a2be1cc1aa385e9f9125b92993Greg Clayton /// rematerializable, meaning it has no side effects and requires no operands 65e15e58facd4814a2be1cc1aa385e9f9125b92993Greg Clayton /// that aren't always available. 66e15e58facd4814a2be1cc1aa385e9f9125b92993Greg Clayton bool isTriviallyReMaterializable(const MachineInstr *MI, 67e15e58facd4814a2be1cc1aa385e9f9125b92993Greg Clayton AliasAnalysis *AA = 0) const { 68e15e58facd4814a2be1cc1aa385e9f9125b92993Greg Clayton return MI->getOpcode() == TargetOpcode::IMPLICIT_DEF || 6995eeb63432ac232f81cf9ee3301abddd7ce2f817Enrico Granata (MI->getDesc().isRematerializable() && 7095eeb63432ac232f81cf9ee3301abddd7ce2f817Enrico Granata (isReallyTriviallyReMaterializable(MI, AA) || 7195eeb63432ac232f81cf9ee3301abddd7ce2f817Enrico Granata isReallyTriviallyReMaterializableGeneric(MI, AA))); 7295eeb63432ac232f81cf9ee3301abddd7ce2f817Enrico Granata } 7395eeb63432ac232f81cf9ee3301abddd7ce2f817Enrico Granata 7495eeb63432ac232f81cf9ee3301abddd7ce2f817Enrico Granataprotected: 7595eeb63432ac232f81cf9ee3301abddd7ce2f817Enrico Granata /// isReallyTriviallyReMaterializable - For instructions with opcodes for 7695eeb63432ac232f81cf9ee3301abddd7ce2f817Enrico Granata /// which the M_REMATERIALIZABLE flag is set, this hook lets the target 7795eeb63432ac232f81cf9ee3301abddd7ce2f817Enrico Granata /// specify whether the instruction is actually trivially rematerializable, 7895eeb63432ac232f81cf9ee3301abddd7ce2f817Enrico Granata /// taking into consideration its operands. This predicate must return false 7995eeb63432ac232f81cf9ee3301abddd7ce2f817Enrico Granata /// if the instruction has any side effects other than producing a value, or 8095eeb63432ac232f81cf9ee3301abddd7ce2f817Enrico Granata /// if it requres any address registers that are not always available. 8195eeb63432ac232f81cf9ee3301abddd7ce2f817Enrico Granata virtual bool isReallyTriviallyReMaterializable(const MachineInstr *MI, 8295eeb63432ac232f81cf9ee3301abddd7ce2f817Enrico Granata AliasAnalysis *AA) const { 8395eeb63432ac232f81cf9ee3301abddd7ce2f817Enrico Granata return false; 8495eeb63432ac232f81cf9ee3301abddd7ce2f817Enrico Granata } 8595eeb63432ac232f81cf9ee3301abddd7ce2f817Enrico Granata 8695eeb63432ac232f81cf9ee3301abddd7ce2f817Enrico Granataprivate: 8795eeb63432ac232f81cf9ee3301abddd7ce2f817Enrico Granata /// isReallyTriviallyReMaterializableGeneric - For instructions with opcodes 8895eeb63432ac232f81cf9ee3301abddd7ce2f817Enrico Granata /// for which the M_REMATERIALIZABLE flag is set and the target hook 8995eeb63432ac232f81cf9ee3301abddd7ce2f817Enrico Granata /// isReallyTriviallyReMaterializable returns false, this function does 9095eeb63432ac232f81cf9ee3301abddd7ce2f817Enrico Granata /// target-independent tests to determine if the instruction is really 9152ebc0aab1fdecb634801deceeddd71a14c2148cGreg Clayton /// trivially rematerializable. 9252ebc0aab1fdecb634801deceeddd71a14c2148cGreg Clayton bool isReallyTriviallyReMaterializableGeneric(const MachineInstr *MI, 9352ebc0aab1fdecb634801deceeddd71a14c2148cGreg Clayton AliasAnalysis *AA) const; 9452ebc0aab1fdecb634801deceeddd71a14c2148cGreg Clayton 9552ebc0aab1fdecb634801deceeddd71a14c2148cGreg Claytonpublic: 9652ebc0aab1fdecb634801deceeddd71a14c2148cGreg Clayton /// isCoalescableExtInstr - Return true if the instruction is a "coalescable" 9712477554ee676b775ec419575e1b091fa95bdc80Greg Clayton /// extension instruction. That is, it's like a copy where it's legal for the 9812477554ee676b775ec419575e1b091fa95bdc80Greg Clayton /// source to overlap the destination. e.g. X86::MOVSX64rr32. If this returns 9912477554ee676b775ec419575e1b091fa95bdc80Greg Clayton /// true, then it's expected the pre-extension value is available as a subreg 10052ebc0aab1fdecb634801deceeddd71a14c2148cGreg Clayton /// of the result register. This also returns the sub-register index in 10152ebc0aab1fdecb634801deceeddd71a14c2148cGreg Clayton /// SubIdx. 10212477554ee676b775ec419575e1b091fa95bdc80Greg Clayton virtual bool isCoalescableExtInstr(const MachineInstr &MI, 10312477554ee676b775ec419575e1b091fa95bdc80Greg Clayton unsigned &SrcReg, unsigned &DstReg, 10412477554ee676b775ec419575e1b091fa95bdc80Greg Clayton unsigned &SubIdx) const { 10552ebc0aab1fdecb634801deceeddd71a14c2148cGreg Clayton return false; 10652ebc0aab1fdecb634801deceeddd71a14c2148cGreg Clayton } 107c66662664c44f34f891f39e4e416f766c7347f3cEnrico Granata 108c66662664c44f34f891f39e4e416f766c7347f3cEnrico Granata /// isLoadFromStackSlot - If the specified machine instruction is a direct 10952ebc0aab1fdecb634801deceeddd71a14c2148cGreg Clayton /// load from a stack slot, return the virtual or physical register number of 11052ebc0aab1fdecb634801deceeddd71a14c2148cGreg Clayton /// the destination along with the FrameIndex of the loaded stack slot. If 11152ebc0aab1fdecb634801deceeddd71a14c2148cGreg Clayton /// not, return 0. This predicate must return 0 if the instruction has 11252ebc0aab1fdecb634801deceeddd71a14c2148cGreg Clayton /// any side effects other than loading from the stack slot. 11352ebc0aab1fdecb634801deceeddd71a14c2148cGreg Clayton virtual unsigned isLoadFromStackSlot(const MachineInstr *MI, 11452ebc0aab1fdecb634801deceeddd71a14c2148cGreg Clayton int &FrameIndex) const { 11552ebc0aab1fdecb634801deceeddd71a14c2148cGreg Clayton return 0; 11652ebc0aab1fdecb634801deceeddd71a14c2148cGreg Clayton } 117c66662664c44f34f891f39e4e416f766c7347f3cEnrico Granata 118c66662664c44f34f891f39e4e416f766c7347f3cEnrico Granata /// isLoadFromStackSlotPostFE - Check for post-frame ptr elimination 119c66662664c44f34f891f39e4e416f766c7347f3cEnrico Granata /// stack locations as well. This uses a heuristic so it isn't 12052ebc0aab1fdecb634801deceeddd71a14c2148cGreg Clayton /// reliable for correctness. 121c66662664c44f34f891f39e4e416f766c7347f3cEnrico Granata virtual unsigned isLoadFromStackSlotPostFE(const MachineInstr *MI, 122c66662664c44f34f891f39e4e416f766c7347f3cEnrico Granata int &FrameIndex) const { 123c66662664c44f34f891f39e4e416f766c7347f3cEnrico Granata return 0; 12452ebc0aab1fdecb634801deceeddd71a14c2148cGreg Clayton } 12552ebc0aab1fdecb634801deceeddd71a14c2148cGreg Clayton 126c66662664c44f34f891f39e4e416f766c7347f3cEnrico Granata /// hasLoadFromStackSlot - If the specified machine instruction has 12752ebc0aab1fdecb634801deceeddd71a14c2148cGreg Clayton /// a load from a stack slot, return true along with the FrameIndex 12852ebc0aab1fdecb634801deceeddd71a14c2148cGreg Clayton /// of the loaded stack slot and the machine mem operand containing 12952ebc0aab1fdecb634801deceeddd71a14c2148cGreg Clayton /// the reference. If not, return false. Unlike 13052ebc0aab1fdecb634801deceeddd71a14c2148cGreg Clayton /// isLoadFromStackSlot, this returns true for any instructions that 13152ebc0aab1fdecb634801deceeddd71a14c2148cGreg Clayton /// loads from the stack. This is just a hint, as some cases may be 13212477554ee676b775ec419575e1b091fa95bdc80Greg Clayton /// missed. 13312477554ee676b775ec419575e1b091fa95bdc80Greg Clayton virtual bool hasLoadFromStackSlot(const MachineInstr *MI, 13452ebc0aab1fdecb634801deceeddd71a14c2148cGreg Clayton const MachineMemOperand *&MMO, 13552ebc0aab1fdecb634801deceeddd71a14c2148cGreg Clayton int &FrameIndex) const { 13612477554ee676b775ec419575e1b091fa95bdc80Greg Clayton return 0; 13752ebc0aab1fdecb634801deceeddd71a14c2148cGreg Clayton } 13852ebc0aab1fdecb634801deceeddd71a14c2148cGreg Clayton 13952ebc0aab1fdecb634801deceeddd71a14c2148cGreg Clayton /// isStoreToStackSlot - If the specified machine instruction is a direct 140c66662664c44f34f891f39e4e416f766c7347f3cEnrico Granata /// store to a stack slot, return the virtual or physical register number of 141c66662664c44f34f891f39e4e416f766c7347f3cEnrico Granata /// the source reg along with the FrameIndex of the loaded stack slot. If 14252ebc0aab1fdecb634801deceeddd71a14c2148cGreg Clayton /// not, return 0. This predicate must return 0 if the instruction has 14352ebc0aab1fdecb634801deceeddd71a14c2148cGreg Clayton /// any side effects other than storing to the stack slot. 144c66662664c44f34f891f39e4e416f766c7347f3cEnrico Granata virtual unsigned isStoreToStackSlot(const MachineInstr *MI, 14552ebc0aab1fdecb634801deceeddd71a14c2148cGreg Clayton int &FrameIndex) const { 14652ebc0aab1fdecb634801deceeddd71a14c2148cGreg Clayton return 0; 14752ebc0aab1fdecb634801deceeddd71a14c2148cGreg Clayton } 148c66662664c44f34f891f39e4e416f766c7347f3cEnrico Granata 149c66662664c44f34f891f39e4e416f766c7347f3cEnrico Granata /// isStoreToStackSlotPostFE - Check for post-frame ptr elimination 15052ebc0aab1fdecb634801deceeddd71a14c2148cGreg Clayton /// stack locations as well. This uses a heuristic so it isn't 15152ebc0aab1fdecb634801deceeddd71a14c2148cGreg Clayton /// reliable for correctness. 152c66662664c44f34f891f39e4e416f766c7347f3cEnrico Granata virtual unsigned isStoreToStackSlotPostFE(const MachineInstr *MI, 15352ebc0aab1fdecb634801deceeddd71a14c2148cGreg Clayton int &FrameIndex) const { 154c66662664c44f34f891f39e4e416f766c7347f3cEnrico Granata return 0; 155c66662664c44f34f891f39e4e416f766c7347f3cEnrico Granata } 15652ebc0aab1fdecb634801deceeddd71a14c2148cGreg Clayton 15752ebc0aab1fdecb634801deceeddd71a14c2148cGreg Clayton /// hasStoreToStackSlot - If the specified machine instruction has a 15852ebc0aab1fdecb634801deceeddd71a14c2148cGreg Clayton /// store to a stack slot, return true along with the FrameIndex of 15912477554ee676b775ec419575e1b091fa95bdc80Greg Clayton /// the loaded stack slot and the machine mem operand containing the 16052ebc0aab1fdecb634801deceeddd71a14c2148cGreg Clayton /// reference. If not, return false. Unlike isStoreToStackSlot, 16152ebc0aab1fdecb634801deceeddd71a14c2148cGreg Clayton /// this returns true for any instructions that stores to the 162c66662664c44f34f891f39e4e416f766c7347f3cEnrico Granata /// stack. This is just a hint, as some cases may be missed. 163c66662664c44f34f891f39e4e416f766c7347f3cEnrico Granata virtual bool hasStoreToStackSlot(const MachineInstr *MI, 164c66662664c44f34f891f39e4e416f766c7347f3cEnrico Granata const MachineMemOperand *&MMO, 16552ebc0aab1fdecb634801deceeddd71a14c2148cGreg Clayton int &FrameIndex) const { 16652ebc0aab1fdecb634801deceeddd71a14c2148cGreg Clayton return 0; 167c66662664c44f34f891f39e4e416f766c7347f3cEnrico Granata } 168c66662664c44f34f891f39e4e416f766c7347f3cEnrico Granata 169c66662664c44f34f891f39e4e416f766c7347f3cEnrico Granata /// reMaterialize - Re-issue the specified 'original' instruction at the 17052ebc0aab1fdecb634801deceeddd71a14c2148cGreg Clayton /// specific location targeting a new destination register. 17152ebc0aab1fdecb634801deceeddd71a14c2148cGreg Clayton /// The register in Orig->getOperand(0).getReg() will be substituted by 172c66662664c44f34f891f39e4e416f766c7347f3cEnrico Granata /// DestReg:SubIdx. Any existing subreg index is preserved or composed with 173c66662664c44f34f891f39e4e416f766c7347f3cEnrico Granata /// SubIdx. 174c66662664c44f34f891f39e4e416f766c7347f3cEnrico Granata virtual void reMaterialize(MachineBasicBlock &MBB, 17552ebc0aab1fdecb634801deceeddd71a14c2148cGreg Clayton MachineBasicBlock::iterator MI, 17652ebc0aab1fdecb634801deceeddd71a14c2148cGreg Clayton unsigned DestReg, unsigned SubIdx, 17712477554ee676b775ec419575e1b091fa95bdc80Greg Clayton const MachineInstr *Orig, 17812477554ee676b775ec419575e1b091fa95bdc80Greg Clayton const TargetRegisterInfo &TRI) const = 0; 17912477554ee676b775ec419575e1b091fa95bdc80Greg Clayton 18052ebc0aab1fdecb634801deceeddd71a14c2148cGreg Clayton /// scheduleTwoAddrSource - Schedule the copy / re-mat of the source of the 18152ebc0aab1fdecb634801deceeddd71a14c2148cGreg Clayton /// two-addrss instruction inserted by two-address pass. 182c66662664c44f34f891f39e4e416f766c7347f3cEnrico Granata virtual void scheduleTwoAddrSource(MachineInstr *SrcMI, 18312477554ee676b775ec419575e1b091fa95bdc80Greg Clayton MachineInstr *UseMI, 184c66662664c44f34f891f39e4e416f766c7347f3cEnrico Granata const TargetRegisterInfo &TRI) const { 18552ebc0aab1fdecb634801deceeddd71a14c2148cGreg Clayton // Do nothing. 18652ebc0aab1fdecb634801deceeddd71a14c2148cGreg Clayton } 187c66662664c44f34f891f39e4e416f766c7347f3cEnrico Granata 18852ebc0aab1fdecb634801deceeddd71a14c2148cGreg Clayton /// duplicate - Create a duplicate of the Orig instruction in MF. This is like 18952ebc0aab1fdecb634801deceeddd71a14c2148cGreg Clayton /// MachineFunction::CloneMachineInstr(), but the target may update operands 19052ebc0aab1fdecb634801deceeddd71a14c2148cGreg Clayton /// that are required to be unique. 19152ebc0aab1fdecb634801deceeddd71a14c2148cGreg Clayton /// 19252ebc0aab1fdecb634801deceeddd71a14c2148cGreg Clayton /// The instruction must be duplicable as indicated by isNotDuplicable(). 193c66662664c44f34f891f39e4e416f766c7347f3cEnrico Granata virtual MachineInstr *duplicate(MachineInstr *Orig, 194c66662664c44f34f891f39e4e416f766c7347f3cEnrico Granata MachineFunction &MF) const = 0; 19552ebc0aab1fdecb634801deceeddd71a14c2148cGreg Clayton 19652ebc0aab1fdecb634801deceeddd71a14c2148cGreg Clayton /// convertToThreeAddress - This method must be implemented by targets that 197c66662664c44f34f891f39e4e416f766c7347f3cEnrico Granata /// set the M_CONVERTIBLE_TO_3_ADDR flag. When this flag is set, the target 19852ebc0aab1fdecb634801deceeddd71a14c2148cGreg Clayton /// may be able to convert a two-address instruction into one or more true 19952ebc0aab1fdecb634801deceeddd71a14c2148cGreg Clayton /// three-address instructions on demand. This allows the X86 target (for 20052ebc0aab1fdecb634801deceeddd71a14c2148cGreg Clayton /// example) to convert ADD and SHL instructions into LEA instructions if they 20152ebc0aab1fdecb634801deceeddd71a14c2148cGreg Clayton /// would require register copies due to two-addressness. 202c66662664c44f34f891f39e4e416f766c7347f3cEnrico Granata /// 203c66662664c44f34f891f39e4e416f766c7347f3cEnrico Granata /// This method returns a null pointer if the transformation cannot be 20452ebc0aab1fdecb634801deceeddd71a14c2148cGreg Clayton /// performed, otherwise it returns the last new instruction. 20552ebc0aab1fdecb634801deceeddd71a14c2148cGreg Clayton /// 206c66662664c44f34f891f39e4e416f766c7347f3cEnrico Granata virtual MachineInstr * 20752ebc0aab1fdecb634801deceeddd71a14c2148cGreg Clayton convertToThreeAddress(MachineFunction::iterator &MFI, 208c66662664c44f34f891f39e4e416f766c7347f3cEnrico Granata MachineBasicBlock::iterator &MBBI, LiveVariables *LV) const { 209c66662664c44f34f891f39e4e416f766c7347f3cEnrico Granata return 0; 21052ebc0aab1fdecb634801deceeddd71a14c2148cGreg Clayton } 21152ebc0aab1fdecb634801deceeddd71a14c2148cGreg Clayton 21252ebc0aab1fdecb634801deceeddd71a14c2148cGreg Clayton /// commuteInstruction - If a target has any instructions that are 21352ebc0aab1fdecb634801deceeddd71a14c2148cGreg Clayton /// commutable but require converting to different instructions or making 21452ebc0aab1fdecb634801deceeddd71a14c2148cGreg Clayton /// non-trivial changes to commute them, this method can overloaded to do 21552ebc0aab1fdecb634801deceeddd71a14c2148cGreg Clayton /// that. The default implementation simply swaps the commutable operands. 216b8f126a807c00e5c2d0e7faaf764c38072cd6764Greg Clayton /// If NewMI is false, MI is modified in place and returned; otherwise, a 217b8f126a807c00e5c2d0e7faaf764c38072cd6764Greg Clayton /// new machine instruction is created and returned. Do not call this 218b8f126a807c00e5c2d0e7faaf764c38072cd6764Greg Clayton /// method for a non-commutable instruction, but there may be some cases 21952ebc0aab1fdecb634801deceeddd71a14c2148cGreg Clayton /// where this method fails and returns null. 22052ebc0aab1fdecb634801deceeddd71a14c2148cGreg Clayton virtual MachineInstr *commuteInstruction(MachineInstr *MI, 221c66662664c44f34f891f39e4e416f766c7347f3cEnrico Granata bool NewMI = false) const = 0; 222c66662664c44f34f891f39e4e416f766c7347f3cEnrico Granata 223c66662664c44f34f891f39e4e416f766c7347f3cEnrico Granata /// findCommutedOpIndices - If specified MI is commutable, return the two 22452ebc0aab1fdecb634801deceeddd71a14c2148cGreg Clayton /// operand indices that would swap value. Return false if the instruction 22552ebc0aab1fdecb634801deceeddd71a14c2148cGreg Clayton /// is not in a form which this routine understands. 226c66662664c44f34f891f39e4e416f766c7347f3cEnrico Granata virtual bool findCommutedOpIndices(MachineInstr *MI, unsigned &SrcOpIdx1, 227c66662664c44f34f891f39e4e416f766c7347f3cEnrico Granata unsigned &SrcOpIdx2) const = 0; 228c66662664c44f34f891f39e4e416f766c7347f3cEnrico Granata 22952ebc0aab1fdecb634801deceeddd71a14c2148cGreg Clayton /// produceSameValue - Return true if two machine instructions would produce 23052ebc0aab1fdecb634801deceeddd71a14c2148cGreg Clayton /// identical values. By default, this is only true when the two instructions 23152ebc0aab1fdecb634801deceeddd71a14c2148cGreg Clayton /// are deemed identical except for defs. If this function is called when the 232c66662664c44f34f891f39e4e416f766c7347f3cEnrico Granata /// IR is still in SSA form, the caller can pass the MachineRegisterInfo for 23312477554ee676b775ec419575e1b091fa95bdc80Greg Clayton /// aggressive checks. 23412477554ee676b775ec419575e1b091fa95bdc80Greg Clayton virtual bool produceSameValue(const MachineInstr *MI0, 23552ebc0aab1fdecb634801deceeddd71a14c2148cGreg Clayton const MachineInstr *MI1, 23652ebc0aab1fdecb634801deceeddd71a14c2148cGreg Clayton const MachineRegisterInfo *MRI = 0) const = 0; 23712477554ee676b775ec419575e1b091fa95bdc80Greg Clayton 238c66662664c44f34f891f39e4e416f766c7347f3cEnrico Granata /// AnalyzeBranch - Analyze the branching code at the end of MBB, returning 239c66662664c44f34f891f39e4e416f766c7347f3cEnrico Granata /// true if it cannot be understood (e.g. it's a switch dispatch or isn't 24052ebc0aab1fdecb634801deceeddd71a14c2148cGreg Clayton /// implemented for a target). Upon success, this returns false and returns 241c66662664c44f34f891f39e4e416f766c7347f3cEnrico Granata /// with the following information in various cases: 242c66662664c44f34f891f39e4e416f766c7347f3cEnrico Granata /// 243c66662664c44f34f891f39e4e416f766c7347f3cEnrico Granata /// 1. If this block ends with no branches (it just falls through to its succ) 24452ebc0aab1fdecb634801deceeddd71a14c2148cGreg Clayton /// just return false, leaving TBB/FBB null. 24552ebc0aab1fdecb634801deceeddd71a14c2148cGreg Clayton /// 2. If this block ends with only an unconditional branch, it sets TBB to be 24652ebc0aab1fdecb634801deceeddd71a14c2148cGreg Clayton /// the destination block. 24752ebc0aab1fdecb634801deceeddd71a14c2148cGreg Clayton /// 3. If this block ends with a conditional branch and it falls through to a 24852ebc0aab1fdecb634801deceeddd71a14c2148cGreg Clayton /// successor block, it sets TBB to be the branch destination block and a 24952ebc0aab1fdecb634801deceeddd71a14c2148cGreg Clayton /// list of operands that evaluate the condition. These operands can be 25052ebc0aab1fdecb634801deceeddd71a14c2148cGreg Clayton /// passed to other TargetInstrInfo methods to create new branches. 25152ebc0aab1fdecb634801deceeddd71a14c2148cGreg Clayton /// 4. If this block ends with a conditional branch followed by an 25252ebc0aab1fdecb634801deceeddd71a14c2148cGreg Clayton /// unconditional branch, it returns the 'true' destination in TBB, the 25352ebc0aab1fdecb634801deceeddd71a14c2148cGreg Clayton /// 'false' destination in FBB, and a list of operands that evaluate the 254c66662664c44f34f891f39e4e416f766c7347f3cEnrico Granata /// condition. These operands can be passed to other TargetInstrInfo 25552ebc0aab1fdecb634801deceeddd71a14c2148cGreg Clayton /// methods to create new branches. 256c66662664c44f34f891f39e4e416f766c7347f3cEnrico Granata /// 25752ebc0aab1fdecb634801deceeddd71a14c2148cGreg Clayton /// Note that RemoveBranch and InsertBranch must be implemented to support 25852ebc0aab1fdecb634801deceeddd71a14c2148cGreg Clayton /// cases where this method returns success. 259c66662664c44f34f891f39e4e416f766c7347f3cEnrico Granata /// 260c66662664c44f34f891f39e4e416f766c7347f3cEnrico Granata /// If AllowModify is true, then this routine is allowed to modify the basic 261c66662664c44f34f891f39e4e416f766c7347f3cEnrico Granata /// block (e.g. delete instructions after the unconditional branch). 26252ebc0aab1fdecb634801deceeddd71a14c2148cGreg Clayton /// 26352ebc0aab1fdecb634801deceeddd71a14c2148cGreg Clayton virtual bool AnalyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB, 264c66662664c44f34f891f39e4e416f766c7347f3cEnrico Granata MachineBasicBlock *&FBB, 26552ebc0aab1fdecb634801deceeddd71a14c2148cGreg Clayton SmallVectorImpl<MachineOperand> &Cond, 26652ebc0aab1fdecb634801deceeddd71a14c2148cGreg Clayton bool AllowModify = false) const { 267c66662664c44f34f891f39e4e416f766c7347f3cEnrico Granata return true; 268c66662664c44f34f891f39e4e416f766c7347f3cEnrico Granata } 269c66662664c44f34f891f39e4e416f766c7347f3cEnrico Granata 270c66662664c44f34f891f39e4e416f766c7347f3cEnrico Granata /// RemoveBranch - Remove the branching code at the end of the specific MBB. 27152ebc0aab1fdecb634801deceeddd71a14c2148cGreg Clayton /// This is only invoked in cases where AnalyzeBranch returns success. It 272c66662664c44f34f891f39e4e416f766c7347f3cEnrico Granata /// returns the number of instructions that were removed. 27352ebc0aab1fdecb634801deceeddd71a14c2148cGreg Clayton virtual unsigned RemoveBranch(MachineBasicBlock &MBB) const { 27452ebc0aab1fdecb634801deceeddd71a14c2148cGreg Clayton assert(0 && "Target didn't implement TargetInstrInfo::RemoveBranch!"); 275c66662664c44f34f891f39e4e416f766c7347f3cEnrico Granata return 0; 276c66662664c44f34f891f39e4e416f766c7347f3cEnrico Granata } 277c66662664c44f34f891f39e4e416f766c7347f3cEnrico Granata 27852ebc0aab1fdecb634801deceeddd71a14c2148cGreg Clayton /// InsertBranch - Insert branch code into the end of the specified 27952ebc0aab1fdecb634801deceeddd71a14c2148cGreg Clayton /// MachineBasicBlock. The operands to this method are the same as those 28052ebc0aab1fdecb634801deceeddd71a14c2148cGreg Clayton /// returned by AnalyzeBranch. This is only invoked in cases where 28152ebc0aab1fdecb634801deceeddd71a14c2148cGreg Clayton /// AnalyzeBranch returns success. It returns the number of instructions 28252ebc0aab1fdecb634801deceeddd71a14c2148cGreg Clayton /// inserted. 28352ebc0aab1fdecb634801deceeddd71a14c2148cGreg Clayton /// 28452ebc0aab1fdecb634801deceeddd71a14c2148cGreg Clayton /// It is also invoked by tail merging to add unconditional branches in 28552ebc0aab1fdecb634801deceeddd71a14c2148cGreg Clayton /// cases where AnalyzeBranch doesn't apply because there was no original 28652ebc0aab1fdecb634801deceeddd71a14c2148cGreg Clayton /// branch to analyze. At least this much must be implemented, else tail 28752ebc0aab1fdecb634801deceeddd71a14c2148cGreg Clayton /// merging needs to be disabled. 28852ebc0aab1fdecb634801deceeddd71a14c2148cGreg Clayton virtual unsigned InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB, 28952ebc0aab1fdecb634801deceeddd71a14c2148cGreg Clayton MachineBasicBlock *FBB, 290c66662664c44f34f891f39e4e416f766c7347f3cEnrico Granata const SmallVectorImpl<MachineOperand> &Cond, 291c66662664c44f34f891f39e4e416f766c7347f3cEnrico Granata DebugLoc DL) const { 292c66662664c44f34f891f39e4e416f766c7347f3cEnrico Granata assert(0 && "Target didn't implement TargetInstrInfo::InsertBranch!"); 29352ebc0aab1fdecb634801deceeddd71a14c2148cGreg Clayton return 0; 29452ebc0aab1fdecb634801deceeddd71a14c2148cGreg Clayton } 295c66662664c44f34f891f39e4e416f766c7347f3cEnrico Granata 296c66662664c44f34f891f39e4e416f766c7347f3cEnrico Granata /// ReplaceTailWithBranchTo - Delete the instruction OldInst and everything 297c66662664c44f34f891f39e4e416f766c7347f3cEnrico Granata /// after it, replacing it with an unconditional branch to NewDest. This is 29852ebc0aab1fdecb634801deceeddd71a14c2148cGreg Clayton /// used by the tail merging pass. 29952ebc0aab1fdecb634801deceeddd71a14c2148cGreg Clayton virtual void ReplaceTailWithBranchTo(MachineBasicBlock::iterator Tail, 30052ebc0aab1fdecb634801deceeddd71a14c2148cGreg Clayton MachineBasicBlock *NewDest) const = 0; 301c66662664c44f34f891f39e4e416f766c7347f3cEnrico Granata 302c66662664c44f34f891f39e4e416f766c7347f3cEnrico Granata /// isLegalToSplitMBBAt - Return true if it's legal to split the given basic 303c66662664c44f34f891f39e4e416f766c7347f3cEnrico Granata /// block at the specified instruction (i.e. instruction would be the start 30452ebc0aab1fdecb634801deceeddd71a14c2148cGreg Clayton /// of a new basic block). 30552ebc0aab1fdecb634801deceeddd71a14c2148cGreg Clayton virtual bool isLegalToSplitMBBAt(MachineBasicBlock &MBB, 306c66662664c44f34f891f39e4e416f766c7347f3cEnrico Granata MachineBasicBlock::iterator MBBI) const { 307c66662664c44f34f891f39e4e416f766c7347f3cEnrico Granata return true; 308c66662664c44f34f891f39e4e416f766c7347f3cEnrico Granata } 30952ebc0aab1fdecb634801deceeddd71a14c2148cGreg Clayton 31052ebc0aab1fdecb634801deceeddd71a14c2148cGreg Clayton /// isProfitableToIfCvt - Return true if it's profitable to predicate 31152ebc0aab1fdecb634801deceeddd71a14c2148cGreg Clayton /// instructions with accumulated instruction latency of "NumCycles" 31252ebc0aab1fdecb634801deceeddd71a14c2148cGreg Clayton /// of the specified basic block, where the probability of the instructions 31352ebc0aab1fdecb634801deceeddd71a14c2148cGreg Clayton /// being executed is given by Probability, and Confidence is a measure 31452ebc0aab1fdecb634801deceeddd71a14c2148cGreg Clayton /// of our confidence that it will be properly predicted. 31552ebc0aab1fdecb634801deceeddd71a14c2148cGreg Clayton virtual 31652ebc0aab1fdecb634801deceeddd71a14c2148cGreg Clayton bool isProfitableToIfCvt(MachineBasicBlock &MBB, unsigned NumCyles, 31752ebc0aab1fdecb634801deceeddd71a14c2148cGreg Clayton unsigned ExtraPredCycles, 31852ebc0aab1fdecb634801deceeddd71a14c2148cGreg Clayton float Probability, float Confidence) const { 31952ebc0aab1fdecb634801deceeddd71a14c2148cGreg Clayton return false; 32052ebc0aab1fdecb634801deceeddd71a14c2148cGreg Clayton } 32152ebc0aab1fdecb634801deceeddd71a14c2148cGreg Clayton 32252ebc0aab1fdecb634801deceeddd71a14c2148cGreg Clayton /// isProfitableToIfCvt - Second variant of isProfitableToIfCvt, this one 323c66662664c44f34f891f39e4e416f766c7347f3cEnrico Granata /// checks for the case where two basic blocks from true and false path 32452ebc0aab1fdecb634801deceeddd71a14c2148cGreg Clayton /// of a if-then-else (diamond) are predicated on mutally exclusive 325c66662664c44f34f891f39e4e416f766c7347f3cEnrico Granata /// predicates, where the probability of the true path being taken is given 32652ebc0aab1fdecb634801deceeddd71a14c2148cGreg Clayton /// by Probability, and Confidence is a measure of our confidence that it 32752ebc0aab1fdecb634801deceeddd71a14c2148cGreg Clayton /// will be properly predicted. 328c66662664c44f34f891f39e4e416f766c7347f3cEnrico Granata virtual bool 329c66662664c44f34f891f39e4e416f766c7347f3cEnrico Granata isProfitableToIfCvt(MachineBasicBlock &TMBB, 330c66662664c44f34f891f39e4e416f766c7347f3cEnrico Granata unsigned NumTCycles, unsigned ExtraTCycles, 33152ebc0aab1fdecb634801deceeddd71a14c2148cGreg Clayton MachineBasicBlock &FMBB, 33252ebc0aab1fdecb634801deceeddd71a14c2148cGreg Clayton unsigned NumFCycles, unsigned ExtraFCycles, 333c66662664c44f34f891f39e4e416f766c7347f3cEnrico Granata float Probability, float Confidence) const { 33412477554ee676b775ec419575e1b091fa95bdc80Greg Clayton return false; 33512477554ee676b775ec419575e1b091fa95bdc80Greg Clayton } 33652ebc0aab1fdecb634801deceeddd71a14c2148cGreg Clayton 33712477554ee676b775ec419575e1b091fa95bdc80Greg Clayton /// isProfitableToDupForIfCvt - Return true if it's profitable for 33812477554ee676b775ec419575e1b091fa95bdc80Greg Clayton /// if-converter to duplicate instructions of specified accumulated 339c66662664c44f34f891f39e4e416f766c7347f3cEnrico Granata /// instruction latencies in the specified MBB to enable if-conversion. 340c66662664c44f34f891f39e4e416f766c7347f3cEnrico Granata /// The probability of the instructions being executed is given by 341c66662664c44f34f891f39e4e416f766c7347f3cEnrico Granata /// Probability, and Confidence is a measure of our confidence that it 34212477554ee676b775ec419575e1b091fa95bdc80Greg Clayton /// will be properly predicted. 34352ebc0aab1fdecb634801deceeddd71a14c2148cGreg Clayton virtual bool 34452ebc0aab1fdecb634801deceeddd71a14c2148cGreg Clayton isProfitableToDupForIfCvt(MachineBasicBlock &MBB, unsigned NumCyles, 34512477554ee676b775ec419575e1b091fa95bdc80Greg Clayton float Probability, float Confidence) const { 34652ebc0aab1fdecb634801deceeddd71a14c2148cGreg Clayton return false; 34752ebc0aab1fdecb634801deceeddd71a14c2148cGreg Clayton } 34852ebc0aab1fdecb634801deceeddd71a14c2148cGreg Clayton 34912477554ee676b775ec419575e1b091fa95bdc80Greg Clayton /// copyPhysReg - Emit instructions to copy a pair of physical registers. 35012477554ee676b775ec419575e1b091fa95bdc80Greg Clayton virtual void copyPhysReg(MachineBasicBlock &MBB, 35188b980bfd735c4691b7f0771a45a78cb75033564Greg Clayton MachineBasicBlock::iterator MI, DebugLoc DL, 35288b980bfd735c4691b7f0771a45a78cb75033564Greg Clayton unsigned DestReg, unsigned SrcReg, 35352ebc0aab1fdecb634801deceeddd71a14c2148cGreg Clayton bool KillSrc) const { 35488b980bfd735c4691b7f0771a45a78cb75033564Greg Clayton assert(0 && "Target didn't implement TargetInstrInfo::copyPhysReg!"); 35552ebc0aab1fdecb634801deceeddd71a14c2148cGreg Clayton } 35688b980bfd735c4691b7f0771a45a78cb75033564Greg Clayton 35752ebc0aab1fdecb634801deceeddd71a14c2148cGreg Clayton /// storeRegToStackSlot - Store the specified register of the given register 35852ebc0aab1fdecb634801deceeddd71a14c2148cGreg Clayton /// class to the specified stack frame index. The store instruction is to be 35952ebc0aab1fdecb634801deceeddd71a14c2148cGreg Clayton /// added to the given machine basic block before the specified machine 36088b980bfd735c4691b7f0771a45a78cb75033564Greg Clayton /// instruction. If isKill is true, the register operand is the last use and 36188b980bfd735c4691b7f0771a45a78cb75033564Greg Clayton /// must be marked kill. 36288b980bfd735c4691b7f0771a45a78cb75033564Greg Clayton virtual void storeRegToStackSlot(MachineBasicBlock &MBB, 36388b980bfd735c4691b7f0771a45a78cb75033564Greg Clayton MachineBasicBlock::iterator MI, 36488b980bfd735c4691b7f0771a45a78cb75033564Greg Clayton unsigned SrcReg, bool isKill, int FrameIndex, 36552ebc0aab1fdecb634801deceeddd71a14c2148cGreg Clayton const TargetRegisterClass *RC, 36688b980bfd735c4691b7f0771a45a78cb75033564Greg Clayton const TargetRegisterInfo *TRI) const { 36752ebc0aab1fdecb634801deceeddd71a14c2148cGreg Clayton assert(0 && "Target didn't implement TargetInstrInfo::storeRegToStackSlot!"); 36888b980bfd735c4691b7f0771a45a78cb75033564Greg Clayton } 36952ebc0aab1fdecb634801deceeddd71a14c2148cGreg Clayton 37036da2aa6dc5ad9994b638ed09eb81c44cc05540bGreg Clayton /// loadRegFromStackSlot - Load the specified register of the given register 37136da2aa6dc5ad9994b638ed09eb81c44cc05540bGreg Clayton /// class from the specified stack frame index. The load instruction is to be 37236da2aa6dc5ad9994b638ed09eb81c44cc05540bGreg Clayton /// added to the given machine basic block before the specified machine 37336da2aa6dc5ad9994b638ed09eb81c44cc05540bGreg Clayton /// instruction. 37436da2aa6dc5ad9994b638ed09eb81c44cc05540bGreg Clayton virtual void loadRegFromStackSlot(MachineBasicBlock &MBB, 37536da2aa6dc5ad9994b638ed09eb81c44cc05540bGreg Clayton MachineBasicBlock::iterator MI, 37636da2aa6dc5ad9994b638ed09eb81c44cc05540bGreg Clayton unsigned DestReg, int FrameIndex, 37736da2aa6dc5ad9994b638ed09eb81c44cc05540bGreg Clayton const TargetRegisterClass *RC, 37888b980bfd735c4691b7f0771a45a78cb75033564Greg Clayton const TargetRegisterInfo *TRI) const { 37988b980bfd735c4691b7f0771a45a78cb75033564Greg Clayton assert(0 && "Target didn't implement TargetInstrInfo::loadRegFromStackSlot!"); 38088b980bfd735c4691b7f0771a45a78cb75033564Greg Clayton } 38188b980bfd735c4691b7f0771a45a78cb75033564Greg Clayton 38252ebc0aab1fdecb634801deceeddd71a14c2148cGreg Clayton /// emitFrameIndexDebugValue - Emit a target-dependent form of 38352ebc0aab1fdecb634801deceeddd71a14c2148cGreg Clayton /// DBG_VALUE encoding the address of a frame index. Addresses would 384c66662664c44f34f891f39e4e416f766c7347f3cEnrico Granata /// normally be lowered the same way as other addresses on the target, 38552ebc0aab1fdecb634801deceeddd71a14c2148cGreg Clayton /// e.g. in load instructions. For targets that do not support this 38652ebc0aab1fdecb634801deceeddd71a14c2148cGreg Clayton /// the debug info is simply lost. 38752ebc0aab1fdecb634801deceeddd71a14c2148cGreg Clayton /// If you add this for a target you should handle this DBG_VALUE in the 388c66662664c44f34f891f39e4e416f766c7347f3cEnrico Granata /// target-specific AsmPrinter code as well; you will probably get invalid 389c66662664c44f34f891f39e4e416f766c7347f3cEnrico Granata /// assembly output if you don't. 39052ebc0aab1fdecb634801deceeddd71a14c2148cGreg Clayton virtual MachineInstr *emitFrameIndexDebugValue(MachineFunction &MF, 39152ebc0aab1fdecb634801deceeddd71a14c2148cGreg Clayton int FrameIx, 392c66662664c44f34f891f39e4e416f766c7347f3cEnrico Granata uint64_t Offset, 393c66662664c44f34f891f39e4e416f766c7347f3cEnrico Granata const MDNode *MDPtr, 394c66662664c44f34f891f39e4e416f766c7347f3cEnrico Granata DebugLoc dl) const { 395c66662664c44f34f891f39e4e416f766c7347f3cEnrico Granata return 0; 39652ebc0aab1fdecb634801deceeddd71a14c2148cGreg Clayton } 39712477554ee676b775ec419575e1b091fa95bdc80Greg Clayton 39852ebc0aab1fdecb634801deceeddd71a14c2148cGreg Clayton /// foldMemoryOperand - Attempt to fold a load or store of the specified stack 39912477554ee676b775ec419575e1b091fa95bdc80Greg Clayton /// slot into the specified machine instruction for the specified operand(s). 40012477554ee676b775ec419575e1b091fa95bdc80Greg Clayton /// If this is possible, a new instruction is returned with the specified 40152ebc0aab1fdecb634801deceeddd71a14c2148cGreg Clayton /// operand folded, otherwise NULL is returned. 40212477554ee676b775ec419575e1b091fa95bdc80Greg Clayton /// The new instruction is inserted before MI, and the client is responsible 403c66662664c44f34f891f39e4e416f766c7347f3cEnrico Granata /// for removing the old instruction. 40452ebc0aab1fdecb634801deceeddd71a14c2148cGreg Clayton MachineInstr* foldMemoryOperand(MachineBasicBlock::iterator MI, 405c66662664c44f34f891f39e4e416f766c7347f3cEnrico Granata const SmallVectorImpl<unsigned> &Ops, 406c66662664c44f34f891f39e4e416f766c7347f3cEnrico Granata int FrameIndex) const; 40752ebc0aab1fdecb634801deceeddd71a14c2148cGreg Clayton 40852ebc0aab1fdecb634801deceeddd71a14c2148cGreg Clayton /// foldMemoryOperand - Same as the previous version except it allows folding 409c66662664c44f34f891f39e4e416f766c7347f3cEnrico Granata /// of any load and store from / to any address, not just from a specific 410c66662664c44f34f891f39e4e416f766c7347f3cEnrico Granata /// stack slot. 411c66662664c44f34f891f39e4e416f766c7347f3cEnrico Granata MachineInstr* foldMemoryOperand(MachineBasicBlock::iterator MI, 412c66662664c44f34f891f39e4e416f766c7347f3cEnrico Granata const SmallVectorImpl<unsigned> &Ops, 41352ebc0aab1fdecb634801deceeddd71a14c2148cGreg Clayton MachineInstr* LoadMI) const; 414c66662664c44f34f891f39e4e416f766c7347f3cEnrico Granata 415c66662664c44f34f891f39e4e416f766c7347f3cEnrico Granataprotected: 41652ebc0aab1fdecb634801deceeddd71a14c2148cGreg Clayton /// foldMemoryOperandImpl - Target-dependent implementation for 417c66662664c44f34f891f39e4e416f766c7347f3cEnrico Granata /// foldMemoryOperand. Target-independent code in foldMemoryOperand will 41852ebc0aab1fdecb634801deceeddd71a14c2148cGreg Clayton /// take care of adding a MachineMemOperand to the newly created instruction. 419c66662664c44f34f891f39e4e416f766c7347f3cEnrico Granata virtual MachineInstr* foldMemoryOperandImpl(MachineFunction &MF, 42052ebc0aab1fdecb634801deceeddd71a14c2148cGreg Clayton MachineInstr* MI, 421c66662664c44f34f891f39e4e416f766c7347f3cEnrico Granata const SmallVectorImpl<unsigned> &Ops, 422c66662664c44f34f891f39e4e416f766c7347f3cEnrico Granata int FrameIndex) const { 423c66662664c44f34f891f39e4e416f766c7347f3cEnrico Granata return 0; 42452ebc0aab1fdecb634801deceeddd71a14c2148cGreg Clayton } 425c66662664c44f34f891f39e4e416f766c7347f3cEnrico Granata 42652ebc0aab1fdecb634801deceeddd71a14c2148cGreg Clayton /// foldMemoryOperandImpl - Target-dependent implementation for 42752ebc0aab1fdecb634801deceeddd71a14c2148cGreg Clayton /// foldMemoryOperand. Target-independent code in foldMemoryOperand will 428c66662664c44f34f891f39e4e416f766c7347f3cEnrico Granata /// take care of adding a MachineMemOperand to the newly created instruction. 429c66662664c44f34f891f39e4e416f766c7347f3cEnrico Granata virtual MachineInstr* foldMemoryOperandImpl(MachineFunction &MF, 430c66662664c44f34f891f39e4e416f766c7347f3cEnrico Granata MachineInstr* MI, 431 const SmallVectorImpl<unsigned> &Ops, 432 MachineInstr* LoadMI) const { 433 return 0; 434 } 435 436public: 437 /// canFoldMemoryOperand - Returns true for the specified load / store if 438 /// folding is possible. 439 virtual 440 bool canFoldMemoryOperand(const MachineInstr *MI, 441 const SmallVectorImpl<unsigned> &Ops) const =0; 442 443 /// unfoldMemoryOperand - Separate a single instruction which folded a load or 444 /// a store or a load and a store into two or more instruction. If this is 445 /// possible, returns true as well as the new instructions by reference. 446 virtual bool unfoldMemoryOperand(MachineFunction &MF, MachineInstr *MI, 447 unsigned Reg, bool UnfoldLoad, bool UnfoldStore, 448 SmallVectorImpl<MachineInstr*> &NewMIs) const{ 449 return false; 450 } 451 452 virtual bool unfoldMemoryOperand(SelectionDAG &DAG, SDNode *N, 453 SmallVectorImpl<SDNode*> &NewNodes) const { 454 return false; 455 } 456 457 /// getOpcodeAfterMemoryUnfold - Returns the opcode of the would be new 458 /// instruction after load / store are unfolded from an instruction of the 459 /// specified opcode. It returns zero if the specified unfolding is not 460 /// possible. If LoadRegIndex is non-null, it is filled in with the operand 461 /// index of the operand which will hold the register holding the loaded 462 /// value. 463 virtual unsigned getOpcodeAfterMemoryUnfold(unsigned Opc, 464 bool UnfoldLoad, bool UnfoldStore, 465 unsigned *LoadRegIndex = 0) const { 466 return 0; 467 } 468 469 /// areLoadsFromSameBasePtr - This is used by the pre-regalloc scheduler 470 /// to determine if two loads are loading from the same base address. It 471 /// should only return true if the base pointers are the same and the 472 /// only differences between the two addresses are the offset. It also returns 473 /// the offsets by reference. 474 virtual bool areLoadsFromSameBasePtr(SDNode *Load1, SDNode *Load2, 475 int64_t &Offset1, int64_t &Offset2) const { 476 return false; 477 } 478 479 /// shouldScheduleLoadsNear - This is a used by the pre-regalloc scheduler to 480 /// determine (in conjuction with areLoadsFromSameBasePtr) if two loads should 481 /// be scheduled togther. On some targets if two loads are loading from 482 /// addresses in the same cache line, it's better if they are scheduled 483 /// together. This function takes two integers that represent the load offsets 484 /// from the common base address. It returns true if it decides it's desirable 485 /// to schedule the two loads together. "NumLoads" is the number of loads that 486 /// have already been scheduled after Load1. 487 virtual bool shouldScheduleLoadsNear(SDNode *Load1, SDNode *Load2, 488 int64_t Offset1, int64_t Offset2, 489 unsigned NumLoads) const { 490 return false; 491 } 492 493 /// ReverseBranchCondition - Reverses the branch condition of the specified 494 /// condition list, returning false on success and true if it cannot be 495 /// reversed. 496 virtual 497 bool ReverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const { 498 return true; 499 } 500 501 /// insertNoop - Insert a noop into the instruction stream at the specified 502 /// point. 503 virtual void insertNoop(MachineBasicBlock &MBB, 504 MachineBasicBlock::iterator MI) const; 505 506 507 /// getNoopForMachoTarget - Return the noop instruction to use for a noop. 508 virtual void getNoopForMachoTarget(MCInst &NopInst) const { 509 // Default to just using 'nop' string. 510 } 511 512 513 /// isPredicated - Returns true if the instruction is already predicated. 514 /// 515 virtual bool isPredicated(const MachineInstr *MI) const { 516 return false; 517 } 518 519 /// isUnpredicatedTerminator - Returns true if the instruction is a 520 /// terminator instruction that has not been predicated. 521 virtual bool isUnpredicatedTerminator(const MachineInstr *MI) const; 522 523 /// PredicateInstruction - Convert the instruction into a predicated 524 /// instruction. It returns true if the operation was successful. 525 virtual 526 bool PredicateInstruction(MachineInstr *MI, 527 const SmallVectorImpl<MachineOperand> &Pred) const = 0; 528 529 /// SubsumesPredicate - Returns true if the first specified predicate 530 /// subsumes the second, e.g. GE subsumes GT. 531 virtual 532 bool SubsumesPredicate(const SmallVectorImpl<MachineOperand> &Pred1, 533 const SmallVectorImpl<MachineOperand> &Pred2) const { 534 return false; 535 } 536 537 /// DefinesPredicate - If the specified instruction defines any predicate 538 /// or condition code register(s) used for predication, returns true as well 539 /// as the definition predicate(s) by reference. 540 virtual bool DefinesPredicate(MachineInstr *MI, 541 std::vector<MachineOperand> &Pred) const { 542 return false; 543 } 544 545 /// isPredicable - Return true if the specified instruction can be predicated. 546 /// By default, this returns true for every instruction with a 547 /// PredicateOperand. 548 virtual bool isPredicable(MachineInstr *MI) const { 549 return MI->getDesc().isPredicable(); 550 } 551 552 /// isSafeToMoveRegClassDefs - Return true if it's safe to move a machine 553 /// instruction that defines the specified register class. 554 virtual bool isSafeToMoveRegClassDefs(const TargetRegisterClass *RC) const { 555 return true; 556 } 557 558 /// isSchedulingBoundary - Test if the given instruction should be 559 /// considered a scheduling boundary. This primarily includes labels and 560 /// terminators. 561 virtual bool isSchedulingBoundary(const MachineInstr *MI, 562 const MachineBasicBlock *MBB, 563 const MachineFunction &MF) const = 0; 564 565 /// Measure the specified inline asm to determine an approximation of its 566 /// length. 567 virtual unsigned getInlineAsmLength(const char *Str, 568 const MCAsmInfo &MAI) const; 569 570 /// CreateTargetPreRAHazardRecognizer - Allocate and return a hazard 571 /// recognizer to use for this target when scheduling the machine instructions 572 /// before register allocation. 573 virtual ScheduleHazardRecognizer* 574 CreateTargetHazardRecognizer(const TargetMachine *TM, 575 const ScheduleDAG *DAG) const = 0; 576 577 /// CreateTargetPostRAHazardRecognizer - Allocate and return a hazard 578 /// recognizer to use for this target when scheduling the machine instructions 579 /// after register allocation. 580 virtual ScheduleHazardRecognizer* 581 CreateTargetPostRAHazardRecognizer(const InstrItineraryData*, 582 const ScheduleDAG *DAG) const = 0; 583 584 /// AnalyzeCompare - For a comparison instruction, return the source register 585 /// in SrcReg and the value it compares against in CmpValue. Return true if 586 /// the comparison instruction can be analyzed. 587 virtual bool AnalyzeCompare(const MachineInstr *MI, 588 unsigned &SrcReg, int &Mask, int &Value) const { 589 return false; 590 } 591 592 /// OptimizeCompareInstr - See if the comparison instruction can be converted 593 /// into something more efficient. E.g., on ARM most instructions can set the 594 /// flags register, obviating the need for a separate CMP. 595 virtual bool OptimizeCompareInstr(MachineInstr *CmpInstr, 596 unsigned SrcReg, int Mask, int Value, 597 const MachineRegisterInfo *MRI) const { 598 return false; 599 } 600 601 /// FoldImmediate - 'Reg' is known to be defined by a move immediate 602 /// instruction, try to fold the immediate into the use instruction. 603 virtual bool FoldImmediate(MachineInstr *UseMI, MachineInstr *DefMI, 604 unsigned Reg, MachineRegisterInfo *MRI) const { 605 return false; 606 } 607 608 /// getNumMicroOps - Return the number of u-operations the given machine 609 /// instruction will be decoded to on the target cpu. 610 virtual unsigned getNumMicroOps(const InstrItineraryData *ItinData, 611 const MachineInstr *MI) const; 612 613 /// getOperandLatency - Compute and return the use operand latency of a given 614 /// pair of def and use. 615 /// In most cases, the static scheduling itinerary was enough to determine the 616 /// operand latency. But it may not be possible for instructions with variable 617 /// number of defs / uses. 618 virtual int getOperandLatency(const InstrItineraryData *ItinData, 619 const MachineInstr *DefMI, unsigned DefIdx, 620 const MachineInstr *UseMI, unsigned UseIdx) const; 621 622 virtual int getOperandLatency(const InstrItineraryData *ItinData, 623 SDNode *DefNode, unsigned DefIdx, 624 SDNode *UseNode, unsigned UseIdx) const; 625 626 /// getInstrLatency - Compute the instruction latency of a given instruction. 627 /// If the instruction has higher cost when predicated, it's returned via 628 /// PredCost. 629 virtual int getInstrLatency(const InstrItineraryData *ItinData, 630 const MachineInstr *MI, 631 unsigned *PredCost = 0) const; 632 633 virtual int getInstrLatency(const InstrItineraryData *ItinData, 634 SDNode *Node) const; 635 636 /// hasHighOperandLatency - Compute operand latency between a def of 'Reg' 637 /// and an use in the current loop, return true if the target considered 638 /// it 'high'. This is used by optimization passes such as machine LICM to 639 /// determine whether it makes sense to hoist an instruction out even in 640 /// high register pressure situation. 641 virtual 642 bool hasHighOperandLatency(const InstrItineraryData *ItinData, 643 const MachineRegisterInfo *MRI, 644 const MachineInstr *DefMI, unsigned DefIdx, 645 const MachineInstr *UseMI, unsigned UseIdx) const { 646 return false; 647 } 648 649 /// hasLowDefLatency - Compute operand latency of a def of 'Reg', return true 650 /// if the target considered it 'low'. 651 virtual 652 bool hasLowDefLatency(const InstrItineraryData *ItinData, 653 const MachineInstr *DefMI, unsigned DefIdx) const; 654}; 655 656/// TargetInstrInfoImpl - This is the default implementation of 657/// TargetInstrInfo, which just provides a couple of default implementations 658/// for various methods. This separated out because it is implemented in 659/// libcodegen, not in libtarget. 660class TargetInstrInfoImpl : public TargetInstrInfo { 661protected: 662 TargetInstrInfoImpl(const TargetInstrDesc *desc, unsigned NumOpcodes) 663 : TargetInstrInfo(desc, NumOpcodes) {} 664public: 665 virtual void ReplaceTailWithBranchTo(MachineBasicBlock::iterator OldInst, 666 MachineBasicBlock *NewDest) const; 667 virtual MachineInstr *commuteInstruction(MachineInstr *MI, 668 bool NewMI = false) const; 669 virtual bool findCommutedOpIndices(MachineInstr *MI, unsigned &SrcOpIdx1, 670 unsigned &SrcOpIdx2) const; 671 virtual bool canFoldMemoryOperand(const MachineInstr *MI, 672 const SmallVectorImpl<unsigned> &Ops) const; 673 virtual bool PredicateInstruction(MachineInstr *MI, 674 const SmallVectorImpl<MachineOperand> &Pred) const; 675 virtual void reMaterialize(MachineBasicBlock &MBB, 676 MachineBasicBlock::iterator MI, 677 unsigned DestReg, unsigned SubReg, 678 const MachineInstr *Orig, 679 const TargetRegisterInfo &TRI) const; 680 virtual MachineInstr *duplicate(MachineInstr *Orig, 681 MachineFunction &MF) const; 682 virtual bool produceSameValue(const MachineInstr *MI0, 683 const MachineInstr *MI1, 684 const MachineRegisterInfo *MRI) const; 685 virtual bool isSchedulingBoundary(const MachineInstr *MI, 686 const MachineBasicBlock *MBB, 687 const MachineFunction &MF) const; 688 689 virtual ScheduleHazardRecognizer * 690 CreateTargetHazardRecognizer(const TargetMachine*, const ScheduleDAG*) const; 691 692 virtual ScheduleHazardRecognizer * 693 CreateTargetPostRAHazardRecognizer(const InstrItineraryData*, 694 const ScheduleDAG*) const; 695}; 696 697} // End llvm namespace 698 699#endif 700