TargetInstrInfo.h revision a5a81d70720a4ce6ac7538927c2a874b0dfa8bd2
1//===-- llvm/Target/TargetInstrInfo.h - Instruction Info --------*- C++ -*-===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This file describes the target machine instruction set to the code generator. 11// 12//===----------------------------------------------------------------------===// 13 14#ifndef LLVM_TARGET_TARGETINSTRINFO_H 15#define LLVM_TARGET_TARGETINSTRINFO_H 16 17#include "llvm/Target/TargetInstrDesc.h" 18#include "llvm/CodeGen/MachineFunction.h" 19 20namespace llvm { 21 22class MCAsmInfo; 23class TargetRegisterClass; 24class TargetRegisterInfo; 25class LiveVariables; 26class CalleeSavedInfo; 27class SDNode; 28class SelectionDAG; 29class MachineMemOperand; 30 31template<class T> class SmallVectorImpl; 32 33 34//--------------------------------------------------------------------------- 35/// 36/// TargetInstrInfo - Interface to description of machine instruction set 37/// 38class TargetInstrInfo { 39 const TargetInstrDesc *Descriptors; // Raw array to allow static init'n 40 unsigned NumOpcodes; // Number of entries in the desc array 41 42 TargetInstrInfo(const TargetInstrInfo &); // DO NOT IMPLEMENT 43 void operator=(const TargetInstrInfo &); // DO NOT IMPLEMENT 44public: 45 TargetInstrInfo(const TargetInstrDesc *desc, unsigned NumOpcodes); 46 virtual ~TargetInstrInfo(); 47 48 // Invariant opcodes: All instruction sets have these as their low opcodes. 49 enum { 50 PHI = 0, 51 INLINEASM = 1, 52 DBG_LABEL = 2, 53 EH_LABEL = 3, 54 GC_LABEL = 4, 55 56 /// KILL - This instruction is a noop that is used only to adjust the liveness 57 /// of registers. This can be useful when dealing with sub-registers. 58 KILL = 5, 59 60 /// EXTRACT_SUBREG - This instruction takes two operands: a register 61 /// that has subregisters, and a subregister index. It returns the 62 /// extracted subregister value. This is commonly used to implement 63 /// truncation operations on target architectures which support it. 64 EXTRACT_SUBREG = 6, 65 66 /// INSERT_SUBREG - This instruction takes three operands: a register 67 /// that has subregisters, a register providing an insert value, and a 68 /// subregister index. It returns the value of the first register with 69 /// the value of the second register inserted. The first register is 70 /// often defined by an IMPLICIT_DEF, as is commonly used to implement 71 /// anyext operations on target architectures which support it. 72 INSERT_SUBREG = 7, 73 74 /// IMPLICIT_DEF - This is the MachineInstr-level equivalent of undef. 75 IMPLICIT_DEF = 8, 76 77 /// SUBREG_TO_REG - This instruction is similar to INSERT_SUBREG except 78 /// that the first operand is an immediate integer constant. This constant 79 /// is often zero, as is commonly used to implement zext operations on 80 /// target architectures which support it, such as with x86-64 (with 81 /// zext from i32 to i64 via implicit zero-extension). 82 SUBREG_TO_REG = 9, 83 84 /// COPY_TO_REGCLASS - This instruction is a placeholder for a plain 85 /// register-to-register copy into a specific register class. This is only 86 /// used between instruction selection and MachineInstr creation, before 87 /// virtual registers have been created for all the instructions, and it's 88 /// only needed in cases where the register classes implied by the 89 /// instructions are insufficient. The actual MachineInstrs to perform 90 /// the copy are emitted with the TargetInstrInfo::copyRegToReg hook. 91 COPY_TO_REGCLASS = 10, 92 93 // DEBUG_VALUE - a mapping of the llvm.dbg.value intrinsic 94 DEBUG_VALUE = 11, 95 96 // DEBUG_DECLARE - a mapping of the llvm.dbg.declare intrinsic 97 DEBUG_DECLARE = 12 98 }; 99 100 unsigned getNumOpcodes() const { return NumOpcodes; } 101 102 /// get - Return the machine instruction descriptor that corresponds to the 103 /// specified instruction opcode. 104 /// 105 const TargetInstrDesc &get(unsigned Opcode) const { 106 assert(Opcode < NumOpcodes && "Invalid opcode!"); 107 return Descriptors[Opcode]; 108 } 109 110 /// isTriviallyReMaterializable - Return true if the instruction is trivially 111 /// rematerializable, meaning it has no side effects and requires no operands 112 /// that aren't always available. 113 bool isTriviallyReMaterializable(const MachineInstr *MI, 114 AliasAnalysis *AA = 0) const { 115 return MI->getOpcode() == IMPLICIT_DEF || 116 (MI->getDesc().isRematerializable() && 117 (isReallyTriviallyReMaterializable(MI, AA) || 118 isReallyTriviallyReMaterializableGeneric(MI, AA))); 119 } 120 121protected: 122 /// isReallyTriviallyReMaterializable - For instructions with opcodes for 123 /// which the M_REMATERIALIZABLE flag is set, this hook lets the target 124 /// specify whether the instruction is actually trivially rematerializable, 125 /// taking into consideration its operands. This predicate must return false 126 /// if the instruction has any side effects other than producing a value, or 127 /// if it requres any address registers that are not always available. 128 virtual bool isReallyTriviallyReMaterializable(const MachineInstr *MI, 129 AliasAnalysis *AA) const { 130 return false; 131 } 132 133private: 134 /// isReallyTriviallyReMaterializableGeneric - For instructions with opcodes 135 /// for which the M_REMATERIALIZABLE flag is set and the target hook 136 /// isReallyTriviallyReMaterializable returns false, this function does 137 /// target-independent tests to determine if the instruction is really 138 /// trivially rematerializable. 139 bool isReallyTriviallyReMaterializableGeneric(const MachineInstr *MI, 140 AliasAnalysis *AA) const; 141 142public: 143 /// isMoveInstr - Return true if the instruction is a register to register 144 /// move and return the source and dest operands and their sub-register 145 /// indices by reference. 146 virtual bool isMoveInstr(const MachineInstr& MI, 147 unsigned& SrcReg, unsigned& DstReg, 148 unsigned& SrcSubIdx, unsigned& DstSubIdx) const { 149 return false; 150 } 151 152 /// isCoalescableInstr - Return true if the instruction is "coalescable". That 153 /// is, it's like a copy where it's legal for the source to overlap the 154 /// destination. e.g. X86::MOVSX64rr32. 155 virtual bool isCoalescableInstr(const MachineInstr &MI, bool &isCopy, 156 unsigned &SrcReg, unsigned &DstReg, 157 unsigned &SrcSubIdx, unsigned &DstSubIdx) const { 158 if (isMoveInstr(MI, SrcReg, DstReg, SrcSubIdx, DstSubIdx)) { 159 isCopy = true; 160 return true; 161 } 162 return false; 163 } 164 165 /// isIdentityCopy - Return true if the instruction is a copy (or 166 /// extract_subreg, insert_subreg, subreg_to_reg) where the source and 167 /// destination registers are the same. 168 bool isIdentityCopy(const MachineInstr &MI) const { 169 unsigned SrcReg, DstReg, SrcSubIdx, DstSubIdx; 170 if (isMoveInstr(MI, SrcReg, DstReg, SrcSubIdx, DstSubIdx) && 171 SrcReg == DstReg) 172 return true; 173 174 if (MI.getOpcode() == TargetInstrInfo::EXTRACT_SUBREG && 175 MI.getOperand(0).getReg() == MI.getOperand(1).getReg()) 176 return true; 177 178 if ((MI.getOpcode() == TargetInstrInfo::INSERT_SUBREG || 179 MI.getOpcode() == TargetInstrInfo::SUBREG_TO_REG) && 180 MI.getOperand(0).getReg() == MI.getOperand(2).getReg()) 181 return true; 182 return false; 183 } 184 185 /// isLoadFromStackSlot - If the specified machine instruction is a direct 186 /// load from a stack slot, return the virtual or physical register number of 187 /// the destination along with the FrameIndex of the loaded stack slot. If 188 /// not, return 0. This predicate must return 0 if the instruction has 189 /// any side effects other than loading from the stack slot. 190 virtual unsigned isLoadFromStackSlot(const MachineInstr *MI, 191 int &FrameIndex) const { 192 return 0; 193 } 194 195 /// isLoadFromStackSlotPostFE - Check for post-frame ptr elimination 196 /// stack locations as well. This uses a heuristic so it isn't 197 /// reliable for correctness. 198 virtual unsigned isLoadFromStackSlotPostFE(const MachineInstr *MI, 199 int &FrameIndex) const { 200 return 0; 201 } 202 203 /// hasLoadFromStackSlot - If the specified machine instruction has 204 /// a load from a stack slot, return true along with the FrameIndex 205 /// of the loaded stack slot and the machine mem operand containing 206 /// the reference. If not, return false. Unlike 207 /// isLoadFromStackSlot, this returns true for any instructions that 208 /// loads from the stack. This is just a hint, as some cases may be 209 /// missed. 210 virtual bool hasLoadFromStackSlot(const MachineInstr *MI, 211 const MachineMemOperand *&MMO, 212 int &FrameIndex) const { 213 return 0; 214 } 215 216 /// isStoreToStackSlot - If the specified machine instruction is a direct 217 /// store to a stack slot, return the virtual or physical register number of 218 /// the source reg along with the FrameIndex of the loaded stack slot. If 219 /// not, return 0. This predicate must return 0 if the instruction has 220 /// any side effects other than storing to the stack slot. 221 virtual unsigned isStoreToStackSlot(const MachineInstr *MI, 222 int &FrameIndex) const { 223 return 0; 224 } 225 226 /// isStoreToStackSlotPostFE - Check for post-frame ptr elimination 227 /// stack locations as well. This uses a heuristic so it isn't 228 /// reliable for correctness. 229 virtual unsigned isStoreToStackSlotPostFE(const MachineInstr *MI, 230 int &FrameIndex) const { 231 return 0; 232 } 233 234 /// hasStoreToStackSlot - If the specified machine instruction has a 235 /// store to a stack slot, return true along with the FrameIndex of 236 /// the loaded stack slot and the machine mem operand containing the 237 /// reference. If not, return false. Unlike isStoreToStackSlot, 238 /// this returns true for any instructions that loads from the 239 /// stack. This is just a hint, as some cases may be missed. 240 virtual bool hasStoreToStackSlot(const MachineInstr *MI, 241 const MachineMemOperand *&MMO, 242 int &FrameIndex) const { 243 return 0; 244 } 245 246 /// reMaterialize - Re-issue the specified 'original' instruction at the 247 /// specific location targeting a new destination register. 248 virtual void reMaterialize(MachineBasicBlock &MBB, 249 MachineBasicBlock::iterator MI, 250 unsigned DestReg, unsigned SubIdx, 251 const MachineInstr *Orig, 252 const TargetRegisterInfo *TRI) const = 0; 253 254 /// duplicate - Create a duplicate of the Orig instruction in MF. This is like 255 /// MachineFunction::CloneMachineInstr(), but the target may update operands 256 /// that are required to be unique. 257 /// 258 /// The instruction must be duplicable as indicated by isNotDuplicable(). 259 virtual MachineInstr *duplicate(MachineInstr *Orig, 260 MachineFunction &MF) const = 0; 261 262 /// convertToThreeAddress - This method must be implemented by targets that 263 /// set the M_CONVERTIBLE_TO_3_ADDR flag. When this flag is set, the target 264 /// may be able to convert a two-address instruction into one or more true 265 /// three-address instructions on demand. This allows the X86 target (for 266 /// example) to convert ADD and SHL instructions into LEA instructions if they 267 /// would require register copies due to two-addressness. 268 /// 269 /// This method returns a null pointer if the transformation cannot be 270 /// performed, otherwise it returns the last new instruction. 271 /// 272 virtual MachineInstr * 273 convertToThreeAddress(MachineFunction::iterator &MFI, 274 MachineBasicBlock::iterator &MBBI, LiveVariables *LV) const { 275 return 0; 276 } 277 278 /// commuteInstruction - If a target has any instructions that are commutable, 279 /// but require converting to a different instruction or making non-trivial 280 /// changes to commute them, this method can overloaded to do this. The 281 /// default implementation of this method simply swaps the first two operands 282 /// of MI and returns it. 283 /// 284 /// If a target wants to make more aggressive changes, they can construct and 285 /// return a new machine instruction. If an instruction cannot commute, it 286 /// can also return null. 287 /// 288 /// If NewMI is true, then a new machine instruction must be created. 289 /// 290 virtual MachineInstr *commuteInstruction(MachineInstr *MI, 291 bool NewMI = false) const = 0; 292 293 /// findCommutedOpIndices - If specified MI is commutable, return the two 294 /// operand indices that would swap value. Return true if the instruction 295 /// is not in a form which this routine understands. 296 virtual bool findCommutedOpIndices(MachineInstr *MI, unsigned &SrcOpIdx1, 297 unsigned &SrcOpIdx2) const = 0; 298 299 /// isIdentical - Return true if two instructions are identical. This differs 300 /// from MachineInstr::isIdenticalTo() in that it does not require the 301 /// virtual destination registers to be the same. This is used by MachineLICM 302 /// and other MI passes to perform CSE. 303 virtual bool isIdentical(const MachineInstr *MI, 304 const MachineInstr *Other, 305 const MachineRegisterInfo *MRI) const = 0; 306 307 /// AnalyzeBranch - Analyze the branching code at the end of MBB, returning 308 /// true if it cannot be understood (e.g. it's a switch dispatch or isn't 309 /// implemented for a target). Upon success, this returns false and returns 310 /// with the following information in various cases: 311 /// 312 /// 1. If this block ends with no branches (it just falls through to its succ) 313 /// just return false, leaving TBB/FBB null. 314 /// 2. If this block ends with only an unconditional branch, it sets TBB to be 315 /// the destination block. 316 /// 3. If this block ends with a conditional branch and it falls through to a 317 /// successor block, it sets TBB to be the branch destination block and a 318 /// list of operands that evaluate the condition. These operands can be 319 /// passed to other TargetInstrInfo methods to create new branches. 320 /// 4. If this block ends with a conditional branch followed by an 321 /// unconditional branch, it returns the 'true' destination in TBB, the 322 /// 'false' destination in FBB, and a list of operands that evaluate the 323 /// condition. These operands can be passed to other TargetInstrInfo 324 /// methods to create new branches. 325 /// 326 /// Note that RemoveBranch and InsertBranch must be implemented to support 327 /// cases where this method returns success. 328 /// 329 /// If AllowModify is true, then this routine is allowed to modify the basic 330 /// block (e.g. delete instructions after the unconditional branch). 331 /// 332 virtual bool AnalyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB, 333 MachineBasicBlock *&FBB, 334 SmallVectorImpl<MachineOperand> &Cond, 335 bool AllowModify = false) const { 336 return true; 337 } 338 339 /// RemoveBranch - Remove the branching code at the end of the specific MBB. 340 /// This is only invoked in cases where AnalyzeBranch returns success. It 341 /// returns the number of instructions that were removed. 342 virtual unsigned RemoveBranch(MachineBasicBlock &MBB) const { 343 assert(0 && "Target didn't implement TargetInstrInfo::RemoveBranch!"); 344 return 0; 345 } 346 347 /// InsertBranch - Insert branch code into the end of the specified 348 /// MachineBasicBlock. The operands to this method are the same as those 349 /// returned by AnalyzeBranch. This is only invoked in cases where 350 /// AnalyzeBranch returns success. It returns the number of instructions 351 /// inserted. 352 /// 353 /// It is also invoked by tail merging to add unconditional branches in 354 /// cases where AnalyzeBranch doesn't apply because there was no original 355 /// branch to analyze. At least this much must be implemented, else tail 356 /// merging needs to be disabled. 357 virtual unsigned InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB, 358 MachineBasicBlock *FBB, 359 const SmallVectorImpl<MachineOperand> &Cond) const { 360 assert(0 && "Target didn't implement TargetInstrInfo::InsertBranch!"); 361 return 0; 362 } 363 364 /// copyRegToReg - Emit instructions to copy between a pair of registers. It 365 /// returns false if the target does not how to copy between the specified 366 /// registers. 367 virtual bool copyRegToReg(MachineBasicBlock &MBB, 368 MachineBasicBlock::iterator MI, 369 unsigned DestReg, unsigned SrcReg, 370 const TargetRegisterClass *DestRC, 371 const TargetRegisterClass *SrcRC) const { 372 assert(0 && "Target didn't implement TargetInstrInfo::copyRegToReg!"); 373 return false; 374 } 375 376 /// storeRegToStackSlot - Store the specified register of the given register 377 /// class to the specified stack frame index. The store instruction is to be 378 /// added to the given machine basic block before the specified machine 379 /// instruction. If isKill is true, the register operand is the last use and 380 /// must be marked kill. 381 virtual void storeRegToStackSlot(MachineBasicBlock &MBB, 382 MachineBasicBlock::iterator MI, 383 unsigned SrcReg, bool isKill, int FrameIndex, 384 const TargetRegisterClass *RC) const { 385 assert(0 && "Target didn't implement TargetInstrInfo::storeRegToStackSlot!"); 386 } 387 388 /// loadRegFromStackSlot - Load the specified register of the given register 389 /// class from the specified stack frame index. The load instruction is to be 390 /// added to the given machine basic block before the specified machine 391 /// instruction. 392 virtual void loadRegFromStackSlot(MachineBasicBlock &MBB, 393 MachineBasicBlock::iterator MI, 394 unsigned DestReg, int FrameIndex, 395 const TargetRegisterClass *RC) const { 396 assert(0 && "Target didn't implement TargetInstrInfo::loadRegFromStackSlot!"); 397 } 398 399 /// spillCalleeSavedRegisters - Issues instruction(s) to spill all callee 400 /// saved registers and returns true if it isn't possible / profitable to do 401 /// so by issuing a series of store instructions via 402 /// storeRegToStackSlot(). Returns false otherwise. 403 virtual bool spillCalleeSavedRegisters(MachineBasicBlock &MBB, 404 MachineBasicBlock::iterator MI, 405 const std::vector<CalleeSavedInfo> &CSI) const { 406 return false; 407 } 408 409 /// restoreCalleeSavedRegisters - Issues instruction(s) to restore all callee 410 /// saved registers and returns true if it isn't possible / profitable to do 411 /// so by issuing a series of load instructions via loadRegToStackSlot(). 412 /// Returns false otherwise. 413 virtual bool restoreCalleeSavedRegisters(MachineBasicBlock &MBB, 414 MachineBasicBlock::iterator MI, 415 const std::vector<CalleeSavedInfo> &CSI) const { 416 return false; 417 } 418 419 /// foldMemoryOperand - Attempt to fold a load or store of the specified stack 420 /// slot into the specified machine instruction for the specified operand(s). 421 /// If this is possible, a new instruction is returned with the specified 422 /// operand folded, otherwise NULL is returned. The client is responsible for 423 /// removing the old instruction and adding the new one in the instruction 424 /// stream. 425 MachineInstr* foldMemoryOperand(MachineFunction &MF, 426 MachineInstr* MI, 427 const SmallVectorImpl<unsigned> &Ops, 428 int FrameIndex) const; 429 430 /// foldMemoryOperand - Same as the previous version except it allows folding 431 /// of any load and store from / to any address, not just from a specific 432 /// stack slot. 433 MachineInstr* foldMemoryOperand(MachineFunction &MF, 434 MachineInstr* MI, 435 const SmallVectorImpl<unsigned> &Ops, 436 MachineInstr* LoadMI) const; 437 438protected: 439 /// foldMemoryOperandImpl - Target-dependent implementation for 440 /// foldMemoryOperand. Target-independent code in foldMemoryOperand will 441 /// take care of adding a MachineMemOperand to the newly created instruction. 442 virtual MachineInstr* foldMemoryOperandImpl(MachineFunction &MF, 443 MachineInstr* MI, 444 const SmallVectorImpl<unsigned> &Ops, 445 int FrameIndex) const { 446 return 0; 447 } 448 449 /// foldMemoryOperandImpl - Target-dependent implementation for 450 /// foldMemoryOperand. Target-independent code in foldMemoryOperand will 451 /// take care of adding a MachineMemOperand to the newly created instruction. 452 virtual MachineInstr* foldMemoryOperandImpl(MachineFunction &MF, 453 MachineInstr* MI, 454 const SmallVectorImpl<unsigned> &Ops, 455 MachineInstr* LoadMI) const { 456 return 0; 457 } 458 459public: 460 /// canFoldMemoryOperand - Returns true for the specified load / store if 461 /// folding is possible. 462 virtual 463 bool canFoldMemoryOperand(const MachineInstr *MI, 464 const SmallVectorImpl<unsigned> &Ops) const { 465 return false; 466 } 467 468 /// unfoldMemoryOperand - Separate a single instruction which folded a load or 469 /// a store or a load and a store into two or more instruction. If this is 470 /// possible, returns true as well as the new instructions by reference. 471 virtual bool unfoldMemoryOperand(MachineFunction &MF, MachineInstr *MI, 472 unsigned Reg, bool UnfoldLoad, bool UnfoldStore, 473 SmallVectorImpl<MachineInstr*> &NewMIs) const{ 474 return false; 475 } 476 477 virtual bool unfoldMemoryOperand(SelectionDAG &DAG, SDNode *N, 478 SmallVectorImpl<SDNode*> &NewNodes) const { 479 return false; 480 } 481 482 /// getOpcodeAfterMemoryUnfold - Returns the opcode of the would be new 483 /// instruction after load / store are unfolded from an instruction of the 484 /// specified opcode. It returns zero if the specified unfolding is not 485 /// possible. If LoadRegIndex is non-null, it is filled in with the operand 486 /// index of the operand which will hold the register holding the loaded 487 /// value. 488 virtual unsigned getOpcodeAfterMemoryUnfold(unsigned Opc, 489 bool UnfoldLoad, bool UnfoldStore, 490 unsigned *LoadRegIndex = 0) const { 491 return 0; 492 } 493 494 /// ReverseBranchCondition - Reverses the branch condition of the specified 495 /// condition list, returning false on success and true if it cannot be 496 /// reversed. 497 virtual 498 bool ReverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const { 499 return true; 500 } 501 502 /// insertNoop - Insert a noop into the instruction stream at the specified 503 /// point. 504 virtual void insertNoop(MachineBasicBlock &MBB, 505 MachineBasicBlock::iterator MI) const; 506 507 /// isPredicated - Returns true if the instruction is already predicated. 508 /// 509 virtual bool isPredicated(const MachineInstr *MI) const { 510 return false; 511 } 512 513 /// isUnpredicatedTerminator - Returns true if the instruction is a 514 /// terminator instruction that has not been predicated. 515 virtual bool isUnpredicatedTerminator(const MachineInstr *MI) const; 516 517 /// PredicateInstruction - Convert the instruction into a predicated 518 /// instruction. It returns true if the operation was successful. 519 virtual 520 bool PredicateInstruction(MachineInstr *MI, 521 const SmallVectorImpl<MachineOperand> &Pred) const = 0; 522 523 /// SubsumesPredicate - Returns true if the first specified predicate 524 /// subsumes the second, e.g. GE subsumes GT. 525 virtual 526 bool SubsumesPredicate(const SmallVectorImpl<MachineOperand> &Pred1, 527 const SmallVectorImpl<MachineOperand> &Pred2) const { 528 return false; 529 } 530 531 /// DefinesPredicate - If the specified instruction defines any predicate 532 /// or condition code register(s) used for predication, returns true as well 533 /// as the definition predicate(s) by reference. 534 virtual bool DefinesPredicate(MachineInstr *MI, 535 std::vector<MachineOperand> &Pred) const { 536 return false; 537 } 538 539 /// isPredicable - Return true if the specified instruction can be predicated. 540 /// By default, this returns true for every instruction with a 541 /// PredicateOperand. 542 virtual bool isPredicable(MachineInstr *MI) const { 543 return MI->getDesc().isPredicable(); 544 } 545 546 /// isSafeToMoveRegClassDefs - Return true if it's safe to move a machine 547 /// instruction that defines the specified register class. 548 virtual bool isSafeToMoveRegClassDefs(const TargetRegisterClass *RC) const { 549 return true; 550 } 551 552 /// GetInstSize - Returns the size of the specified Instruction. 553 /// 554 virtual unsigned GetInstSizeInBytes(const MachineInstr *MI) const { 555 assert(0 && "Target didn't implement TargetInstrInfo::GetInstSize!"); 556 return 0; 557 } 558 559 /// GetFunctionSizeInBytes - Returns the size of the specified 560 /// MachineFunction. 561 /// 562 virtual unsigned GetFunctionSizeInBytes(const MachineFunction &MF) const = 0; 563 564 /// Measure the specified inline asm to determine an approximation of its 565 /// length. 566 virtual unsigned getInlineAsmLength(const char *Str, 567 const MCAsmInfo &MAI) const; 568}; 569 570/// TargetInstrInfoImpl - This is the default implementation of 571/// TargetInstrInfo, which just provides a couple of default implementations 572/// for various methods. This separated out because it is implemented in 573/// libcodegen, not in libtarget. 574class TargetInstrInfoImpl : public TargetInstrInfo { 575protected: 576 TargetInstrInfoImpl(const TargetInstrDesc *desc, unsigned NumOpcodes) 577 : TargetInstrInfo(desc, NumOpcodes) {} 578public: 579 virtual MachineInstr *commuteInstruction(MachineInstr *MI, 580 bool NewMI = false) const; 581 virtual bool findCommutedOpIndices(MachineInstr *MI, unsigned &SrcOpIdx1, 582 unsigned &SrcOpIdx2) const; 583 virtual bool PredicateInstruction(MachineInstr *MI, 584 const SmallVectorImpl<MachineOperand> &Pred) const; 585 virtual void reMaterialize(MachineBasicBlock &MBB, 586 MachineBasicBlock::iterator MI, 587 unsigned DestReg, unsigned SubReg, 588 const MachineInstr *Orig, 589 const TargetRegisterInfo *TRI) const; 590 virtual MachineInstr *duplicate(MachineInstr *Orig, 591 MachineFunction &MF) const; 592 virtual bool isIdentical(const MachineInstr *MI, 593 const MachineInstr *Other, 594 const MachineRegisterInfo *MRI) const; 595 596 virtual unsigned GetFunctionSizeInBytes(const MachineFunction &MF) const; 597}; 598 599} // End llvm namespace 600 601#endif 602