TargetInstrInfo.h revision af9fa2bd0c1ee25f3adda96b3e5d7129fbab393a
1//===-- llvm/Target/TargetInstrInfo.h - Instruction Info --------*- C++ -*-===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file was developed by the LLVM research group and is distributed under 6// the University of Illinois Open Source License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This file describes the target machine instructions to the code generator. 11// 12//===----------------------------------------------------------------------===// 13 14#ifndef LLVM_TARGET_TARGETINSTRINFO_H 15#define LLVM_TARGET_TARGETINSTRINFO_H 16 17#include "llvm/CodeGen/MachineBasicBlock.h" 18#include "llvm/Support/DataTypes.h" 19#include <vector> 20#include <cassert> 21 22namespace llvm { 23 24class MachineInstr; 25class TargetMachine; 26class Value; 27class Type; 28class Instruction; 29class Constant; 30class Function; 31class MachineCodeForInstruction; 32class TargetRegisterClass; 33 34//--------------------------------------------------------------------------- 35// Data types used to define information about a single machine instruction 36//--------------------------------------------------------------------------- 37 38typedef short MachineOpCode; 39typedef unsigned InstrSchedClass; 40 41//--------------------------------------------------------------------------- 42// struct TargetInstrDescriptor: 43// Predefined information about each machine instruction. 44// Designed to initialized statically. 45// 46 47const unsigned M_NOP_FLAG = 1 << 0; 48const unsigned M_BRANCH_FLAG = 1 << 1; 49const unsigned M_CALL_FLAG = 1 << 2; 50const unsigned M_RET_FLAG = 1 << 3; 51const unsigned M_BARRIER_FLAG = 1 << 4; 52const unsigned M_DELAY_SLOT_FLAG = 1 << 5; 53const unsigned M_CC_FLAG = 1 << 6; 54const unsigned M_LOAD_FLAG = 1 << 7; 55const unsigned M_STORE_FLAG = 1 << 8; 56 57// M_2_ADDR_FLAG - 3-addr instructions which really work like 2-addr ones. 58const unsigned M_2_ADDR_FLAG = 1 << 9; 59 60// M_CONVERTIBLE_TO_3_ADDR - This is a M_2_ADDR_FLAG instruction which can be 61// changed into a 3-address instruction if the first two operands cannot be 62// assigned to the same register. The target must implement the 63// TargetInstrInfo::convertToThreeAddress method for this instruction. 64const unsigned M_CONVERTIBLE_TO_3_ADDR = 1 << 10; 65 66// This M_COMMUTABLE - is a 2- or 3-address instruction (of the form X = op Y, 67// Z), which produces the same result if Y and Z are exchanged. 68const unsigned M_COMMUTABLE = 1 << 11; 69 70// M_TERMINATOR_FLAG - Is this instruction part of the terminator for a basic 71// block? Typically this is things like return and branch instructions. 72// Various passes use this to insert code into the bottom of a basic block, but 73// before control flow occurs. 74const unsigned M_TERMINATOR_FLAG = 1 << 12; 75 76// M_USES_CUSTOM_DAG_SCHED_INSERTION - Set if this instruction requires custom 77// insertion support when the DAG scheduler is inserting it into a machine basic 78// block. 79const unsigned M_USES_CUSTOM_DAG_SCHED_INSERTION = 1 << 13; 80 81/// TargetOperandInfo - This holds information about one operand of a machine 82/// instruction, indicating the register class for register operands, etc. 83/// 84class TargetOperandInfo { 85public: 86 /// RegClass - This specifies the register class of the operand if the 87 /// operand is a register. If not, this contains null. 88 const TargetRegisterClass *RegClass; 89 90 /// Currently no other information. 91}; 92 93 94class TargetInstrDescriptor { 95public: 96 const char * Name; // Assembly language mnemonic for the opcode. 97 int numOperands; // Number of args; -1 if variable #args 98 int resultPos; // Position of the result; -1 if no result 99 unsigned maxImmedConst; // Largest +ve constant in IMMED field or 0. 100 bool immedIsSignExtended; // Is IMMED field sign-extended? If so, 101 // smallest -ve value is -(maxImmedConst+1). 102 unsigned numDelaySlots; // Number of delay slots after instruction 103 unsigned latency; // Latency in machine cycles 104 InstrSchedClass schedClass; // enum identifying instr sched class 105 unsigned Flags; // flags identifying machine instr class 106 unsigned TSFlags; // Target Specific Flag values 107 const unsigned *ImplicitUses; // Registers implicitly read by this instr 108 const unsigned *ImplicitDefs; // Registers implicitly defined by this instr 109 const TargetOperandInfo *OpInfo; // 'numOperands' entries about operands. 110}; 111 112 113//--------------------------------------------------------------------------- 114/// 115/// TargetInstrInfo - Interface to description of machine instructions 116/// 117class TargetInstrInfo { 118 const TargetInstrDescriptor* desc; // raw array to allow static init'n 119 unsigned NumOpcodes; // number of entries in the desc array 120 unsigned numRealOpCodes; // number of non-dummy op codes 121 122 TargetInstrInfo(const TargetInstrInfo &); // DO NOT IMPLEMENT 123 void operator=(const TargetInstrInfo &); // DO NOT IMPLEMENT 124public: 125 TargetInstrInfo(const TargetInstrDescriptor *desc, unsigned NumOpcodes); 126 virtual ~TargetInstrInfo(); 127 128 // Invariant opcodes: All instruction sets have these as their low opcodes. 129 enum { 130 PHI = 0, 131 INLINEASM = 1 132 }; 133 134 unsigned getNumOpcodes() const { return NumOpcodes; } 135 136 /// get - Return the machine instruction descriptor that corresponds to the 137 /// specified instruction opcode. 138 /// 139 const TargetInstrDescriptor& get(MachineOpCode Opcode) const { 140 assert((unsigned)Opcode < NumOpcodes); 141 return desc[Opcode]; 142 } 143 144 const char *getName(MachineOpCode Opcode) const { 145 return get(Opcode).Name; 146 } 147 148 int getNumOperands(MachineOpCode Opcode) const { 149 return get(Opcode).numOperands; 150 } 151 152 InstrSchedClass getSchedClass(MachineOpCode Opcode) const { 153 return get(Opcode).schedClass; 154 } 155 156 const unsigned *getImplicitUses(MachineOpCode Opcode) const { 157 return get(Opcode).ImplicitUses; 158 } 159 160 const unsigned *getImplicitDefs(MachineOpCode Opcode) const { 161 return get(Opcode).ImplicitDefs; 162 } 163 164 165 // 166 // Query instruction class flags according to the machine-independent 167 // flags listed above. 168 // 169 bool isReturn(MachineOpCode Opcode) const { 170 return get(Opcode).Flags & M_RET_FLAG; 171 } 172 173 bool isTwoAddrInstr(MachineOpCode Opcode) const { 174 return get(Opcode).Flags & M_2_ADDR_FLAG; 175 } 176 bool isTerminatorInstr(unsigned Opcode) const { 177 return get(Opcode).Flags & M_TERMINATOR_FLAG; 178 } 179 180 bool isBranch(MachineOpCode Opcode) const { 181 return get(Opcode).Flags & M_BRANCH_FLAG; 182 } 183 184 /// isBarrier - Returns true if the specified instruction stops control flow 185 /// from executing the instruction immediately following it. Examples include 186 /// unconditional branches and return instructions. 187 bool isBarrier(MachineOpCode Opcode) const { 188 return get(Opcode).Flags & M_BARRIER_FLAG; 189 } 190 191 bool isCall(MachineOpCode Opcode) const { 192 return get(Opcode).Flags & M_CALL_FLAG; 193 } 194 bool isLoad(MachineOpCode Opcode) const { 195 return get(Opcode).Flags & M_LOAD_FLAG; 196 } 197 bool isStore(MachineOpCode Opcode) const { 198 return get(Opcode).Flags & M_STORE_FLAG; 199 } 200 201 /// usesCustomDAGSchedInsertionHook - Return true if this instruction requires 202 /// custom insertion support when the DAG scheduler is inserting it into a 203 /// machine basic block. 204 bool usesCustomDAGSchedInsertionHook(unsigned Opcode) const { 205 return get(Opcode).Flags & M_USES_CUSTOM_DAG_SCHED_INSERTION; 206 } 207 208 /// Return true if the instruction is a register to register move 209 /// and leave the source and dest operands in the passed parameters. 210 virtual bool isMoveInstr(const MachineInstr& MI, 211 unsigned& sourceReg, 212 unsigned& destReg) const { 213 return false; 214 } 215 216 /// isLoadFromStackSlot - If the specified machine instruction is a direct 217 /// load from a stack slot, return the virtual or physical register number of 218 /// the destination along with the FrameIndex of the loaded stack slot. If 219 /// not, return 0. This predicate must return 0 if the instruction has 220 /// any side effects other than loading from the stack slot. 221 virtual unsigned isLoadFromStackSlot(MachineInstr *MI, int &FrameIndex) const{ 222 return 0; 223 } 224 225 /// isStoreToStackSlot - If the specified machine instruction is a direct 226 /// store to a stack slot, return the virtual or physical register number of 227 /// the source reg along with the FrameIndex of the loaded stack slot. If 228 /// not, return 0. This predicate must return 0 if the instruction has 229 /// any side effects other than storing to the stack slot. 230 virtual unsigned isStoreToStackSlot(MachineInstr *MI, int &FrameIndex) const { 231 return 0; 232 } 233 234 /// convertToThreeAddress - This method must be implemented by targets that 235 /// set the M_CONVERTIBLE_TO_3_ADDR flag. When this flag is set, the target 236 /// may be able to convert a two-address instruction into a true 237 /// three-address instruction on demand. This allows the X86 target (for 238 /// example) to convert ADD and SHL instructions into LEA instructions if they 239 /// would require register copies due to two-addressness. 240 /// 241 /// This method returns a null pointer if the transformation cannot be 242 /// performed, otherwise it returns the new instruction. 243 /// 244 virtual MachineInstr *convertToThreeAddress(MachineInstr *TA) const { 245 return 0; 246 } 247 248 /// commuteInstruction - If a target has any instructions that are commutable, 249 /// but require converting to a different instruction or making non-trivial 250 /// changes to commute them, this method can overloaded to do this. The 251 /// default implementation of this method simply swaps the first two operands 252 /// of MI and returns it. 253 /// 254 /// If a target wants to make more aggressive changes, they can construct and 255 /// return a new machine instruction. If an instruction cannot commute, it 256 /// can also return null. 257 /// 258 virtual MachineInstr *commuteInstruction(MachineInstr *MI) const; 259 260 /// Insert a goto (unconditional branch) sequence to TMBB, at the 261 /// end of MBB 262 virtual void insertGoto(MachineBasicBlock& MBB, 263 MachineBasicBlock& TMBB) const { 264 assert(0 && "Target didn't implement insertGoto!"); 265 } 266 267 /// Reverses the branch condition of the MachineInstr pointed by 268 /// MI. The instruction is replaced and the new MI is returned. 269 virtual MachineBasicBlock::iterator 270 reverseBranchCondition(MachineBasicBlock::iterator MI) const { 271 assert(0 && "Target didn't implement reverseBranchCondition!"); 272 abort(); 273 return MI; 274 } 275 276 277 //------------------------------------------------------------------------- 278 // Code generation support for creating individual machine instructions 279 // 280 // WARNING: These methods are Sparc specific 281 // 282 // DO NOT USE ANY OF THESE METHODS THEY ARE DEPRECATED! 283 // 284 //------------------------------------------------------------------------- 285 286 unsigned getNumDelaySlots(MachineOpCode Opcode) const { 287 return get(Opcode).numDelaySlots; 288 } 289 bool isCCInstr(MachineOpCode Opcode) const { 290 return get(Opcode).Flags & M_CC_FLAG; 291 } 292 bool isNop(MachineOpCode Opcode) const { 293 return get(Opcode).Flags & M_NOP_FLAG; 294 } 295 296 /// hasDelaySlot - Returns true if the specified instruction has a delay slot 297 /// which must be filled by the code generator. 298 bool hasDelaySlot(unsigned Opcode) const { 299 return get(Opcode).Flags & M_DELAY_SLOT_FLAG; 300 } 301 302 virtual bool hasResultInterlock(MachineOpCode Opcode) const { 303 return true; 304 } 305 306 // 307 // Latencies for individual instructions and instruction pairs 308 // 309 virtual int minLatency(MachineOpCode Opcode) const { 310 return get(Opcode).latency; 311 } 312 313 virtual int maxLatency(MachineOpCode Opcode) const { 314 return get(Opcode).latency; 315 } 316 317 // 318 // Which operand holds an immediate constant? Returns -1 if none 319 // 320 virtual int getImmedConstantPos(MachineOpCode Opcode) const { 321 return -1; // immediate position is machine specific, so say -1 == "none" 322 } 323 324 // Check if the specified constant fits in the immediate field 325 // of this machine instruction 326 // 327 virtual bool constantFitsInImmedField(MachineOpCode Opcode, 328 int64_t intValue) const; 329 330 // Return the largest positive constant that can be held in the IMMED field 331 // of this machine instruction. 332 // isSignExtended is set to true if the value is sign-extended before use 333 // (this is true for all immediate fields in SPARC instructions). 334 // Return 0 if the instruction has no IMMED field. 335 // 336 virtual uint64_t maxImmedConstant(MachineOpCode Opcode, 337 bool &isSignExtended) const { 338 isSignExtended = get(Opcode).immedIsSignExtended; 339 return get(Opcode).maxImmedConst; 340 } 341}; 342 343} // End llvm namespace 344 345#endif 346