TargetInstrInfo.h revision b87bc95db075dae3033a3c541b55b4cb711c332c
1//===-- llvm/Target/TargetInstrInfo.h - Instruction Info --------*- C++ -*-===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This file describes the target machine instruction set to the code generator. 11// 12//===----------------------------------------------------------------------===// 13 14#ifndef LLVM_TARGET_TARGETINSTRINFO_H 15#define LLVM_TARGET_TARGETINSTRINFO_H 16 17#include "llvm/Target/TargetInstrDesc.h" 18#include "llvm/CodeGen/MachineFunction.h" 19 20namespace llvm { 21 22class MCAsmInfo; 23class TargetRegisterClass; 24class LiveVariables; 25class CalleeSavedInfo; 26class SDNode; 27class SelectionDAG; 28 29template<class T> class SmallVectorImpl; 30 31 32//--------------------------------------------------------------------------- 33/// 34/// TargetInstrInfo - Interface to description of machine instruction set 35/// 36class TargetInstrInfo { 37 const TargetInstrDesc *Descriptors; // Raw array to allow static init'n 38 unsigned NumOpcodes; // Number of entries in the desc array 39 40 TargetInstrInfo(const TargetInstrInfo &); // DO NOT IMPLEMENT 41 void operator=(const TargetInstrInfo &); // DO NOT IMPLEMENT 42public: 43 TargetInstrInfo(const TargetInstrDesc *desc, unsigned NumOpcodes); 44 virtual ~TargetInstrInfo(); 45 46 // Invariant opcodes: All instruction sets have these as their low opcodes. 47 enum { 48 PHI = 0, 49 INLINEASM = 1, 50 DBG_LABEL = 2, 51 EH_LABEL = 3, 52 GC_LABEL = 4, 53 54 /// KILL - This instruction is a noop that is used only to adjust the liveness 55 /// of registers. This can be useful when dealing with sub-registers. 56 KILL = 5, 57 58 /// EXTRACT_SUBREG - This instruction takes two operands: a register 59 /// that has subregisters, and a subregister index. It returns the 60 /// extracted subregister value. This is commonly used to implement 61 /// truncation operations on target architectures which support it. 62 EXTRACT_SUBREG = 6, 63 64 /// INSERT_SUBREG - This instruction takes three operands: a register 65 /// that has subregisters, a register providing an insert value, and a 66 /// subregister index. It returns the value of the first register with 67 /// the value of the second register inserted. The first register is 68 /// often defined by an IMPLICIT_DEF, as is commonly used to implement 69 /// anyext operations on target architectures which support it. 70 INSERT_SUBREG = 7, 71 72 /// IMPLICIT_DEF - This is the MachineInstr-level equivalent of undef. 73 IMPLICIT_DEF = 8, 74 75 /// SUBREG_TO_REG - This instruction is similar to INSERT_SUBREG except 76 /// that the first operand is an immediate integer constant. This constant 77 /// is often zero, as is commonly used to implement zext operations on 78 /// target architectures which support it, such as with x86-64 (with 79 /// zext from i32 to i64 via implicit zero-extension). 80 SUBREG_TO_REG = 9, 81 82 /// COPY_TO_REGCLASS - This instruction is a placeholder for a plain 83 /// register-to-register copy into a specific register class. This is only 84 /// used between instruction selection and MachineInstr creation, before 85 /// virtual registers have been created for all the instructions, and it's 86 /// only needed in cases where the register classes implied by the 87 /// instructions are insufficient. The actual MachineInstrs to perform 88 /// the copy are emitted with the TargetInstrInfo::copyRegToReg hook. 89 COPY_TO_REGCLASS = 10 90 }; 91 92 unsigned getNumOpcodes() const { return NumOpcodes; } 93 94 /// get - Return the machine instruction descriptor that corresponds to the 95 /// specified instruction opcode. 96 /// 97 const TargetInstrDesc &get(unsigned Opcode) const { 98 assert(Opcode < NumOpcodes && "Invalid opcode!"); 99 return Descriptors[Opcode]; 100 } 101 102 /// isTriviallyReMaterializable - Return true if the instruction is trivially 103 /// rematerializable, meaning it has no side effects and requires no operands 104 /// that aren't always available. 105 bool isTriviallyReMaterializable(const MachineInstr *MI, 106 AliasAnalysis *AA = 0) const { 107 return MI->getOpcode() == IMPLICIT_DEF || 108 (MI->getDesc().isRematerializable() && 109 (isReallyTriviallyReMaterializable(MI, AA) || 110 isReallyTriviallyReMaterializableGeneric(MI, AA))); 111 } 112 113protected: 114 /// isReallyTriviallyReMaterializable - For instructions with opcodes for 115 /// which the M_REMATERIALIZABLE flag is set, this hook lets the target 116 /// specify whether the instruction is actually trivially rematerializable, 117 /// taking into consideration its operands. This predicate must return false 118 /// if the instruction has any side effects other than producing a value, or 119 /// if it requres any address registers that are not always available. 120 virtual bool isReallyTriviallyReMaterializable(const MachineInstr *MI, 121 AliasAnalysis *AA) const { 122 return false; 123 } 124 125private: 126 /// isReallyTriviallyReMaterializableGeneric - For instructions with opcodes 127 /// for which the M_REMATERIALIZABLE flag is set and the target hook 128 /// isReallyTriviallyReMaterializable returns false, this function does 129 /// target-independent tests to determine if the instruction is really 130 /// trivially rematerializable. 131 bool isReallyTriviallyReMaterializableGeneric(const MachineInstr *MI, 132 AliasAnalysis *AA) const; 133 134public: 135 /// isMoveInstr - Return true if the instruction is a register to register 136 /// move and return the source and dest operands and their sub-register 137 /// indices by reference. 138 virtual bool isMoveInstr(const MachineInstr& MI, 139 unsigned& SrcReg, unsigned& DstReg, 140 unsigned& SrcSubIdx, unsigned& DstSubIdx) const { 141 return false; 142 } 143 144 /// isIdentityCopy - Return true if the instruction is a copy (or 145 /// extract_subreg, insert_subreg, subreg_to_reg) where the source and 146 /// destination registers are the same. 147 bool isIdentityCopy(const MachineInstr &MI) const { 148 unsigned SrcReg, DstReg, SrcSubIdx, DstSubIdx; 149 if (isMoveInstr(MI, SrcReg, DstReg, SrcSubIdx, DstSubIdx) && 150 SrcReg == DstReg) 151 return true; 152 153 if (MI.getOpcode() == TargetInstrInfo::EXTRACT_SUBREG && 154 MI.getOperand(0).getReg() == MI.getOperand(1).getReg()) 155 return true; 156 157 if ((MI.getOpcode() == TargetInstrInfo::INSERT_SUBREG || 158 MI.getOpcode() == TargetInstrInfo::SUBREG_TO_REG) && 159 MI.getOperand(0).getReg() == MI.getOperand(2).getReg()) 160 return true; 161 return false; 162 } 163 164 /// isLoadFromStackSlot - If the specified machine instruction is a direct 165 /// load from a stack slot, return the virtual or physical register number of 166 /// the destination along with the FrameIndex of the loaded stack slot. If 167 /// not, return 0. This predicate must return 0 if the instruction has 168 /// any side effects other than loading from the stack slot. 169 virtual unsigned isLoadFromStackSlot(const MachineInstr *MI, 170 int &FrameIndex) const { 171 return 0; 172 } 173 174 /// hasLoadFromStackSlot - If the specified machine instruction has 175 /// a load from a stack slot, return true along with the FrameIndex 176 /// of the loaded stack slot. If not, return false. Unlike 177 /// isLoadFromStackSlot, this returns true for any instructions that 178 /// loads from the stack. This is just a hint, as some cases may be 179 /// missed. 180 virtual bool hasLoadFromStackSlot(const MachineInstr *MI, 181 int &FrameIndex) const { 182 return 0; 183 } 184 185 /// isStoreToStackSlot - If the specified machine instruction is a direct 186 /// store to a stack slot, return the virtual or physical register number of 187 /// the source reg along with the FrameIndex of the loaded stack slot. If 188 /// not, return 0. This predicate must return 0 if the instruction has 189 /// any side effects other than storing to the stack slot. 190 virtual unsigned isStoreToStackSlot(const MachineInstr *MI, 191 int &FrameIndex) const { 192 return 0; 193 } 194 195 /// hasStoreToStackSlot - If the specified machine instruction has a 196 /// store to a stack slot, return true along with the FrameIndex of 197 /// the loaded stack slot. If not, return false. Unlike 198 /// isStoreToStackSlot, this returns true for any instructions that 199 /// loads from the stack. This is just a hint, as some cases may be 200 /// missed. 201 virtual bool hasStoreToStackSlot(const MachineInstr *MI, 202 int &FrameIndex) const { 203 return 0; 204 } 205 206 /// reMaterialize - Re-issue the specified 'original' instruction at the 207 /// specific location targeting a new destination register. 208 virtual void reMaterialize(MachineBasicBlock &MBB, 209 MachineBasicBlock::iterator MI, 210 unsigned DestReg, unsigned SubIdx, 211 const MachineInstr *Orig) const = 0; 212 213 /// convertToThreeAddress - This method must be implemented by targets that 214 /// set the M_CONVERTIBLE_TO_3_ADDR flag. When this flag is set, the target 215 /// may be able to convert a two-address instruction into one or more true 216 /// three-address instructions on demand. This allows the X86 target (for 217 /// example) to convert ADD and SHL instructions into LEA instructions if they 218 /// would require register copies due to two-addressness. 219 /// 220 /// This method returns a null pointer if the transformation cannot be 221 /// performed, otherwise it returns the last new instruction. 222 /// 223 virtual MachineInstr * 224 convertToThreeAddress(MachineFunction::iterator &MFI, 225 MachineBasicBlock::iterator &MBBI, LiveVariables *LV) const { 226 return 0; 227 } 228 229 /// commuteInstruction - If a target has any instructions that are commutable, 230 /// but require converting to a different instruction or making non-trivial 231 /// changes to commute them, this method can overloaded to do this. The 232 /// default implementation of this method simply swaps the first two operands 233 /// of MI and returns it. 234 /// 235 /// If a target wants to make more aggressive changes, they can construct and 236 /// return a new machine instruction. If an instruction cannot commute, it 237 /// can also return null. 238 /// 239 /// If NewMI is true, then a new machine instruction must be created. 240 /// 241 virtual MachineInstr *commuteInstruction(MachineInstr *MI, 242 bool NewMI = false) const = 0; 243 244 /// findCommutedOpIndices - If specified MI is commutable, return the two 245 /// operand indices that would swap value. Return true if the instruction 246 /// is not in a form which this routine understands. 247 virtual bool findCommutedOpIndices(MachineInstr *MI, unsigned &SrcOpIdx1, 248 unsigned &SrcOpIdx2) const = 0; 249 250 /// isIdentical - Return true if two instructions are identical. This differs 251 /// from MachineInstr::isIdenticalTo() in that it does not require the 252 /// virtual destination registers to be the same. This is used by MachineLICM 253 /// and other MI passes to perform CSE. 254 virtual bool isIdentical(const MachineInstr *MI, 255 const MachineInstr *Other, 256 const MachineRegisterInfo *MRI) const = 0; 257 258 /// AnalyzeBranch - Analyze the branching code at the end of MBB, returning 259 /// true if it cannot be understood (e.g. it's a switch dispatch or isn't 260 /// implemented for a target). Upon success, this returns false and returns 261 /// with the following information in various cases: 262 /// 263 /// 1. If this block ends with no branches (it just falls through to its succ) 264 /// just return false, leaving TBB/FBB null. 265 /// 2. If this block ends with only an unconditional branch, it sets TBB to be 266 /// the destination block. 267 /// 3. If this block ends with an conditional branch and it falls through to 268 /// a successor block, it sets TBB to be the branch destination block and 269 /// a list of operands that evaluate the condition. These 270 /// operands can be passed to other TargetInstrInfo methods to create new 271 /// branches. 272 /// 4. If this block ends with a conditional branch followed by an 273 /// unconditional branch, it returns the 'true' destination in TBB, the 274 /// 'false' destination in FBB, and a list of operands that evaluate the 275 /// condition. These operands can be passed to other TargetInstrInfo 276 /// methods to create new branches. 277 /// 278 /// Note that RemoveBranch and InsertBranch must be implemented to support 279 /// cases where this method returns success. 280 /// 281 /// If AllowModify is true, then this routine is allowed to modify the basic 282 /// block (e.g. delete instructions after the unconditional branch). 283 /// 284 virtual bool AnalyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB, 285 MachineBasicBlock *&FBB, 286 SmallVectorImpl<MachineOperand> &Cond, 287 bool AllowModify = false) const { 288 return true; 289 } 290 291 /// RemoveBranch - Remove the branching code at the end of the specific MBB. 292 /// This is only invoked in cases where AnalyzeBranch returns success. It 293 /// returns the number of instructions that were removed. 294 virtual unsigned RemoveBranch(MachineBasicBlock &MBB) const { 295 assert(0 && "Target didn't implement TargetInstrInfo::RemoveBranch!"); 296 return 0; 297 } 298 299 /// InsertBranch - Insert branch code into the end of the specified 300 /// MachineBasicBlock. The operands to this method are the same as those 301 /// returned by AnalyzeBranch. This is only invoked in cases where 302 /// AnalyzeBranch returns success. It returns the number of instructions 303 /// inserted. 304 /// 305 /// It is also invoked by tail merging to add unconditional branches in 306 /// cases where AnalyzeBranch doesn't apply because there was no original 307 /// branch to analyze. At least this much must be implemented, else tail 308 /// merging needs to be disabled. 309 virtual unsigned InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB, 310 MachineBasicBlock *FBB, 311 const SmallVectorImpl<MachineOperand> &Cond) const { 312 assert(0 && "Target didn't implement TargetInstrInfo::InsertBranch!"); 313 return 0; 314 } 315 316 /// copyRegToReg - Emit instructions to copy between a pair of registers. It 317 /// returns false if the target does not how to copy between the specified 318 /// registers. 319 virtual bool copyRegToReg(MachineBasicBlock &MBB, 320 MachineBasicBlock::iterator MI, 321 unsigned DestReg, unsigned SrcReg, 322 const TargetRegisterClass *DestRC, 323 const TargetRegisterClass *SrcRC) const { 324 assert(0 && "Target didn't implement TargetInstrInfo::copyRegToReg!"); 325 return false; 326 } 327 328 /// storeRegToStackSlot - Store the specified register of the given register 329 /// class to the specified stack frame index. The store instruction is to be 330 /// added to the given machine basic block before the specified machine 331 /// instruction. If isKill is true, the register operand is the last use and 332 /// must be marked kill. 333 virtual void storeRegToStackSlot(MachineBasicBlock &MBB, 334 MachineBasicBlock::iterator MI, 335 unsigned SrcReg, bool isKill, int FrameIndex, 336 const TargetRegisterClass *RC) const { 337 assert(0 && "Target didn't implement TargetInstrInfo::storeRegToStackSlot!"); 338 } 339 340 /// loadRegFromStackSlot - Load the specified register of the given register 341 /// class from the specified stack frame index. The load instruction is to be 342 /// added to the given machine basic block before the specified machine 343 /// instruction. 344 virtual void loadRegFromStackSlot(MachineBasicBlock &MBB, 345 MachineBasicBlock::iterator MI, 346 unsigned DestReg, int FrameIndex, 347 const TargetRegisterClass *RC) const { 348 assert(0 && "Target didn't implement TargetInstrInfo::loadRegFromStackSlot!"); 349 } 350 351 /// spillCalleeSavedRegisters - Issues instruction(s) to spill all callee 352 /// saved registers and returns true if it isn't possible / profitable to do 353 /// so by issuing a series of store instructions via 354 /// storeRegToStackSlot(). Returns false otherwise. 355 virtual bool spillCalleeSavedRegisters(MachineBasicBlock &MBB, 356 MachineBasicBlock::iterator MI, 357 const std::vector<CalleeSavedInfo> &CSI) const { 358 return false; 359 } 360 361 /// restoreCalleeSavedRegisters - Issues instruction(s) to restore all callee 362 /// saved registers and returns true if it isn't possible / profitable to do 363 /// so by issuing a series of load instructions via loadRegToStackSlot(). 364 /// Returns false otherwise. 365 virtual bool restoreCalleeSavedRegisters(MachineBasicBlock &MBB, 366 MachineBasicBlock::iterator MI, 367 const std::vector<CalleeSavedInfo> &CSI) const { 368 return false; 369 } 370 371 /// foldMemoryOperand - Attempt to fold a load or store of the specified stack 372 /// slot into the specified machine instruction for the specified operand(s). 373 /// If this is possible, a new instruction is returned with the specified 374 /// operand folded, otherwise NULL is returned. The client is responsible for 375 /// removing the old instruction and adding the new one in the instruction 376 /// stream. 377 MachineInstr* foldMemoryOperand(MachineFunction &MF, 378 MachineInstr* MI, 379 const SmallVectorImpl<unsigned> &Ops, 380 int FrameIndex) const; 381 382 /// foldMemoryOperand - Same as the previous version except it allows folding 383 /// of any load and store from / to any address, not just from a specific 384 /// stack slot. 385 MachineInstr* foldMemoryOperand(MachineFunction &MF, 386 MachineInstr* MI, 387 const SmallVectorImpl<unsigned> &Ops, 388 MachineInstr* LoadMI) const; 389 390protected: 391 /// foldMemoryOperandImpl - Target-dependent implementation for 392 /// foldMemoryOperand. Target-independent code in foldMemoryOperand will 393 /// take care of adding a MachineMemOperand to the newly created instruction. 394 virtual MachineInstr* foldMemoryOperandImpl(MachineFunction &MF, 395 MachineInstr* MI, 396 const SmallVectorImpl<unsigned> &Ops, 397 int FrameIndex) const { 398 return 0; 399 } 400 401 /// foldMemoryOperandImpl - Target-dependent implementation for 402 /// foldMemoryOperand. Target-independent code in foldMemoryOperand will 403 /// take care of adding a MachineMemOperand to the newly created instruction. 404 virtual MachineInstr* foldMemoryOperandImpl(MachineFunction &MF, 405 MachineInstr* MI, 406 const SmallVectorImpl<unsigned> &Ops, 407 MachineInstr* LoadMI) const { 408 return 0; 409 } 410 411public: 412 /// canFoldMemoryOperand - Returns true for the specified load / store if 413 /// folding is possible. 414 virtual 415 bool canFoldMemoryOperand(const MachineInstr *MI, 416 const SmallVectorImpl<unsigned> &Ops) const { 417 return false; 418 } 419 420 /// unfoldMemoryOperand - Separate a single instruction which folded a load or 421 /// a store or a load and a store into two or more instruction. If this is 422 /// possible, returns true as well as the new instructions by reference. 423 virtual bool unfoldMemoryOperand(MachineFunction &MF, MachineInstr *MI, 424 unsigned Reg, bool UnfoldLoad, bool UnfoldStore, 425 SmallVectorImpl<MachineInstr*> &NewMIs) const{ 426 return false; 427 } 428 429 virtual bool unfoldMemoryOperand(SelectionDAG &DAG, SDNode *N, 430 SmallVectorImpl<SDNode*> &NewNodes) const { 431 return false; 432 } 433 434 /// getOpcodeAfterMemoryUnfold - Returns the opcode of the would be new 435 /// instruction after load / store are unfolded from an instruction of the 436 /// specified opcode. It returns zero if the specified unfolding is not 437 /// possible. If LoadRegIndex is non-null, it is filled in with the operand 438 /// index of the operand which will hold the register holding the loaded 439 /// value. 440 virtual unsigned getOpcodeAfterMemoryUnfold(unsigned Opc, 441 bool UnfoldLoad, bool UnfoldStore, 442 unsigned *LoadRegIndex = 0) const { 443 return 0; 444 } 445 446 /// BlockHasNoFallThrough - Return true if the specified block does not 447 /// fall-through into its successor block. This is primarily used when a 448 /// branch is unanalyzable. It is useful for things like unconditional 449 /// indirect branches (jump tables). 450 virtual bool BlockHasNoFallThrough(const MachineBasicBlock &MBB) const { 451 return false; 452 } 453 454 /// ReverseBranchCondition - Reverses the branch condition of the specified 455 /// condition list, returning false on success and true if it cannot be 456 /// reversed. 457 virtual 458 bool ReverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const { 459 return true; 460 } 461 462 /// insertNoop - Insert a noop into the instruction stream at the specified 463 /// point. 464 virtual void insertNoop(MachineBasicBlock &MBB, 465 MachineBasicBlock::iterator MI) const; 466 467 /// isPredicated - Returns true if the instruction is already predicated. 468 /// 469 virtual bool isPredicated(const MachineInstr *MI) const { 470 return false; 471 } 472 473 /// isUnpredicatedTerminator - Returns true if the instruction is a 474 /// terminator instruction that has not been predicated. 475 virtual bool isUnpredicatedTerminator(const MachineInstr *MI) const; 476 477 /// PredicateInstruction - Convert the instruction into a predicated 478 /// instruction. It returns true if the operation was successful. 479 virtual 480 bool PredicateInstruction(MachineInstr *MI, 481 const SmallVectorImpl<MachineOperand> &Pred) const = 0; 482 483 /// SubsumesPredicate - Returns true if the first specified predicate 484 /// subsumes the second, e.g. GE subsumes GT. 485 virtual 486 bool SubsumesPredicate(const SmallVectorImpl<MachineOperand> &Pred1, 487 const SmallVectorImpl<MachineOperand> &Pred2) const { 488 return false; 489 } 490 491 /// DefinesPredicate - If the specified instruction defines any predicate 492 /// or condition code register(s) used for predication, returns true as well 493 /// as the definition predicate(s) by reference. 494 virtual bool DefinesPredicate(MachineInstr *MI, 495 std::vector<MachineOperand> &Pred) const { 496 return false; 497 } 498 499 /// isSafeToMoveRegClassDefs - Return true if it's safe to move a machine 500 /// instruction that defines the specified register class. 501 virtual bool isSafeToMoveRegClassDefs(const TargetRegisterClass *RC) const { 502 return true; 503 } 504 505 /// GetInstSize - Returns the size of the specified Instruction. 506 /// 507 virtual unsigned GetInstSizeInBytes(const MachineInstr *MI) const { 508 assert(0 && "Target didn't implement TargetInstrInfo::GetInstSize!"); 509 return 0; 510 } 511 512 /// GetFunctionSizeInBytes - Returns the size of the specified 513 /// MachineFunction. 514 /// 515 virtual unsigned GetFunctionSizeInBytes(const MachineFunction &MF) const = 0; 516 517 /// Measure the specified inline asm to determine an approximation of its 518 /// length. 519 virtual unsigned getInlineAsmLength(const char *Str, 520 const MCAsmInfo &MAI) const; 521}; 522 523/// TargetInstrInfoImpl - This is the default implementation of 524/// TargetInstrInfo, which just provides a couple of default implementations 525/// for various methods. This separated out because it is implemented in 526/// libcodegen, not in libtarget. 527class TargetInstrInfoImpl : public TargetInstrInfo { 528protected: 529 TargetInstrInfoImpl(const TargetInstrDesc *desc, unsigned NumOpcodes) 530 : TargetInstrInfo(desc, NumOpcodes) {} 531public: 532 virtual MachineInstr *commuteInstruction(MachineInstr *MI, 533 bool NewMI = false) const; 534 virtual bool findCommutedOpIndices(MachineInstr *MI, unsigned &SrcOpIdx1, 535 unsigned &SrcOpIdx2) const; 536 virtual bool PredicateInstruction(MachineInstr *MI, 537 const SmallVectorImpl<MachineOperand> &Pred) const; 538 virtual void reMaterialize(MachineBasicBlock &MBB, 539 MachineBasicBlock::iterator MI, 540 unsigned DestReg, unsigned SubReg, 541 const MachineInstr *Orig) const; 542 virtual bool isIdentical(const MachineInstr *MI, 543 const MachineInstr *Other, 544 const MachineRegisterInfo *MRI) const; 545 546 virtual unsigned GetFunctionSizeInBytes(const MachineFunction &MF) const; 547}; 548 549} // End llvm namespace 550 551#endif 552