TargetInstrInfo.h revision cbad42cfd1cc93a41ff26ea2e8895bfbc09f54f2
1//===-- llvm/Target/TargetInstrInfo.h - Instruction Info --------*- C++ -*-===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This file describes the target machine instruction set to the code generator. 11// 12//===----------------------------------------------------------------------===// 13 14#ifndef LLVM_TARGET_TARGETINSTRINFO_H 15#define LLVM_TARGET_TARGETINSTRINFO_H 16 17#include "llvm/Target/TargetInstrDesc.h" 18#include "llvm/CodeGen/MachineFunction.h" 19 20namespace llvm { 21 22class TargetRegisterClass; 23class LiveVariables; 24class CalleeSavedInfo; 25class SDNode; 26class SelectionDAG; 27 28template<class T> class SmallVectorImpl; 29 30 31//--------------------------------------------------------------------------- 32/// 33/// TargetInstrInfo - Interface to description of machine instruction set 34/// 35class TargetInstrInfo { 36 const TargetInstrDesc *Descriptors; // Raw array to allow static init'n 37 unsigned NumOpcodes; // Number of entries in the desc array 38 39 TargetInstrInfo(const TargetInstrInfo &); // DO NOT IMPLEMENT 40 void operator=(const TargetInstrInfo &); // DO NOT IMPLEMENT 41public: 42 TargetInstrInfo(const TargetInstrDesc *desc, unsigned NumOpcodes); 43 virtual ~TargetInstrInfo(); 44 45 // Invariant opcodes: All instruction sets have these as their low opcodes. 46 enum { 47 PHI = 0, 48 INLINEASM = 1, 49 DBG_LABEL = 2, 50 EH_LABEL = 3, 51 GC_LABEL = 4, 52 DECLARE = 5, 53 EXTRACT_SUBREG = 6, 54 INSERT_SUBREG = 7, 55 IMPLICIT_DEF = 8, 56 SUBREG_TO_REG = 9 57 }; 58 59 unsigned getNumOpcodes() const { return NumOpcodes; } 60 61 /// get - Return the machine instruction descriptor that corresponds to the 62 /// specified instruction opcode. 63 /// 64 const TargetInstrDesc &get(unsigned Opcode) const { 65 assert(Opcode < NumOpcodes && "Invalid opcode!"); 66 return Descriptors[Opcode]; 67 } 68 69 /// isTriviallyReMaterializable - Return true if the instruction is trivially 70 /// rematerializable, meaning it has no side effects and requires no operands 71 /// that aren't always available. 72 bool isTriviallyReMaterializable(const MachineInstr *MI) const { 73 return MI->getDesc().isRematerializable() && 74 isReallyTriviallyReMaterializable(MI); 75 } 76 77protected: 78 /// isReallyTriviallyReMaterializable - For instructions with opcodes for 79 /// which the M_REMATERIALIZABLE flag is set, this function tests whether the 80 /// instruction itself is actually trivially rematerializable, considering 81 /// its operands. This is used for targets that have instructions that are 82 /// only trivially rematerializable for specific uses. This predicate must 83 /// return false if the instruction has any side effects other than 84 /// producing a value, or if it requres any address registers that are not 85 /// always available. 86 virtual bool isReallyTriviallyReMaterializable(const MachineInstr *MI) const { 87 return true; 88 } 89 90public: 91 /// Return true if the instruction is a register to register move 92 /// and leave the source and dest operands in the passed parameters. 93 virtual bool isMoveInstr(const MachineInstr& MI, 94 unsigned& sourceReg, 95 unsigned& destReg) const { 96 return false; 97 } 98 99 /// isLoadFromStackSlot - If the specified machine instruction is a direct 100 /// load from a stack slot, return the virtual or physical register number of 101 /// the destination along with the FrameIndex of the loaded stack slot. If 102 /// not, return 0. This predicate must return 0 if the instruction has 103 /// any side effects other than loading from the stack slot. 104 virtual unsigned isLoadFromStackSlot(const MachineInstr *MI, 105 int &FrameIndex) const { 106 return 0; 107 } 108 109 /// isStoreToStackSlot - If the specified machine instruction is a direct 110 /// store to a stack slot, return the virtual or physical register number of 111 /// the source reg along with the FrameIndex of the loaded stack slot. If 112 /// not, return 0. This predicate must return 0 if the instruction has 113 /// any side effects other than storing to the stack slot. 114 virtual unsigned isStoreToStackSlot(const MachineInstr *MI, 115 int &FrameIndex) const { 116 return 0; 117 } 118 119 /// reMaterialize - Re-issue the specified 'original' instruction at the 120 /// specific location targeting a new destination register. 121 virtual void reMaterialize(MachineBasicBlock &MBB, 122 MachineBasicBlock::iterator MI, 123 unsigned DestReg, 124 const MachineInstr *Orig) const = 0; 125 126 /// isInvariantLoad - Return true if the specified instruction (which is 127 /// marked mayLoad) is loading from a location whose value is invariant across 128 /// the function. For example, loading a value from the constant pool or from 129 /// from the argument area of a function if it does not change. This should 130 /// only return true of *all* loads the instruction does are invariant (if it 131 /// does multiple loads). 132 virtual bool isInvariantLoad(const MachineInstr *MI) const { 133 return false; 134 } 135 136 /// convertToThreeAddress - This method must be implemented by targets that 137 /// set the M_CONVERTIBLE_TO_3_ADDR flag. When this flag is set, the target 138 /// may be able to convert a two-address instruction into one or more true 139 /// three-address instructions on demand. This allows the X86 target (for 140 /// example) to convert ADD and SHL instructions into LEA instructions if they 141 /// would require register copies due to two-addressness. 142 /// 143 /// This method returns a null pointer if the transformation cannot be 144 /// performed, otherwise it returns the last new instruction. 145 /// 146 virtual MachineInstr * 147 convertToThreeAddress(MachineFunction::iterator &MFI, 148 MachineBasicBlock::iterator &MBBI, LiveVariables *LV) const { 149 return 0; 150 } 151 152 /// commuteInstruction - If a target has any instructions that are commutable, 153 /// but require converting to a different instruction or making non-trivial 154 /// changes to commute them, this method can overloaded to do this. The 155 /// default implementation of this method simply swaps the first two operands 156 /// of MI and returns it. 157 /// 158 /// If a target wants to make more aggressive changes, they can construct and 159 /// return a new machine instruction. If an instruction cannot commute, it 160 /// can also return null. 161 /// 162 /// If NewMI is true, then a new machine instruction must be created. 163 /// 164 virtual MachineInstr *commuteInstruction(MachineInstr *MI, 165 bool NewMI = false) const = 0; 166 167 /// CommuteChangesDestination - Return true if commuting the specified 168 /// instruction will also changes the destination operand. Also return the 169 /// current operand index of the would be new destination register by 170 /// reference. This can happen when the commutable instruction is also a 171 /// two-address instruction. 172 virtual bool CommuteChangesDestination(MachineInstr *MI, 173 unsigned &OpIdx) const = 0; 174 175 /// AnalyzeBranch - Analyze the branching code at the end of MBB, returning 176 /// true if it cannot be understood (e.g. it's a switch dispatch or isn't 177 /// implemented for a target). Upon success, this returns false and returns 178 /// with the following information in various cases: 179 /// 180 /// 1. If this block ends with no branches (it just falls through to its succ) 181 /// just return false, leaving TBB/FBB null. 182 /// 2. If this block ends with only an unconditional branch, it sets TBB to be 183 /// the destination block. 184 /// 3. If this block ends with an conditional branch and it falls through to 185 /// an successor block, it sets TBB to be the branch destination block and a 186 /// list of operands that evaluate the condition. These 187 /// operands can be passed to other TargetInstrInfo methods to create new 188 /// branches. 189 /// 4. If this block ends with an conditional branch and an unconditional 190 /// block, it returns the 'true' destination in TBB, the 'false' destination 191 /// in FBB, and a list of operands that evaluate the condition. These 192 /// operands can be passed to other TargetInstrInfo methods to create new 193 /// branches. 194 /// 195 /// Note that RemoveBranch and InsertBranch must be implemented to support 196 /// cases where this method returns success. 197 /// 198 virtual bool AnalyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB, 199 MachineBasicBlock *&FBB, 200 SmallVectorImpl<MachineOperand> &Cond) const { 201 return true; 202 } 203 204 /// RemoveBranch - Remove the branching code at the end of the specific MBB. 205 /// This is only invoked in cases where AnalyzeBranch returns success. It 206 /// returns the number of instructions that were removed. 207 virtual unsigned RemoveBranch(MachineBasicBlock &MBB) const { 208 assert(0 && "Target didn't implement TargetInstrInfo::RemoveBranch!"); 209 return 0; 210 } 211 212 /// InsertBranch - Insert a branch into the end of the specified 213 /// MachineBasicBlock. This operands to this method are the same as those 214 /// returned by AnalyzeBranch. This is invoked in cases where AnalyzeBranch 215 /// returns success and when an unconditional branch (TBB is non-null, FBB is 216 /// null, Cond is empty) needs to be inserted. It returns the number of 217 /// instructions inserted. 218 virtual unsigned InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB, 219 MachineBasicBlock *FBB, 220 const SmallVectorImpl<MachineOperand> &Cond) const { 221 assert(0 && "Target didn't implement TargetInstrInfo::InsertBranch!"); 222 return 0; 223 } 224 225 /// copyRegToReg - Emit instructions to copy between a pair of registers. It 226 /// returns false if the target does not how to copy between the specified 227 /// registers. 228 virtual bool copyRegToReg(MachineBasicBlock &MBB, 229 MachineBasicBlock::iterator MI, 230 unsigned DestReg, unsigned SrcReg, 231 const TargetRegisterClass *DestRC, 232 const TargetRegisterClass *SrcRC) const { 233 assert(0 && "Target didn't implement TargetInstrInfo::copyRegToReg!"); 234 return false; 235 } 236 237 /// storeRegToStackSlot - Store the specified register of the given register 238 /// class to the specified stack frame index. The store instruction is to be 239 /// added to the given machine basic block before the specified machine 240 /// instruction. If isKill is true, the register operand is the last use and 241 /// must be marked kill. 242 virtual void storeRegToStackSlot(MachineBasicBlock &MBB, 243 MachineBasicBlock::iterator MI, 244 unsigned SrcReg, bool isKill, int FrameIndex, 245 const TargetRegisterClass *RC) const { 246 assert(0 && "Target didn't implement TargetInstrInfo::storeRegToStackSlot!"); 247 } 248 249 /// storeRegToAddr - Store the specified register of the given register class 250 /// to the specified address. The store instruction is to be added to the 251 /// given machine basic block before the specified machine instruction. If 252 /// isKill is true, the register operand is the last use and must be marked 253 /// kill. 254 virtual void storeRegToAddr(MachineFunction &MF, unsigned SrcReg, bool isKill, 255 SmallVectorImpl<MachineOperand> &Addr, 256 const TargetRegisterClass *RC, 257 SmallVectorImpl<MachineInstr*> &NewMIs) const { 258 assert(0 && "Target didn't implement TargetInstrInfo::storeRegToAddr!"); 259 } 260 261 /// loadRegFromStackSlot - Load the specified register of the given register 262 /// class from the specified stack frame index. The load instruction is to be 263 /// added to the given machine basic block before the specified machine 264 /// instruction. 265 virtual void loadRegFromStackSlot(MachineBasicBlock &MBB, 266 MachineBasicBlock::iterator MI, 267 unsigned DestReg, int FrameIndex, 268 const TargetRegisterClass *RC) const { 269 assert(0 && "Target didn't implement TargetInstrInfo::loadRegFromStackSlot!"); 270 } 271 272 /// loadRegFromAddr - Load the specified register of the given register class 273 /// class from the specified address. The load instruction is to be added to 274 /// the given machine basic block before the specified machine instruction. 275 virtual void loadRegFromAddr(MachineFunction &MF, unsigned DestReg, 276 SmallVectorImpl<MachineOperand> &Addr, 277 const TargetRegisterClass *RC, 278 SmallVectorImpl<MachineInstr*> &NewMIs) const { 279 assert(0 && "Target didn't implement TargetInstrInfo::loadRegFromAddr!"); 280 } 281 282 /// spillCalleeSavedRegisters - Issues instruction(s) to spill all callee 283 /// saved registers and returns true if it isn't possible / profitable to do 284 /// so by issuing a series of store instructions via 285 /// storeRegToStackSlot(). Returns false otherwise. 286 virtual bool spillCalleeSavedRegisters(MachineBasicBlock &MBB, 287 MachineBasicBlock::iterator MI, 288 const std::vector<CalleeSavedInfo> &CSI) const { 289 return false; 290 } 291 292 /// restoreCalleeSavedRegisters - Issues instruction(s) to restore all callee 293 /// saved registers and returns true if it isn't possible / profitable to do 294 /// so by issuing a series of load instructions via loadRegToStackSlot(). 295 /// Returns false otherwise. 296 virtual bool restoreCalleeSavedRegisters(MachineBasicBlock &MBB, 297 MachineBasicBlock::iterator MI, 298 const std::vector<CalleeSavedInfo> &CSI) const { 299 return false; 300 } 301 302 /// foldMemoryOperand - Attempt to fold a load or store of the specified stack 303 /// slot into the specified machine instruction for the specified operand(s). 304 /// If this is possible, a new instruction is returned with the specified 305 /// operand folded, otherwise NULL is returned. The client is responsible for 306 /// removing the old instruction and adding the new one in the instruction 307 /// stream. 308 virtual MachineInstr* foldMemoryOperand(MachineFunction &MF, 309 MachineInstr* MI, 310 const SmallVectorImpl<unsigned> &Ops, 311 int FrameIndex) const { 312 return 0; 313 } 314 315 /// foldMemoryOperand - Same as the previous version except it allows folding 316 /// of any load and store from / to any address, not just from a specific 317 /// stack slot. 318 virtual MachineInstr* foldMemoryOperand(MachineFunction &MF, 319 MachineInstr* MI, 320 const SmallVectorImpl<unsigned> &Ops, 321 MachineInstr* LoadMI) const { 322 return 0; 323 } 324 325 /// canFoldMemoryOperand - Returns true if the specified load / store is 326 /// folding is possible. 327 virtual 328 bool canFoldMemoryOperand(const MachineInstr *MI, 329 const SmallVectorImpl<unsigned> &Ops) const { 330 return false; 331 } 332 333 /// unfoldMemoryOperand - Separate a single instruction which folded a load or 334 /// a store or a load and a store into two or more instruction. If this is 335 /// possible, returns true as well as the new instructions by reference. 336 virtual bool unfoldMemoryOperand(MachineFunction &MF, MachineInstr *MI, 337 unsigned Reg, bool UnfoldLoad, bool UnfoldStore, 338 SmallVectorImpl<MachineInstr*> &NewMIs) const{ 339 return false; 340 } 341 342 virtual bool unfoldMemoryOperand(SelectionDAG &DAG, SDNode *N, 343 SmallVectorImpl<SDNode*> &NewNodes) const { 344 return false; 345 } 346 347 /// getOpcodeAfterMemoryUnfold - Returns the opcode of the would be new 348 /// instruction after load / store are unfolded from an instruction of the 349 /// specified opcode. It returns zero if the specified unfolding is not 350 /// possible. 351 virtual unsigned getOpcodeAfterMemoryUnfold(unsigned Opc, 352 bool UnfoldLoad, bool UnfoldStore) const { 353 return 0; 354 } 355 356 /// BlockHasNoFallThrough - Return true if the specified block does not 357 /// fall-through into its successor block. This is primarily used when a 358 /// branch is unanalyzable. It is useful for things like unconditional 359 /// indirect branches (jump tables). 360 virtual bool BlockHasNoFallThrough(const MachineBasicBlock &MBB) const { 361 return false; 362 } 363 364 /// ReverseBranchCondition - Reverses the branch condition of the specified 365 /// condition list, returning false on success and true if it cannot be 366 /// reversed. 367 virtual 368 bool ReverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const { 369 return true; 370 } 371 372 /// insertNoop - Insert a noop into the instruction stream at the specified 373 /// point. 374 virtual void insertNoop(MachineBasicBlock &MBB, 375 MachineBasicBlock::iterator MI) const { 376 assert(0 && "Target didn't implement insertNoop!"); 377 abort(); 378 } 379 380 /// isPredicated - Returns true if the instruction is already predicated. 381 /// 382 virtual bool isPredicated(const MachineInstr *MI) const { 383 return false; 384 } 385 386 /// isUnpredicatedTerminator - Returns true if the instruction is a 387 /// terminator instruction that has not been predicated. 388 virtual bool isUnpredicatedTerminator(const MachineInstr *MI) const; 389 390 /// PredicateInstruction - Convert the instruction into a predicated 391 /// instruction. It returns true if the operation was successful. 392 virtual 393 bool PredicateInstruction(MachineInstr *MI, 394 const SmallVectorImpl<MachineOperand> &Pred) const = 0; 395 396 /// SubsumesPredicate - Returns true if the first specified predicate 397 /// subsumes the second, e.g. GE subsumes GT. 398 virtual 399 bool SubsumesPredicate(const SmallVectorImpl<MachineOperand> &Pred1, 400 const SmallVectorImpl<MachineOperand> &Pred2) const { 401 return false; 402 } 403 404 /// DefinesPredicate - If the specified instruction defines any predicate 405 /// or condition code register(s) used for predication, returns true as well 406 /// as the definition predicate(s) by reference. 407 virtual bool DefinesPredicate(MachineInstr *MI, 408 std::vector<MachineOperand> &Pred) const { 409 return false; 410 } 411 412 /// IgnoreRegisterClassBarriers - Returns true if pre-register allocation 413 /// live interval splitting pass should ignore barriers of the specified 414 /// register class. 415 virtual bool IgnoreRegisterClassBarriers(const TargetRegisterClass *RC) const{ 416 return true; 417 } 418 419 /// getPointerRegClass - Returns a TargetRegisterClass used for pointer 420 /// values. 421 virtual const TargetRegisterClass *getPointerRegClass() const { 422 assert(0 && "Target didn't implement getPointerRegClass!"); 423 abort(); 424 return 0; // Must return a value in order to compile with VS 2005 425 } 426 427 /// GetInstSize - Returns the size of the specified Instruction. 428 /// 429 virtual unsigned GetInstSizeInBytes(const MachineInstr *MI) const { 430 assert(0 && "Target didn't implement TargetInstrInfo::GetInstSize!"); 431 return 0; 432 } 433 434 /// GetFunctionSizeInBytes - Returns the size of the specified MachineFunction. 435 /// 436 virtual unsigned GetFunctionSizeInBytes(const MachineFunction &MF) const = 0; 437}; 438 439/// TargetInstrInfoImpl - This is the default implementation of 440/// TargetInstrInfo, which just provides a couple of default implementations 441/// for various methods. This separated out because it is implemented in 442/// libcodegen, not in libtarget. 443class TargetInstrInfoImpl : public TargetInstrInfo { 444protected: 445 TargetInstrInfoImpl(const TargetInstrDesc *desc, unsigned NumOpcodes) 446 : TargetInstrInfo(desc, NumOpcodes) {} 447public: 448 virtual MachineInstr *commuteInstruction(MachineInstr *MI, 449 bool NewMI = false) const; 450 virtual bool CommuteChangesDestination(MachineInstr *MI, 451 unsigned &OpIdx) const; 452 virtual bool PredicateInstruction(MachineInstr *MI, 453 const SmallVectorImpl<MachineOperand> &Pred) const; 454 virtual void reMaterialize(MachineBasicBlock &MBB, 455 MachineBasicBlock::iterator MI, 456 unsigned DestReg, 457 const MachineInstr *Orig) const; 458 virtual unsigned GetFunctionSizeInBytes(const MachineFunction &MF) const; 459}; 460 461} // End llvm namespace 462 463#endif 464