TargetInstrInfo.h revision cd775ceff0b25a0b026f643a7990c2924bd310a3
1//===-- llvm/Target/TargetInstrInfo.h - Instruction Info --------*- C++ -*-===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This file describes the target machine instruction set to the code generator. 11// 12//===----------------------------------------------------------------------===// 13 14#ifndef LLVM_TARGET_TARGETINSTRINFO_H 15#define LLVM_TARGET_TARGETINSTRINFO_H 16 17#include "llvm/Target/TargetInstrDesc.h" 18#include "llvm/CodeGen/MachineFunction.h" 19 20namespace llvm { 21 22class InstrItineraryData; 23class LiveVariables; 24class MCAsmInfo; 25class MachineMemOperand; 26class MachineRegisterInfo; 27class MDNode; 28class MCInst; 29class SDNode; 30class ScheduleHazardRecognizer; 31class SelectionDAG; 32class TargetRegisterClass; 33class TargetRegisterInfo; 34 35template<class T> class SmallVectorImpl; 36 37 38//--------------------------------------------------------------------------- 39/// 40/// TargetInstrInfo - Interface to description of machine instruction set 41/// 42class TargetInstrInfo { 43 const TargetInstrDesc *Descriptors; // Raw array to allow static init'n 44 unsigned NumOpcodes; // Number of entries in the desc array 45 46 TargetInstrInfo(const TargetInstrInfo &); // DO NOT IMPLEMENT 47 void operator=(const TargetInstrInfo &); // DO NOT IMPLEMENT 48public: 49 TargetInstrInfo(const TargetInstrDesc *desc, unsigned NumOpcodes); 50 virtual ~TargetInstrInfo(); 51 52 unsigned getNumOpcodes() const { return NumOpcodes; } 53 54 /// get - Return the machine instruction descriptor that corresponds to the 55 /// specified instruction opcode. 56 /// 57 const TargetInstrDesc &get(unsigned Opcode) const { 58 assert(Opcode < NumOpcodes && "Invalid opcode!"); 59 return Descriptors[Opcode]; 60 } 61 62 /// isTriviallyReMaterializable - Return true if the instruction is trivially 63 /// rematerializable, meaning it has no side effects and requires no operands 64 /// that aren't always available. 65 bool isTriviallyReMaterializable(const MachineInstr *MI, 66 AliasAnalysis *AA = 0) const { 67 return MI->getOpcode() == TargetOpcode::IMPLICIT_DEF || 68 (MI->getDesc().isRematerializable() && 69 (isReallyTriviallyReMaterializable(MI, AA) || 70 isReallyTriviallyReMaterializableGeneric(MI, AA))); 71 } 72 73protected: 74 /// isReallyTriviallyReMaterializable - For instructions with opcodes for 75 /// which the M_REMATERIALIZABLE flag is set, this hook lets the target 76 /// specify whether the instruction is actually trivially rematerializable, 77 /// taking into consideration its operands. This predicate must return false 78 /// if the instruction has any side effects other than producing a value, or 79 /// if it requres any address registers that are not always available. 80 virtual bool isReallyTriviallyReMaterializable(const MachineInstr *MI, 81 AliasAnalysis *AA) const { 82 return false; 83 } 84 85private: 86 /// isReallyTriviallyReMaterializableGeneric - For instructions with opcodes 87 /// for which the M_REMATERIALIZABLE flag is set and the target hook 88 /// isReallyTriviallyReMaterializable returns false, this function does 89 /// target-independent tests to determine if the instruction is really 90 /// trivially rematerializable. 91 bool isReallyTriviallyReMaterializableGeneric(const MachineInstr *MI, 92 AliasAnalysis *AA) const; 93 94public: 95 /// isCoalescableExtInstr - Return true if the instruction is a "coalescable" 96 /// extension instruction. That is, it's like a copy where it's legal for the 97 /// source to overlap the destination. e.g. X86::MOVSX64rr32. If this returns 98 /// true, then it's expected the pre-extension value is available as a subreg 99 /// of the result register. This also returns the sub-register index in 100 /// SubIdx. 101 virtual bool isCoalescableExtInstr(const MachineInstr &MI, 102 unsigned &SrcReg, unsigned &DstReg, 103 unsigned &SubIdx) const { 104 return false; 105 } 106 107 /// isLoadFromStackSlot - If the specified machine instruction is a direct 108 /// load from a stack slot, return the virtual or physical register number of 109 /// the destination along with the FrameIndex of the loaded stack slot. If 110 /// not, return 0. This predicate must return 0 if the instruction has 111 /// any side effects other than loading from the stack slot. 112 virtual unsigned isLoadFromStackSlot(const MachineInstr *MI, 113 int &FrameIndex) const { 114 return 0; 115 } 116 117 /// isLoadFromStackSlotPostFE - Check for post-frame ptr elimination 118 /// stack locations as well. This uses a heuristic so it isn't 119 /// reliable for correctness. 120 virtual unsigned isLoadFromStackSlotPostFE(const MachineInstr *MI, 121 int &FrameIndex) const { 122 return 0; 123 } 124 125 /// hasLoadFromStackSlot - If the specified machine instruction has 126 /// a load from a stack slot, return true along with the FrameIndex 127 /// of the loaded stack slot and the machine mem operand containing 128 /// the reference. If not, return false. Unlike 129 /// isLoadFromStackSlot, this returns true for any instructions that 130 /// loads from the stack. This is just a hint, as some cases may be 131 /// missed. 132 virtual bool hasLoadFromStackSlot(const MachineInstr *MI, 133 const MachineMemOperand *&MMO, 134 int &FrameIndex) const { 135 return 0; 136 } 137 138 /// isStoreToStackSlot - If the specified machine instruction is a direct 139 /// store to a stack slot, return the virtual or physical register number of 140 /// the source reg along with the FrameIndex of the loaded stack slot. If 141 /// not, return 0. This predicate must return 0 if the instruction has 142 /// any side effects other than storing to the stack slot. 143 virtual unsigned isStoreToStackSlot(const MachineInstr *MI, 144 int &FrameIndex) const { 145 return 0; 146 } 147 148 /// isStoreToStackSlotPostFE - Check for post-frame ptr elimination 149 /// stack locations as well. This uses a heuristic so it isn't 150 /// reliable for correctness. 151 virtual unsigned isStoreToStackSlotPostFE(const MachineInstr *MI, 152 int &FrameIndex) const { 153 return 0; 154 } 155 156 /// hasStoreToStackSlot - If the specified machine instruction has a 157 /// store to a stack slot, return true along with the FrameIndex of 158 /// the loaded stack slot and the machine mem operand containing the 159 /// reference. If not, return false. Unlike isStoreToStackSlot, 160 /// this returns true for any instructions that stores to the 161 /// stack. This is just a hint, as some cases may be missed. 162 virtual bool hasStoreToStackSlot(const MachineInstr *MI, 163 const MachineMemOperand *&MMO, 164 int &FrameIndex) const { 165 return 0; 166 } 167 168 /// reMaterialize - Re-issue the specified 'original' instruction at the 169 /// specific location targeting a new destination register. 170 /// The register in Orig->getOperand(0).getReg() will be substituted by 171 /// DestReg:SubIdx. Any existing subreg index is preserved or composed with 172 /// SubIdx. 173 virtual void reMaterialize(MachineBasicBlock &MBB, 174 MachineBasicBlock::iterator MI, 175 unsigned DestReg, unsigned SubIdx, 176 const MachineInstr *Orig, 177 const TargetRegisterInfo &TRI) const = 0; 178 179 /// scheduleTwoAddrSource - Schedule the copy / re-mat of the source of the 180 /// two-addrss instruction inserted by two-address pass. 181 virtual void scheduleTwoAddrSource(MachineInstr *SrcMI, 182 MachineInstr *UseMI, 183 const TargetRegisterInfo &TRI) const { 184 // Do nothing. 185 } 186 187 /// duplicate - Create a duplicate of the Orig instruction in MF. This is like 188 /// MachineFunction::CloneMachineInstr(), but the target may update operands 189 /// that are required to be unique. 190 /// 191 /// The instruction must be duplicable as indicated by isNotDuplicable(). 192 virtual MachineInstr *duplicate(MachineInstr *Orig, 193 MachineFunction &MF) const = 0; 194 195 /// convertToThreeAddress - This method must be implemented by targets that 196 /// set the M_CONVERTIBLE_TO_3_ADDR flag. When this flag is set, the target 197 /// may be able to convert a two-address instruction into one or more true 198 /// three-address instructions on demand. This allows the X86 target (for 199 /// example) to convert ADD and SHL instructions into LEA instructions if they 200 /// would require register copies due to two-addressness. 201 /// 202 /// This method returns a null pointer if the transformation cannot be 203 /// performed, otherwise it returns the last new instruction. 204 /// 205 virtual MachineInstr * 206 convertToThreeAddress(MachineFunction::iterator &MFI, 207 MachineBasicBlock::iterator &MBBI, LiveVariables *LV) const { 208 return 0; 209 } 210 211 /// commuteInstruction - If a target has any instructions that are 212 /// commutable but require converting to different instructions or making 213 /// non-trivial changes to commute them, this method can overloaded to do 214 /// that. The default implementation simply swaps the commutable operands. 215 /// If NewMI is false, MI is modified in place and returned; otherwise, a 216 /// new machine instruction is created and returned. Do not call this 217 /// method for a non-commutable instruction, but there may be some cases 218 /// where this method fails and returns null. 219 virtual MachineInstr *commuteInstruction(MachineInstr *MI, 220 bool NewMI = false) const = 0; 221 222 /// findCommutedOpIndices - If specified MI is commutable, return the two 223 /// operand indices that would swap value. Return false if the instruction 224 /// is not in a form which this routine understands. 225 virtual bool findCommutedOpIndices(MachineInstr *MI, unsigned &SrcOpIdx1, 226 unsigned &SrcOpIdx2) const = 0; 227 228 /// produceSameValue - Return true if two machine instructions would produce 229 /// identical values. By default, this is only true when the two instructions 230 /// are deemed identical except for defs. 231 virtual bool produceSameValue(const MachineInstr *MI0, 232 const MachineInstr *MI1) const = 0; 233 234 /// AnalyzeBranch - Analyze the branching code at the end of MBB, returning 235 /// true if it cannot be understood (e.g. it's a switch dispatch or isn't 236 /// implemented for a target). Upon success, this returns false and returns 237 /// with the following information in various cases: 238 /// 239 /// 1. If this block ends with no branches (it just falls through to its succ) 240 /// just return false, leaving TBB/FBB null. 241 /// 2. If this block ends with only an unconditional branch, it sets TBB to be 242 /// the destination block. 243 /// 3. If this block ends with a conditional branch and it falls through to a 244 /// successor block, it sets TBB to be the branch destination block and a 245 /// list of operands that evaluate the condition. These operands can be 246 /// passed to other TargetInstrInfo methods to create new branches. 247 /// 4. If this block ends with a conditional branch followed by an 248 /// unconditional branch, it returns the 'true' destination in TBB, the 249 /// 'false' destination in FBB, and a list of operands that evaluate the 250 /// condition. These operands can be passed to other TargetInstrInfo 251 /// methods to create new branches. 252 /// 253 /// Note that RemoveBranch and InsertBranch must be implemented to support 254 /// cases where this method returns success. 255 /// 256 /// If AllowModify is true, then this routine is allowed to modify the basic 257 /// block (e.g. delete instructions after the unconditional branch). 258 /// 259 virtual bool AnalyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB, 260 MachineBasicBlock *&FBB, 261 SmallVectorImpl<MachineOperand> &Cond, 262 bool AllowModify = false) const { 263 return true; 264 } 265 266 /// RemoveBranch - Remove the branching code at the end of the specific MBB. 267 /// This is only invoked in cases where AnalyzeBranch returns success. It 268 /// returns the number of instructions that were removed. 269 virtual unsigned RemoveBranch(MachineBasicBlock &MBB) const { 270 assert(0 && "Target didn't implement TargetInstrInfo::RemoveBranch!"); 271 return 0; 272 } 273 274 /// InsertBranch - Insert branch code into the end of the specified 275 /// MachineBasicBlock. The operands to this method are the same as those 276 /// returned by AnalyzeBranch. This is only invoked in cases where 277 /// AnalyzeBranch returns success. It returns the number of instructions 278 /// inserted. 279 /// 280 /// It is also invoked by tail merging to add unconditional branches in 281 /// cases where AnalyzeBranch doesn't apply because there was no original 282 /// branch to analyze. At least this much must be implemented, else tail 283 /// merging needs to be disabled. 284 virtual unsigned InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB, 285 MachineBasicBlock *FBB, 286 const SmallVectorImpl<MachineOperand> &Cond, 287 DebugLoc DL) const { 288 assert(0 && "Target didn't implement TargetInstrInfo::InsertBranch!"); 289 return 0; 290 } 291 292 /// ReplaceTailWithBranchTo - Delete the instruction OldInst and everything 293 /// after it, replacing it with an unconditional branch to NewDest. This is 294 /// used by the tail merging pass. 295 virtual void ReplaceTailWithBranchTo(MachineBasicBlock::iterator Tail, 296 MachineBasicBlock *NewDest) const = 0; 297 298 /// isLegalToSplitMBBAt - Return true if it's legal to split the given basic 299 /// block at the specified instruction (i.e. instruction would be the start 300 /// of a new basic block). 301 virtual bool isLegalToSplitMBBAt(MachineBasicBlock &MBB, 302 MachineBasicBlock::iterator MBBI) const { 303 return true; 304 } 305 306 /// isProfitableToIfCvt - Return true if it's profitable to predicate 307 /// instructions with accumulated instruction latency of "NumCycles" 308 /// of the specified basic block, where the probability of the instructions 309 /// being executed is given by Probability, and Confidence is a measure 310 /// of our confidence that it will be properly predicted. 311 virtual 312 bool isProfitableToIfCvt(MachineBasicBlock &MBB, unsigned NumCyles, 313 unsigned ExtraPredCycles, 314 float Probability, float Confidence) const { 315 return false; 316 } 317 318 /// isProfitableToIfCvt - Second variant of isProfitableToIfCvt, this one 319 /// checks for the case where two basic blocks from true and false path 320 /// of a if-then-else (diamond) are predicated on mutally exclusive 321 /// predicates, where the probability of the true path being taken is given 322 /// by Probability, and Confidence is a measure of our confidence that it 323 /// will be properly predicted. 324 virtual bool 325 isProfitableToIfCvt(MachineBasicBlock &TMBB, 326 unsigned NumTCycles, unsigned ExtraTCycles, 327 MachineBasicBlock &FMBB, 328 unsigned NumFCycles, unsigned ExtraFCycles, 329 float Probability, float Confidence) const { 330 return false; 331 } 332 333 /// isProfitableToDupForIfCvt - Return true if it's profitable for 334 /// if-converter to duplicate instructions of specified accumulated 335 /// instruction latencies in the specified MBB to enable if-conversion. 336 /// The probability of the instructions being executed is given by 337 /// Probability, and Confidence is a measure of our confidence that it 338 /// will be properly predicted. 339 virtual bool 340 isProfitableToDupForIfCvt(MachineBasicBlock &MBB, unsigned NumCyles, 341 float Probability, float Confidence) const { 342 return false; 343 } 344 345 /// copyPhysReg - Emit instructions to copy a pair of physical registers. 346 virtual void copyPhysReg(MachineBasicBlock &MBB, 347 MachineBasicBlock::iterator MI, DebugLoc DL, 348 unsigned DestReg, unsigned SrcReg, 349 bool KillSrc) const { 350 assert(0 && "Target didn't implement TargetInstrInfo::copyPhysReg!"); 351 } 352 353 /// storeRegToStackSlot - Store the specified register of the given register 354 /// class to the specified stack frame index. The store instruction is to be 355 /// added to the given machine basic block before the specified machine 356 /// instruction. If isKill is true, the register operand is the last use and 357 /// must be marked kill. 358 virtual void storeRegToStackSlot(MachineBasicBlock &MBB, 359 MachineBasicBlock::iterator MI, 360 unsigned SrcReg, bool isKill, int FrameIndex, 361 const TargetRegisterClass *RC, 362 const TargetRegisterInfo *TRI) const { 363 assert(0 && "Target didn't implement TargetInstrInfo::storeRegToStackSlot!"); 364 } 365 366 /// loadRegFromStackSlot - Load the specified register of the given register 367 /// class from the specified stack frame index. The load instruction is to be 368 /// added to the given machine basic block before the specified machine 369 /// instruction. 370 virtual void loadRegFromStackSlot(MachineBasicBlock &MBB, 371 MachineBasicBlock::iterator MI, 372 unsigned DestReg, int FrameIndex, 373 const TargetRegisterClass *RC, 374 const TargetRegisterInfo *TRI) const { 375 assert(0 && "Target didn't implement TargetInstrInfo::loadRegFromStackSlot!"); 376 } 377 378 /// emitFrameIndexDebugValue - Emit a target-dependent form of 379 /// DBG_VALUE encoding the address of a frame index. Addresses would 380 /// normally be lowered the same way as other addresses on the target, 381 /// e.g. in load instructions. For targets that do not support this 382 /// the debug info is simply lost. 383 /// If you add this for a target you should handle this DBG_VALUE in the 384 /// target-specific AsmPrinter code as well; you will probably get invalid 385 /// assembly output if you don't. 386 virtual MachineInstr *emitFrameIndexDebugValue(MachineFunction &MF, 387 int FrameIx, 388 uint64_t Offset, 389 const MDNode *MDPtr, 390 DebugLoc dl) const { 391 return 0; 392 } 393 394 /// foldMemoryOperand - Attempt to fold a load or store of the specified stack 395 /// slot into the specified machine instruction for the specified operand(s). 396 /// If this is possible, a new instruction is returned with the specified 397 /// operand folded, otherwise NULL is returned. 398 /// The new instruction is inserted before MI, and the client is responsible 399 /// for removing the old instruction. 400 MachineInstr* foldMemoryOperand(MachineBasicBlock::iterator MI, 401 const SmallVectorImpl<unsigned> &Ops, 402 int FrameIndex) const; 403 404 /// foldMemoryOperand - Same as the previous version except it allows folding 405 /// of any load and store from / to any address, not just from a specific 406 /// stack slot. 407 MachineInstr* foldMemoryOperand(MachineBasicBlock::iterator MI, 408 const SmallVectorImpl<unsigned> &Ops, 409 MachineInstr* LoadMI) const; 410 411protected: 412 /// foldMemoryOperandImpl - Target-dependent implementation for 413 /// foldMemoryOperand. Target-independent code in foldMemoryOperand will 414 /// take care of adding a MachineMemOperand to the newly created instruction. 415 virtual MachineInstr* foldMemoryOperandImpl(MachineFunction &MF, 416 MachineInstr* MI, 417 const SmallVectorImpl<unsigned> &Ops, 418 int FrameIndex) const { 419 return 0; 420 } 421 422 /// foldMemoryOperandImpl - Target-dependent implementation for 423 /// foldMemoryOperand. Target-independent code in foldMemoryOperand will 424 /// take care of adding a MachineMemOperand to the newly created instruction. 425 virtual MachineInstr* foldMemoryOperandImpl(MachineFunction &MF, 426 MachineInstr* MI, 427 const SmallVectorImpl<unsigned> &Ops, 428 MachineInstr* LoadMI) const { 429 return 0; 430 } 431 432public: 433 /// canFoldMemoryOperand - Returns true for the specified load / store if 434 /// folding is possible. 435 virtual 436 bool canFoldMemoryOperand(const MachineInstr *MI, 437 const SmallVectorImpl<unsigned> &Ops) const =0; 438 439 /// unfoldMemoryOperand - Separate a single instruction which folded a load or 440 /// a store or a load and a store into two or more instruction. If this is 441 /// possible, returns true as well as the new instructions by reference. 442 virtual bool unfoldMemoryOperand(MachineFunction &MF, MachineInstr *MI, 443 unsigned Reg, bool UnfoldLoad, bool UnfoldStore, 444 SmallVectorImpl<MachineInstr*> &NewMIs) const{ 445 return false; 446 } 447 448 virtual bool unfoldMemoryOperand(SelectionDAG &DAG, SDNode *N, 449 SmallVectorImpl<SDNode*> &NewNodes) const { 450 return false; 451 } 452 453 /// getOpcodeAfterMemoryUnfold - Returns the opcode of the would be new 454 /// instruction after load / store are unfolded from an instruction of the 455 /// specified opcode. It returns zero if the specified unfolding is not 456 /// possible. If LoadRegIndex is non-null, it is filled in with the operand 457 /// index of the operand which will hold the register holding the loaded 458 /// value. 459 virtual unsigned getOpcodeAfterMemoryUnfold(unsigned Opc, 460 bool UnfoldLoad, bool UnfoldStore, 461 unsigned *LoadRegIndex = 0) const { 462 return 0; 463 } 464 465 /// areLoadsFromSameBasePtr - This is used by the pre-regalloc scheduler 466 /// to determine if two loads are loading from the same base address. It 467 /// should only return true if the base pointers are the same and the 468 /// only differences between the two addresses are the offset. It also returns 469 /// the offsets by reference. 470 virtual bool areLoadsFromSameBasePtr(SDNode *Load1, SDNode *Load2, 471 int64_t &Offset1, int64_t &Offset2) const { 472 return false; 473 } 474 475 /// shouldScheduleLoadsNear - This is a used by the pre-regalloc scheduler to 476 /// determine (in conjuction with areLoadsFromSameBasePtr) if two loads should 477 /// be scheduled togther. On some targets if two loads are loading from 478 /// addresses in the same cache line, it's better if they are scheduled 479 /// together. This function takes two integers that represent the load offsets 480 /// from the common base address. It returns true if it decides it's desirable 481 /// to schedule the two loads together. "NumLoads" is the number of loads that 482 /// have already been scheduled after Load1. 483 virtual bool shouldScheduleLoadsNear(SDNode *Load1, SDNode *Load2, 484 int64_t Offset1, int64_t Offset2, 485 unsigned NumLoads) const { 486 return false; 487 } 488 489 /// ReverseBranchCondition - Reverses the branch condition of the specified 490 /// condition list, returning false on success and true if it cannot be 491 /// reversed. 492 virtual 493 bool ReverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const { 494 return true; 495 } 496 497 /// insertNoop - Insert a noop into the instruction stream at the specified 498 /// point. 499 virtual void insertNoop(MachineBasicBlock &MBB, 500 MachineBasicBlock::iterator MI) const; 501 502 503 /// getNoopForMachoTarget - Return the noop instruction to use for a noop. 504 virtual void getNoopForMachoTarget(MCInst &NopInst) const { 505 // Default to just using 'nop' string. 506 } 507 508 509 /// isPredicated - Returns true if the instruction is already predicated. 510 /// 511 virtual bool isPredicated(const MachineInstr *MI) const { 512 return false; 513 } 514 515 /// isUnpredicatedTerminator - Returns true if the instruction is a 516 /// terminator instruction that has not been predicated. 517 virtual bool isUnpredicatedTerminator(const MachineInstr *MI) const; 518 519 /// PredicateInstruction - Convert the instruction into a predicated 520 /// instruction. It returns true if the operation was successful. 521 virtual 522 bool PredicateInstruction(MachineInstr *MI, 523 const SmallVectorImpl<MachineOperand> &Pred) const = 0; 524 525 /// SubsumesPredicate - Returns true if the first specified predicate 526 /// subsumes the second, e.g. GE subsumes GT. 527 virtual 528 bool SubsumesPredicate(const SmallVectorImpl<MachineOperand> &Pred1, 529 const SmallVectorImpl<MachineOperand> &Pred2) const { 530 return false; 531 } 532 533 /// DefinesPredicate - If the specified instruction defines any predicate 534 /// or condition code register(s) used for predication, returns true as well 535 /// as the definition predicate(s) by reference. 536 virtual bool DefinesPredicate(MachineInstr *MI, 537 std::vector<MachineOperand> &Pred) const { 538 return false; 539 } 540 541 /// isPredicable - Return true if the specified instruction can be predicated. 542 /// By default, this returns true for every instruction with a 543 /// PredicateOperand. 544 virtual bool isPredicable(MachineInstr *MI) const { 545 return MI->getDesc().isPredicable(); 546 } 547 548 /// isSafeToMoveRegClassDefs - Return true if it's safe to move a machine 549 /// instruction that defines the specified register class. 550 virtual bool isSafeToMoveRegClassDefs(const TargetRegisterClass *RC) const { 551 return true; 552 } 553 554 /// isSchedulingBoundary - Test if the given instruction should be 555 /// considered a scheduling boundary. This primarily includes labels and 556 /// terminators. 557 virtual bool isSchedulingBoundary(const MachineInstr *MI, 558 const MachineBasicBlock *MBB, 559 const MachineFunction &MF) const = 0; 560 561 /// Measure the specified inline asm to determine an approximation of its 562 /// length. 563 virtual unsigned getInlineAsmLength(const char *Str, 564 const MCAsmInfo &MAI) const; 565 566 /// CreateTargetHazardRecognizer - Allocate and return a hazard recognizer 567 /// to use for this target when scheduling the machine instructions after 568 /// register allocation. 569 virtual ScheduleHazardRecognizer* 570 CreateTargetPostRAHazardRecognizer(const InstrItineraryData*) const = 0; 571 572 /// AnalyzeCompare - For a comparison instruction, return the source register 573 /// in SrcReg and the value it compares against in CmpValue. Return true if 574 /// the comparison instruction can be analyzed. 575 virtual bool AnalyzeCompare(const MachineInstr *MI, 576 unsigned &SrcReg, int &Mask, int &Value) const { 577 return false; 578 } 579 580 /// OptimizeCompareInstr - See if the comparison instruction can be converted 581 /// into something more efficient. E.g., on ARM most instructions can set the 582 /// flags register, obviating the need for a separate CMP. 583 virtual bool OptimizeCompareInstr(MachineInstr *CmpInstr, 584 unsigned SrcReg, int Mask, int Value, 585 const MachineRegisterInfo *MRI) const { 586 return false; 587 } 588 589 /// FoldImmediate - 'Reg' is known to be defined by a move immediate 590 /// instruction, try to fold the immediate into the use instruction. 591 virtual bool FoldImmediate(MachineInstr *UseMI, MachineInstr *DefMI, 592 unsigned Reg, MachineRegisterInfo *MRI) const { 593 return false; 594 } 595 596 /// getNumMicroOps - Return the number of u-operations the given machine 597 /// instruction will be decoded to on the target cpu. 598 virtual unsigned getNumMicroOps(const InstrItineraryData *ItinData, 599 const MachineInstr *MI) const; 600 601 /// getOperandLatency - Compute and return the use operand latency of a given 602 /// pair of def and use. 603 /// In most cases, the static scheduling itinerary was enough to determine the 604 /// operand latency. But it may not be possible for instructions with variable 605 /// number of defs / uses. 606 virtual int getOperandLatency(const InstrItineraryData *ItinData, 607 const MachineInstr *DefMI, unsigned DefIdx, 608 const MachineInstr *UseMI, unsigned UseIdx) const; 609 610 virtual int getOperandLatency(const InstrItineraryData *ItinData, 611 SDNode *DefNode, unsigned DefIdx, 612 SDNode *UseNode, unsigned UseIdx) const; 613 614 /// getInstrLatency - Compute the instruction latency of a given instruction. 615 /// If the instruction has higher cost when predicated, it's returned via 616 /// PredCost. 617 virtual int getInstrLatency(const InstrItineraryData *ItinData, 618 const MachineInstr *MI, 619 unsigned *PredCost = 0) const; 620 621 virtual int getInstrLatency(const InstrItineraryData *ItinData, 622 SDNode *Node) const; 623 624 /// hasHighOperandLatency - Compute operand latency between a def of 'Reg' 625 /// and an use in the current loop, return true if the target considered 626 /// it 'high'. This is used by optimization passes such as machine LICM to 627 /// determine whether it makes sense to hoist an instruction out even in 628 /// high register pressure situation. 629 virtual 630 bool hasHighOperandLatency(const InstrItineraryData *ItinData, 631 const MachineRegisterInfo *MRI, 632 const MachineInstr *DefMI, unsigned DefIdx, 633 const MachineInstr *UseMI, unsigned UseIdx) const { 634 return false; 635 } 636 637 /// hasLowDefLatency - Compute operand latency of a def of 'Reg', return true 638 /// if the target considered it 'low'. 639 virtual 640 bool hasLowDefLatency(const InstrItineraryData *ItinData, 641 const MachineInstr *DefMI, unsigned DefIdx) const; 642}; 643 644/// TargetInstrInfoImpl - This is the default implementation of 645/// TargetInstrInfo, which just provides a couple of default implementations 646/// for various methods. This separated out because it is implemented in 647/// libcodegen, not in libtarget. 648class TargetInstrInfoImpl : public TargetInstrInfo { 649protected: 650 TargetInstrInfoImpl(const TargetInstrDesc *desc, unsigned NumOpcodes) 651 : TargetInstrInfo(desc, NumOpcodes) {} 652public: 653 virtual void ReplaceTailWithBranchTo(MachineBasicBlock::iterator OldInst, 654 MachineBasicBlock *NewDest) const; 655 virtual MachineInstr *commuteInstruction(MachineInstr *MI, 656 bool NewMI = false) const; 657 virtual bool findCommutedOpIndices(MachineInstr *MI, unsigned &SrcOpIdx1, 658 unsigned &SrcOpIdx2) const; 659 virtual bool canFoldMemoryOperand(const MachineInstr *MI, 660 const SmallVectorImpl<unsigned> &Ops) const; 661 virtual bool PredicateInstruction(MachineInstr *MI, 662 const SmallVectorImpl<MachineOperand> &Pred) const; 663 virtual void reMaterialize(MachineBasicBlock &MBB, 664 MachineBasicBlock::iterator MI, 665 unsigned DestReg, unsigned SubReg, 666 const MachineInstr *Orig, 667 const TargetRegisterInfo &TRI) const; 668 virtual MachineInstr *duplicate(MachineInstr *Orig, 669 MachineFunction &MF) const; 670 virtual bool produceSameValue(const MachineInstr *MI0, 671 const MachineInstr *MI1) const; 672 virtual bool isSchedulingBoundary(const MachineInstr *MI, 673 const MachineBasicBlock *MBB, 674 const MachineFunction &MF) const; 675 676 virtual ScheduleHazardRecognizer * 677 CreateTargetPostRAHazardRecognizer(const InstrItineraryData*) const; 678}; 679 680} // End llvm namespace 681 682#endif 683