TargetInstrInfo.h revision d3f99e2bbf5e62261c8948127aacfe9a7d3b2456
1//===-- llvm/Target/TargetInstrInfo.h - Instruction Info --------*- C++ -*-===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This file describes the target machine instructions to the code generator. 11// 12//===----------------------------------------------------------------------===// 13 14#ifndef LLVM_TARGET_TARGETINSTRINFO_H 15#define LLVM_TARGET_TARGETINSTRINFO_H 16 17#include "llvm/Target/TargetInstrDesc.h" 18#include "llvm/CodeGen/MachineFunction.h" 19 20namespace llvm { 21 22class TargetRegisterClass; 23class LiveVariables; 24class CalleeSavedInfo; 25class SDNode; 26class SelectionDAG; 27 28template<class T> class SmallVectorImpl; 29 30 31//--------------------------------------------------------------------------- 32/// 33/// TargetInstrInfo - Interface to description of machine instructions 34/// 35class TargetInstrInfo { 36 const TargetInstrDesc *Descriptors; // Raw array to allow static init'n 37 unsigned NumOpcodes; // Number of entries in the desc array 38 39 TargetInstrInfo(const TargetInstrInfo &); // DO NOT IMPLEMENT 40 void operator=(const TargetInstrInfo &); // DO NOT IMPLEMENT 41public: 42 TargetInstrInfo(const TargetInstrDesc *desc, unsigned NumOpcodes); 43 virtual ~TargetInstrInfo(); 44 45 // Invariant opcodes: All instruction sets have these as their low opcodes. 46 enum { 47 PHI = 0, 48 INLINEASM = 1, 49 LABEL = 2, 50 EXTRACT_SUBREG = 3, 51 INSERT_SUBREG = 4 52 }; 53 54 unsigned getNumOpcodes() const { return NumOpcodes; } 55 56 /// get - Return the machine instruction descriptor that corresponds to the 57 /// specified instruction opcode. 58 /// 59 const TargetInstrDesc &get(unsigned Opcode) const { 60 assert(Opcode < NumOpcodes && "Invalid opcode!"); 61 return Descriptors[Opcode]; 62 } 63 64 /// isTriviallyReMaterializable - Return true if the instruction is trivially 65 /// rematerializable, meaning it has no side effects and requires no operands 66 /// that aren't always available. 67 bool isTriviallyReMaterializable(MachineInstr *MI) const { 68 return MI->getDesc().isRematerializable() && 69 isReallyTriviallyReMaterializable(MI); 70 } 71 72 /// hasUnmodelledSideEffects - Returns true if the instruction has side 73 /// effects that are not captured by any operands of the instruction or other 74 /// flags. 75 bool hasUnmodelledSideEffects(MachineInstr *MI) const { 76 const TargetInstrDesc &TID = MI->getDesc(); 77 if (TID.hasNoSideEffects()) return false; 78 if (!TID.hasConditionalSideEffects()) return true; 79 return !isReallySideEffectFree(MI); // May have side effects 80 } 81protected: 82 /// isReallyTriviallyReMaterializable - For instructions with opcodes for 83 /// which the M_REMATERIALIZABLE flag is set, this function tests whether the 84 /// instruction itself is actually trivially rematerializable, considering 85 /// its operands. This is used for targets that have instructions that are 86 /// only trivially rematerializable for specific uses. This predicate must 87 /// return false if the instruction has any side effects other than 88 /// producing a value, or if it requres any address registers that are not 89 /// always available. 90 virtual bool isReallyTriviallyReMaterializable(MachineInstr *MI) const { 91 return true; 92 } 93 94 /// isReallySideEffectFree - If the M_MAY_HAVE_SIDE_EFFECTS flag is set, this 95 /// method is called to determine if the specific instance of this 96 /// instruction has side effects. This is useful in cases of instructions, 97 /// like loads, which generally always have side effects. A load from a 98 /// constant pool doesn't have side effects, though. So we need to 99 /// differentiate it from the general case. 100 virtual bool isReallySideEffectFree(MachineInstr *MI) const { 101 return false; 102 } 103public: 104 /// Return true if the instruction is a register to register move 105 /// and leave the source and dest operands in the passed parameters. 106 virtual bool isMoveInstr(const MachineInstr& MI, 107 unsigned& sourceReg, 108 unsigned& destReg) const { 109 return false; 110 } 111 112 /// isLoadFromStackSlot - If the specified machine instruction is a direct 113 /// load from a stack slot, return the virtual or physical register number of 114 /// the destination along with the FrameIndex of the loaded stack slot. If 115 /// not, return 0. This predicate must return 0 if the instruction has 116 /// any side effects other than loading from the stack slot. 117 virtual unsigned isLoadFromStackSlot(MachineInstr *MI, int &FrameIndex) const{ 118 return 0; 119 } 120 121 /// isStoreToStackSlot - If the specified machine instruction is a direct 122 /// store to a stack slot, return the virtual or physical register number of 123 /// the source reg along with the FrameIndex of the loaded stack slot. If 124 /// not, return 0. This predicate must return 0 if the instruction has 125 /// any side effects other than storing to the stack slot. 126 virtual unsigned isStoreToStackSlot(MachineInstr *MI, int &FrameIndex) const { 127 return 0; 128 } 129 130 /// convertToThreeAddress - This method must be implemented by targets that 131 /// set the M_CONVERTIBLE_TO_3_ADDR flag. When this flag is set, the target 132 /// may be able to convert a two-address instruction into one or more true 133 /// three-address instructions on demand. This allows the X86 target (for 134 /// example) to convert ADD and SHL instructions into LEA instructions if they 135 /// would require register copies due to two-addressness. 136 /// 137 /// This method returns a null pointer if the transformation cannot be 138 /// performed, otherwise it returns the last new instruction. 139 /// 140 virtual MachineInstr * 141 convertToThreeAddress(MachineFunction::iterator &MFI, 142 MachineBasicBlock::iterator &MBBI, LiveVariables &LV) const { 143 return 0; 144 } 145 146 /// commuteInstruction - If a target has any instructions that are commutable, 147 /// but require converting to a different instruction or making non-trivial 148 /// changes to commute them, this method can overloaded to do this. The 149 /// default implementation of this method simply swaps the first two operands 150 /// of MI and returns it. 151 /// 152 /// If a target wants to make more aggressive changes, they can construct and 153 /// return a new machine instruction. If an instruction cannot commute, it 154 /// can also return null. 155 /// 156 virtual MachineInstr *commuteInstruction(MachineInstr *MI) const = 0; 157 158 /// AnalyzeBranch - Analyze the branching code at the end of MBB, returning 159 /// true if it cannot be understood (e.g. it's a switch dispatch or isn't 160 /// implemented for a target). Upon success, this returns false and returns 161 /// with the following information in various cases: 162 /// 163 /// 1. If this block ends with no branches (it just falls through to its succ) 164 /// just return false, leaving TBB/FBB null. 165 /// 2. If this block ends with only an unconditional branch, it sets TBB to be 166 /// the destination block. 167 /// 3. If this block ends with an conditional branch and it falls through to 168 /// an successor block, it sets TBB to be the branch destination block and a 169 /// list of operands that evaluate the condition. These 170 /// operands can be passed to other TargetInstrInfo methods to create new 171 /// branches. 172 /// 4. If this block ends with an conditional branch and an unconditional 173 /// block, it returns the 'true' destination in TBB, the 'false' destination 174 /// in FBB, and a list of operands that evaluate the condition. These 175 /// operands can be passed to other TargetInstrInfo methods to create new 176 /// branches. 177 /// 178 /// Note that RemoveBranch and InsertBranch must be implemented to support 179 /// cases where this method returns success. 180 /// 181 virtual bool AnalyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB, 182 MachineBasicBlock *&FBB, 183 std::vector<MachineOperand> &Cond) const { 184 return true; 185 } 186 187 /// RemoveBranch - Remove the branching code at the end of the specific MBB. 188 /// this is only invoked in cases where AnalyzeBranch returns success. It 189 /// returns the number of instructions that were removed. 190 virtual unsigned RemoveBranch(MachineBasicBlock &MBB) const { 191 assert(0 && "Target didn't implement TargetInstrInfo::RemoveBranch!"); 192 return 0; 193 } 194 195 /// InsertBranch - Insert a branch into the end of the specified 196 /// MachineBasicBlock. This operands to this method are the same as those 197 /// returned by AnalyzeBranch. This is invoked in cases where AnalyzeBranch 198 /// returns success and when an unconditional branch (TBB is non-null, FBB is 199 /// null, Cond is empty) needs to be inserted. It returns the number of 200 /// instructions inserted. 201 virtual unsigned InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB, 202 MachineBasicBlock *FBB, 203 const std::vector<MachineOperand> &Cond) const { 204 assert(0 && "Target didn't implement TargetInstrInfo::InsertBranch!"); 205 return 0; 206 } 207 208 /// copyRegToReg - Add a copy between a pair of registers 209 virtual void copyRegToReg(MachineBasicBlock &MBB, 210 MachineBasicBlock::iterator MI, 211 unsigned DestReg, unsigned SrcReg, 212 const TargetRegisterClass *DestRC, 213 const TargetRegisterClass *SrcRC) const { 214 assert(0 && "Target didn't implement TargetInstrInfo::copyRegToReg!"); 215 } 216 217 virtual void storeRegToStackSlot(MachineBasicBlock &MBB, 218 MachineBasicBlock::iterator MI, 219 unsigned SrcReg, bool isKill, int FrameIndex, 220 const TargetRegisterClass *RC) const { 221 assert(0 && "Target didn't implement TargetInstrInfo::storeRegToStackSlot!"); 222 } 223 224 virtual void storeRegToAddr(MachineFunction &MF, unsigned SrcReg, bool isKill, 225 SmallVectorImpl<MachineOperand> &Addr, 226 const TargetRegisterClass *RC, 227 SmallVectorImpl<MachineInstr*> &NewMIs) const { 228 assert(0 && "Target didn't implement TargetInstrInfo::storeRegToAddr!"); 229 } 230 231 virtual void loadRegFromStackSlot(MachineBasicBlock &MBB, 232 MachineBasicBlock::iterator MI, 233 unsigned DestReg, int FrameIndex, 234 const TargetRegisterClass *RC) const { 235 assert(0 && "Target didn't implement TargetInstrInfo::loadRegFromStackSlot!"); 236 } 237 238 virtual void loadRegFromAddr(MachineFunction &MF, unsigned DestReg, 239 SmallVectorImpl<MachineOperand> &Addr, 240 const TargetRegisterClass *RC, 241 SmallVectorImpl<MachineInstr*> &NewMIs) const { 242 assert(0 && "Target didn't implement TargetInstrInfo::loadRegFromAddr!"); 243 } 244 245 /// spillCalleeSavedRegisters - Issues instruction(s) to spill all callee 246 /// saved registers and returns true if it isn't possible / profitable to do 247 /// so by issuing a series of store instructions via 248 /// storeRegToStackSlot(). Returns false otherwise. 249 virtual bool spillCalleeSavedRegisters(MachineBasicBlock &MBB, 250 MachineBasicBlock::iterator MI, 251 const std::vector<CalleeSavedInfo> &CSI) const { 252 return false; 253 } 254 255 /// restoreCalleeSavedRegisters - Issues instruction(s) to restore all callee 256 /// saved registers and returns true if it isn't possible / profitable to do 257 /// so by issuing a series of load instructions via loadRegToStackSlot(). 258 /// Returns false otherwise. 259 virtual bool restoreCalleeSavedRegisters(MachineBasicBlock &MBB, 260 MachineBasicBlock::iterator MI, 261 const std::vector<CalleeSavedInfo> &CSI) const { 262 return false; 263 } 264 265 /// foldMemoryOperand - Attempt to fold a load or store of the specified stack 266 /// slot into the specified machine instruction for the specified operand(s). 267 /// If this is possible, a new instruction is returned with the specified 268 /// operand folded, otherwise NULL is returned. The client is responsible for 269 /// removing the old instruction and adding the new one in the instruction 270 /// stream. 271 virtual MachineInstr* foldMemoryOperand(MachineInstr* MI, 272 SmallVectorImpl<unsigned> &Ops, 273 int FrameIndex) const { 274 return 0; 275 } 276 277 /// foldMemoryOperand - Same as the previous version except it allows folding 278 /// of any load and store from / to any address, not just from a specific 279 /// stack slot. 280 virtual MachineInstr* foldMemoryOperand(MachineInstr* MI, 281 SmallVectorImpl<unsigned> &Ops, 282 MachineInstr* LoadMI) const { 283 return 0; 284 } 285 286 /// canFoldMemoryOperand - Returns true if the specified load / store is 287 /// folding is possible. 288 virtual 289 bool canFoldMemoryOperand(MachineInstr *MI, 290 SmallVectorImpl<unsigned> &Ops) const{ 291 return false; 292 } 293 294 /// unfoldMemoryOperand - Separate a single instruction which folded a load or 295 /// a store or a load and a store into two or more instruction. If this is 296 /// possible, returns true as well as the new instructions by reference. 297 virtual bool unfoldMemoryOperand(MachineFunction &MF, MachineInstr *MI, 298 unsigned Reg, bool UnfoldLoad, bool UnfoldStore, 299 SmallVectorImpl<MachineInstr*> &NewMIs) const{ 300 return false; 301 } 302 303 virtual bool unfoldMemoryOperand(SelectionDAG &DAG, SDNode *N, 304 SmallVectorImpl<SDNode*> &NewNodes) const { 305 return false; 306 } 307 308 /// getOpcodeAfterMemoryUnfold - Returns the opcode of the would be new 309 /// instruction after load / store are unfolded from an instruction of the 310 /// specified opcode. It returns zero if the specified unfolding is not 311 /// possible. 312 virtual unsigned getOpcodeAfterMemoryUnfold(unsigned Opc, 313 bool UnfoldLoad, bool UnfoldStore) const { 314 return 0; 315 } 316 317 /// BlockHasNoFallThrough - Return true if the specified block does not 318 /// fall-through into its successor block. This is primarily used when a 319 /// branch is unanalyzable. It is useful for things like unconditional 320 /// indirect branches (jump tables). 321 virtual bool BlockHasNoFallThrough(MachineBasicBlock &MBB) const { 322 return false; 323 } 324 325 /// ReverseBranchCondition - Reverses the branch condition of the specified 326 /// condition list, returning false on success and true if it cannot be 327 /// reversed. 328 virtual bool ReverseBranchCondition(std::vector<MachineOperand> &Cond) const { 329 return true; 330 } 331 332 /// insertNoop - Insert a noop into the instruction stream at the specified 333 /// point. 334 virtual void insertNoop(MachineBasicBlock &MBB, 335 MachineBasicBlock::iterator MI) const { 336 assert(0 && "Target didn't implement insertNoop!"); 337 abort(); 338 } 339 340 /// isPredicated - Returns true if the instruction is already predicated. 341 /// 342 virtual bool isPredicated(const MachineInstr *MI) const { 343 return false; 344 } 345 346 /// isUnpredicatedTerminator - Returns true if the instruction is a 347 /// terminator instruction that has not been predicated. 348 virtual bool isUnpredicatedTerminator(const MachineInstr *MI) const; 349 350 /// PredicateInstruction - Convert the instruction into a predicated 351 /// instruction. It returns true if the operation was successful. 352 virtual 353 bool PredicateInstruction(MachineInstr *MI, 354 const std::vector<MachineOperand> &Pred) const = 0; 355 356 /// SubsumesPredicate - Returns true if the first specified predicate 357 /// subsumes the second, e.g. GE subsumes GT. 358 virtual 359 bool SubsumesPredicate(const std::vector<MachineOperand> &Pred1, 360 const std::vector<MachineOperand> &Pred2) const { 361 return false; 362 } 363 364 /// DefinesPredicate - If the specified instruction defines any predicate 365 /// or condition code register(s) used for predication, returns true as well 366 /// as the definition predicate(s) by reference. 367 virtual bool DefinesPredicate(MachineInstr *MI, 368 std::vector<MachineOperand> &Pred) const { 369 return false; 370 } 371 372 /// getPointerRegClass - Returns a TargetRegisterClass used for pointer 373 /// values. 374 virtual const TargetRegisterClass *getPointerRegClass() const { 375 assert(0 && "Target didn't implement getPointerRegClass!"); 376 abort(); 377 return 0; // Must return a value in order to compile with VS 2005 378 } 379}; 380 381/// TargetInstrInfoImpl - This is the default implementation of 382/// TargetInstrInfo, which just provides a couple of default implementations 383/// for various methods. This separated out because it is implemented in 384/// libcodegen, not in libtarget. 385class TargetInstrInfoImpl : public TargetInstrInfo { 386protected: 387 TargetInstrInfoImpl(const TargetInstrDesc *desc, unsigned NumOpcodes) 388 : TargetInstrInfo(desc, NumOpcodes) {} 389public: 390 virtual MachineInstr *commuteInstruction(MachineInstr *MI) const; 391 virtual bool PredicateInstruction(MachineInstr *MI, 392 const std::vector<MachineOperand> &Pred) const; 393 394}; 395 396} // End llvm namespace 397 398#endif 399