TargetInstrInfo.h revision d45eddd214061bf12ad1e6b86497a41725e61d75
1//===-- llvm/Target/TargetInstrInfo.h - Instruction Info --------*- C++ -*-===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file was developed by the LLVM research group and is distributed under 6// the University of Illinois Open Source License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This file describes the target machine instructions to the code generator. 11// 12//===----------------------------------------------------------------------===// 13 14#ifndef LLVM_TARGET_TARGETINSTRINFO_H 15#define LLVM_TARGET_TARGETINSTRINFO_H 16 17#include "llvm/CodeGen/MachineBasicBlock.h" 18#include "llvm/CodeGen/MachineFunction.h" 19#include "llvm/Support/DataTypes.h" 20#include <vector> 21#include <cassert> 22 23namespace llvm { 24 25class MachineInstr; 26class TargetMachine; 27class MachineCodeForInstruction; 28class TargetRegisterClass; 29class LiveVariables; 30 31//--------------------------------------------------------------------------- 32// Data types used to define information about a single machine instruction 33//--------------------------------------------------------------------------- 34 35typedef short MachineOpCode; 36typedef unsigned InstrSchedClass; 37 38//--------------------------------------------------------------------------- 39// struct TargetInstrDescriptor: 40// Predefined information about each machine instruction. 41// Designed to initialized statically. 42// 43 44const unsigned M_BRANCH_FLAG = 1 << 0; 45const unsigned M_CALL_FLAG = 1 << 1; 46const unsigned M_RET_FLAG = 1 << 2; 47const unsigned M_BARRIER_FLAG = 1 << 3; 48const unsigned M_DELAY_SLOT_FLAG = 1 << 4; 49const unsigned M_LOAD_FLAG = 1 << 5; 50const unsigned M_STORE_FLAG = 1 << 6; 51 52// M_CONVERTIBLE_TO_3_ADDR - This is a 2-address instruction which can be 53// changed into a 3-address instruction if the first two operands cannot be 54// assigned to the same register. The target must implement the 55// TargetInstrInfo::convertToThreeAddress method for this instruction. 56const unsigned M_CONVERTIBLE_TO_3_ADDR = 1 << 7; 57 58// This M_COMMUTABLE - is a 2- or 3-address instruction (of the form X = op Y, 59// Z), which produces the same result if Y and Z are exchanged. 60const unsigned M_COMMUTABLE = 1 << 8; 61 62// M_TERMINATOR_FLAG - Is this instruction part of the terminator for a basic 63// block? Typically this is things like return and branch instructions. 64// Various passes use this to insert code into the bottom of a basic block, but 65// before control flow occurs. 66const unsigned M_TERMINATOR_FLAG = 1 << 9; 67 68// M_USES_CUSTOM_DAG_SCHED_INSERTION - Set if this instruction requires custom 69// insertion support when the DAG scheduler is inserting it into a machine basic 70// block. 71const unsigned M_USES_CUSTOM_DAG_SCHED_INSERTION = 1 << 10; 72 73// M_VARIABLE_OPS - Set if this instruction can have a variable number of extra 74// operands in addition to the minimum number operands specified. 75const unsigned M_VARIABLE_OPS = 1 << 11; 76 77// M_PREDICABLE - Set if this instruction has a predicate operand that 78// controls execution. It may be set to 'always'. 79const unsigned M_PREDICABLE = 1 << 12; 80 81// M_REMATERIALIZIBLE - Set if this instruction can be trivally re-materialized 82// at any time, e.g. constant generation, load from constant pool. 83const unsigned M_REMATERIALIZIBLE = 1 << 13; 84 85// M_CLOBBERS_PRED - Set if this instruction may clobbers the condition code 86// register and / or registers that are used to predicate instructions. 87const unsigned M_CLOBBERS_PRED = 1 << 14; 88 89// M_NOT_DUPLICABLE - Set if this instruction cannot be safely duplicated. 90// (e.g. instructions with unique labels attached). 91const unsigned M_NOT_DUPLICABLE = 1 << 15; 92 93// Machine operand flags 94// M_LOOK_UP_PTR_REG_CLASS - Set if this operand is a pointer value and it 95// requires a callback to look up its register class. 96const unsigned M_LOOK_UP_PTR_REG_CLASS = 1 << 0; 97 98/// M_PREDICATE_OPERAND - Set if this is one of the operands that made up of the 99/// predicate operand that controls an M_PREDICATED instruction. 100const unsigned M_PREDICATE_OPERAND = 1 << 1; 101 102namespace TOI { 103 // Operand constraints: only "tied_to" for now. 104 enum OperandConstraint { 105 TIED_TO = 0 // Must be allocated the same register as. 106 }; 107} 108 109/// TargetOperandInfo - This holds information about one operand of a machine 110/// instruction, indicating the register class for register operands, etc. 111/// 112class TargetOperandInfo { 113public: 114 /// RegClass - This specifies the register class enumeration of the operand 115 /// if the operand is a register. If not, this contains 0. 116 unsigned short RegClass; 117 unsigned short Flags; 118 /// Lower 16 bits are used to specify which constraints are set. The higher 16 119 /// bits are used to specify the value of constraints (4 bits each). 120 unsigned int Constraints; 121 /// Currently no other information. 122}; 123 124 125class TargetInstrDescriptor { 126public: 127 MachineOpCode Opcode; // The opcode. 128 unsigned short numOperands; // Num of args (may be more if variable_ops). 129 const char * Name; // Assembly language mnemonic for the opcode. 130 InstrSchedClass schedClass; // enum identifying instr sched class 131 unsigned Flags; // flags identifying machine instr class 132 unsigned TSFlags; // Target Specific Flag values 133 const unsigned *ImplicitUses; // Registers implicitly read by this instr 134 const unsigned *ImplicitDefs; // Registers implicitly defined by this instr 135 const TargetOperandInfo *OpInfo; // 'numOperands' entries about operands. 136 137 /// getOperandConstraint - Returns the value of the specific constraint if 138 /// it is set. Returns -1 if it is not set. 139 int getOperandConstraint(unsigned OpNum, 140 TOI::OperandConstraint Constraint) const { 141 assert((OpNum < numOperands || (Flags & M_VARIABLE_OPS)) && 142 "Invalid operand # of TargetInstrInfo"); 143 if (OpNum < numOperands && 144 (OpInfo[OpNum].Constraints & (1 << Constraint))) { 145 unsigned Pos = 16 + Constraint * 4; 146 return (int)(OpInfo[OpNum].Constraints >> Pos) & 0xf; 147 } 148 return -1; 149 } 150 151 /// findTiedToSrcOperand - Returns the operand that is tied to the specified 152 /// dest operand. Returns -1 if there isn't one. 153 int findTiedToSrcOperand(unsigned OpNum) const; 154}; 155 156 157//--------------------------------------------------------------------------- 158/// 159/// TargetInstrInfo - Interface to description of machine instructions 160/// 161class TargetInstrInfo { 162 const TargetInstrDescriptor* desc; // raw array to allow static init'n 163 unsigned NumOpcodes; // number of entries in the desc array 164 unsigned numRealOpCodes; // number of non-dummy op codes 165 166 TargetInstrInfo(const TargetInstrInfo &); // DO NOT IMPLEMENT 167 void operator=(const TargetInstrInfo &); // DO NOT IMPLEMENT 168public: 169 TargetInstrInfo(const TargetInstrDescriptor *desc, unsigned NumOpcodes); 170 virtual ~TargetInstrInfo(); 171 172 // Invariant opcodes: All instruction sets have these as their low opcodes. 173 enum { 174 PHI = 0, 175 INLINEASM = 1, 176 LABEL = 2 177 }; 178 179 unsigned getNumOpcodes() const { return NumOpcodes; } 180 181 /// get - Return the machine instruction descriptor that corresponds to the 182 /// specified instruction opcode. 183 /// 184 const TargetInstrDescriptor& get(MachineOpCode Opcode) const { 185 assert((unsigned)Opcode < NumOpcodes); 186 return desc[Opcode]; 187 } 188 189 const char *getName(MachineOpCode Opcode) const { 190 return get(Opcode).Name; 191 } 192 193 int getNumOperands(MachineOpCode Opcode) const { 194 return get(Opcode).numOperands; 195 } 196 197 InstrSchedClass getSchedClass(MachineOpCode Opcode) const { 198 return get(Opcode).schedClass; 199 } 200 201 const unsigned *getImplicitUses(MachineOpCode Opcode) const { 202 return get(Opcode).ImplicitUses; 203 } 204 205 const unsigned *getImplicitDefs(MachineOpCode Opcode) const { 206 return get(Opcode).ImplicitDefs; 207 } 208 209 210 // 211 // Query instruction class flags according to the machine-independent 212 // flags listed above. 213 // 214 bool isReturn(MachineOpCode Opcode) const { 215 return get(Opcode).Flags & M_RET_FLAG; 216 } 217 218 bool isCommutableInstr(MachineOpCode Opcode) const { 219 return get(Opcode).Flags & M_COMMUTABLE; 220 } 221 bool isTerminatorInstr(MachineOpCode Opcode) const { 222 return get(Opcode).Flags & M_TERMINATOR_FLAG; 223 } 224 225 bool isBranch(MachineOpCode Opcode) const { 226 return get(Opcode).Flags & M_BRANCH_FLAG; 227 } 228 229 /// isBarrier - Returns true if the specified instruction stops control flow 230 /// from executing the instruction immediately following it. Examples include 231 /// unconditional branches and return instructions. 232 bool isBarrier(MachineOpCode Opcode) const { 233 return get(Opcode).Flags & M_BARRIER_FLAG; 234 } 235 236 bool isCall(MachineOpCode Opcode) const { 237 return get(Opcode).Flags & M_CALL_FLAG; 238 } 239 bool isLoad(MachineOpCode Opcode) const { 240 return get(Opcode).Flags & M_LOAD_FLAG; 241 } 242 bool isStore(MachineOpCode Opcode) const { 243 return get(Opcode).Flags & M_STORE_FLAG; 244 } 245 246 /// hasDelaySlot - Returns true if the specified instruction has a delay slot 247 /// which must be filled by the code generator. 248 bool hasDelaySlot(MachineOpCode Opcode) const { 249 return get(Opcode).Flags & M_DELAY_SLOT_FLAG; 250 } 251 252 /// usesCustomDAGSchedInsertionHook - Return true if this instruction requires 253 /// custom insertion support when the DAG scheduler is inserting it into a 254 /// machine basic block. 255 bool usesCustomDAGSchedInsertionHook(MachineOpCode Opcode) const { 256 return get(Opcode).Flags & M_USES_CUSTOM_DAG_SCHED_INSERTION; 257 } 258 259 bool hasVariableOperands(MachineOpCode Opcode) const { 260 return get(Opcode).Flags & M_VARIABLE_OPS; 261 } 262 263 bool isPredicable(MachineOpCode Opcode) const { 264 return get(Opcode).Flags & M_PREDICABLE; 265 } 266 267 bool clobbersPredicate(MachineOpCode Opcode) const { 268 return get(Opcode).Flags & M_CLOBBERS_PRED; 269 } 270 271 bool isNotDuplicable(MachineOpCode Opcode) const { 272 return get(Opcode).Flags & M_NOT_DUPLICABLE; 273 } 274 275 /// isTriviallyReMaterializable - Return true if the instruction is trivially 276 /// rematerializable, meaning it has no side effects and requires no operands 277 /// that aren't always available. 278 bool isTriviallyReMaterializable(MachineInstr *MI) const { 279 return (MI->getInstrDescriptor()->Flags & M_REMATERIALIZIBLE) && 280 isReallyTriviallyReMaterializable(MI); 281 } 282 283protected: 284 /// isReallyTriviallyReMaterializable - For instructions with opcodes for 285 /// which the M_REMATERIALIZABLE flag is set, this function tests whether the 286 /// instruction itself is actually trivially rematerializable, considering 287 /// its operands. This is used for targets that have instructions that are 288 /// only trivially rematerializable for specific uses. This predicate must 289 /// return false if the instruction has any side effects other than 290 /// producing a value, or if it requres any address registers that are not 291 /// always available. 292 virtual bool isReallyTriviallyReMaterializable(MachineInstr *MI) const { 293 return true; 294 } 295 296public: 297 /// getOperandConstraint - Returns the value of the specific constraint if 298 /// it is set. Returns -1 if it is not set. 299 int getOperandConstraint(MachineOpCode Opcode, unsigned OpNum, 300 TOI::OperandConstraint Constraint) const { 301 return get(Opcode).getOperandConstraint(OpNum, Constraint); 302 } 303 304 /// Return true if the instruction is a register to register move 305 /// and leave the source and dest operands in the passed parameters. 306 virtual bool isMoveInstr(const MachineInstr& MI, 307 unsigned& sourceReg, 308 unsigned& destReg) const { 309 return false; 310 } 311 312 /// isLoadFromStackSlot - If the specified machine instruction is a direct 313 /// load from a stack slot, return the virtual or physical register number of 314 /// the destination along with the FrameIndex of the loaded stack slot. If 315 /// not, return 0. This predicate must return 0 if the instruction has 316 /// any side effects other than loading from the stack slot. 317 virtual unsigned isLoadFromStackSlot(MachineInstr *MI, int &FrameIndex) const{ 318 return 0; 319 } 320 321 /// isStoreToStackSlot - If the specified machine instruction is a direct 322 /// store to a stack slot, return the virtual or physical register number of 323 /// the source reg along with the FrameIndex of the loaded stack slot. If 324 /// not, return 0. This predicate must return 0 if the instruction has 325 /// any side effects other than storing to the stack slot. 326 virtual unsigned isStoreToStackSlot(MachineInstr *MI, int &FrameIndex) const { 327 return 0; 328 } 329 330 /// convertToThreeAddress - This method must be implemented by targets that 331 /// set the M_CONVERTIBLE_TO_3_ADDR flag. When this flag is set, the target 332 /// may be able to convert a two-address instruction into one or moretrue 333 /// three-address instructions on demand. This allows the X86 target (for 334 /// example) to convert ADD and SHL instructions into LEA instructions if they 335 /// would require register copies due to two-addressness. 336 /// 337 /// This method returns a null pointer if the transformation cannot be 338 /// performed, otherwise it returns the last new instruction. 339 /// 340 virtual MachineInstr * 341 convertToThreeAddress(MachineFunction::iterator &MFI, 342 MachineBasicBlock::iterator &MBBI, LiveVariables &LV) const { 343 return 0; 344 } 345 346 /// commuteInstruction - If a target has any instructions that are commutable, 347 /// but require converting to a different instruction or making non-trivial 348 /// changes to commute them, this method can overloaded to do this. The 349 /// default implementation of this method simply swaps the first two operands 350 /// of MI and returns it. 351 /// 352 /// If a target wants to make more aggressive changes, they can construct and 353 /// return a new machine instruction. If an instruction cannot commute, it 354 /// can also return null. 355 /// 356 virtual MachineInstr *commuteInstruction(MachineInstr *MI) const; 357 358 /// AnalyzeBranch - Analyze the branching code at the end of MBB, returning 359 /// true if it cannot be understood (e.g. it's a switch dispatch or isn't 360 /// implemented for a target). Upon success, this returns false and returns 361 /// with the following information in various cases: 362 /// 363 /// 1. If this block ends with no branches (it just falls through to its succ) 364 /// just return false, leaving TBB/FBB null. 365 /// 2. If this block ends with only an unconditional branch, it sets TBB to be 366 /// the destination block. 367 /// 3. If this block ends with an conditional branch and it falls through to 368 /// an successor block, it sets TBB to be the branch destination block and a 369 /// list of operands that evaluate the condition. These 370 /// operands can be passed to other TargetInstrInfo methods to create new 371 /// branches. 372 /// 4. If this block ends with an conditional branch and an unconditional 373 /// block, it returns the 'true' destination in TBB, the 'false' destination 374 /// in FBB, and a list of operands that evaluate the condition. These 375 /// operands can be passed to other TargetInstrInfo methods to create new 376 /// branches. 377 /// 378 /// Note that RemoveBranch and InsertBranch must be implemented to support 379 /// cases where this method returns success. 380 /// 381 virtual bool AnalyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB, 382 MachineBasicBlock *&FBB, 383 std::vector<MachineOperand> &Cond) const { 384 return true; 385 } 386 387 /// RemoveBranch - Remove the branching code at the end of the specific MBB. 388 /// this is only invoked in cases where AnalyzeBranch returns success. It 389 /// returns the number of instructions that were removed. 390 virtual unsigned RemoveBranch(MachineBasicBlock &MBB) const { 391 assert(0 && "Target didn't implement TargetInstrInfo::RemoveBranch!"); 392 return 0; 393 } 394 395 /// InsertBranch - Insert a branch into the end of the specified 396 /// MachineBasicBlock. This operands to this method are the same as those 397 /// returned by AnalyzeBranch. This is invoked in cases where AnalyzeBranch 398 /// returns success and when an unconditional branch (TBB is non-null, FBB is 399 /// null, Cond is empty) needs to be inserted. It returns the number of 400 /// instructions inserted. 401 virtual unsigned InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB, 402 MachineBasicBlock *FBB, 403 const std::vector<MachineOperand> &Cond) const { 404 assert(0 && "Target didn't implement TargetInstrInfo::InsertBranch!"); 405 return 0; 406 } 407 408 /// BlockHasNoFallThrough - Return true if the specified block does not 409 /// fall-through into its successor block. This is primarily used when a 410 /// branch is unanalyzable. It is useful for things like unconditional 411 /// indirect branches (jump tables). 412 virtual bool BlockHasNoFallThrough(MachineBasicBlock &MBB) const { 413 return false; 414 } 415 416 /// ReverseBranchCondition - Reverses the branch condition of the specified 417 /// condition list, returning false on success and true if it cannot be 418 /// reversed. 419 virtual bool ReverseBranchCondition(std::vector<MachineOperand> &Cond) const { 420 return true; 421 } 422 423 /// insertNoop - Insert a noop into the instruction stream at the specified 424 /// point. 425 virtual void insertNoop(MachineBasicBlock &MBB, 426 MachineBasicBlock::iterator MI) const { 427 assert(0 && "Target didn't implement insertNoop!"); 428 abort(); 429 } 430 431 /// isPredicated - Returns true if the instruction is already predicated. 432 /// 433 virtual bool isPredicated(const MachineInstr *MI) const { 434 return false; 435 } 436 437 /// isUnpredicatedTerminator - Returns true if the instruction is a 438 /// terminator instruction that has not been predicated. 439 virtual bool isUnpredicatedTerminator(const MachineInstr *MI) const; 440 441 /// PredicateInstruction - Convert the instruction into a predicated 442 /// instruction. It returns true if the operation was successful. 443 virtual 444 bool PredicateInstruction(MachineInstr *MI, 445 const std::vector<MachineOperand> &Pred) const; 446 447 /// SubsumesPredicate - Returns true if the first specified predicate 448 /// subsumes the second, e.g. GE subsumes GT. 449 virtual 450 bool SubsumesPredicate(const std::vector<MachineOperand> &Pred1, 451 const std::vector<MachineOperand> &Pred2) const { 452 return false; 453 } 454 455 /// getPointerRegClass - Returns a TargetRegisterClass used for pointer 456 /// values. 457 virtual const TargetRegisterClass *getPointerRegClass() const { 458 assert(0 && "Target didn't implement getPointerRegClass!"); 459 abort(); 460 return 0; // Must return a value in order to compile with VS 2005 461 } 462}; 463 464} // End llvm namespace 465 466#endif 467