TargetInstrInfo.h revision e30eeaaf72b461aebf3dfcdd7c119eea76458561
1//===-- llvm/Target/InstrInfo.h - Target Instruction Information --*-C++-*-==// 2// 3// This file describes the target machine instructions to the code generator. 4// 5//===---------------------------------------------------------------------===// 6 7#ifndef LLVM_TARGET_MACHINEINSTRINFO_H 8#define LLVM_TARGET_MACHINEINSTRINFO_H 9 10#include "Support/DataTypes.h" 11#include <vector> 12 13class MachineInstrDescriptor; 14class MachineInstr; 15class TargetMachine; 16class Value; 17class Instruction; 18class Constant; 19class Function; 20class MachineCodeForInstruction; 21 22//--------------------------------------------------------------------------- 23// Data types used to define information about a single machine instruction 24//--------------------------------------------------------------------------- 25 26typedef int MachineOpCode; 27typedef unsigned InstrSchedClass; 28 29const MachineOpCode INVALID_MACHINE_OPCODE = -1; 30 31 32// Global variable holding an array of descriptors for machine instructions. 33// The actual object needs to be created separately for each target machine. 34// This variable is initialized and reset by class MachineInstrInfo. 35// 36// FIXME: This should be a property of the target so that more than one target 37// at a time can be active... 38// 39extern const MachineInstrDescriptor *TargetInstrDescriptors; 40 41 42//--------------------------------------------------------------------------- 43// struct MachineInstrDescriptor: 44// Predefined information about each machine instruction. 45// Designed to initialized statically. 46// 47// class MachineInstructionInfo 48// Interface to description of machine instructions 49// 50//--------------------------------------------------------------------------- 51 52const unsigned M_NOP_FLAG = 1 << 0; 53const unsigned M_BRANCH_FLAG = 1 << 1; 54const unsigned M_CALL_FLAG = 1 << 2; 55const unsigned M_RET_FLAG = 1 << 3; 56const unsigned M_ARITH_FLAG = 1 << 4; 57const unsigned M_CC_FLAG = 1 << 6; 58const unsigned M_LOGICAL_FLAG = 1 << 6; 59const unsigned M_INT_FLAG = 1 << 7; 60const unsigned M_FLOAT_FLAG = 1 << 8; 61const unsigned M_CONDL_FLAG = 1 << 9; 62const unsigned M_LOAD_FLAG = 1 << 10; 63const unsigned M_PREFETCH_FLAG = 1 << 11; 64const unsigned M_STORE_FLAG = 1 << 12; 65const unsigned M_DUMMY_PHI_FLAG = 1 << 13; 66const unsigned M_PSEUDO_FLAG = 1 << 14; 67 68 69struct MachineInstrDescriptor { 70 const char * opCodeString; // Assembly language mnemonic for the opcode. 71 int numOperands; // Number of args; -1 if variable #args 72 int resultPos; // Position of the result; -1 if no result 73 unsigned maxImmedConst; // Largest +ve constant in IMMMED field or 0. 74 bool immedIsSignExtended; // Is IMMED field sign-extended? If so, 75 // smallest -ve value is -(maxImmedConst+1). 76 unsigned numDelaySlots; // Number of delay slots after instruction 77 unsigned latency; // Latency in machine cycles 78 InstrSchedClass schedClass; // enum identifying instr sched class 79 unsigned iclass; // flags identifying machine instr class 80}; 81 82 83class MachineInstrInfo { 84 const MachineInstrDescriptor* desc; // raw array to allow static init'n 85 unsigned descSize; // number of entries in the desc array 86 unsigned numRealOpCodes; // number of non-dummy op codes 87 88 MachineInstrInfo(const MachineInstrInfo &); // DO NOT IMPLEMENT 89 void operator=(const MachineInstrInfo &); // DO NOT IMPLEMENT 90public: 91 MachineInstrInfo(const MachineInstrDescriptor *desc, unsigned descSize, 92 unsigned numRealOpCodes); 93 virtual ~MachineInstrInfo(); 94 95 unsigned getNumRealOpCodes() const { return numRealOpCodes; } 96 unsigned getNumTotalOpCodes() const { return descSize; } 97 98 /// get - Return the machine instruction descriptor that corresponds to the 99 /// specified instruction opcode. 100 /// 101 const MachineInstrDescriptor& get(MachineOpCode opCode) const { 102 assert(opCode >= 0 && opCode < (int)descSize); 103 return desc[opCode]; 104 } 105 106 int getNumOperands(MachineOpCode opCode) const { 107 return get(opCode).numOperands; 108 } 109 110 int getResultPos(MachineOpCode opCode) const { 111 return get(opCode).resultPos; 112 } 113 114 unsigned getNumDelaySlots(MachineOpCode opCode) const { 115 return get(opCode).numDelaySlots; 116 } 117 118 InstrSchedClass getSchedClass(MachineOpCode opCode) const { 119 return get(opCode).schedClass; 120 } 121 122 // 123 // Query instruction class flags according to the machine-independent 124 // flags listed above. 125 // 126 unsigned getIClass(MachineOpCode opCode) const { 127 return get(opCode).iclass; 128 } 129 bool isNop(MachineOpCode opCode) const { 130 return get(opCode).iclass & M_NOP_FLAG; 131 } 132 bool isBranch(MachineOpCode opCode) const { 133 return get(opCode).iclass & M_BRANCH_FLAG; 134 } 135 bool isCall(MachineOpCode opCode) const { 136 return get(opCode).iclass & M_CALL_FLAG; 137 } 138 bool isReturn(MachineOpCode opCode) const { 139 return get(opCode).iclass & M_RET_FLAG; 140 } 141 bool isControlFlow(MachineOpCode opCode) const { 142 return get(opCode).iclass & M_BRANCH_FLAG 143 || get(opCode).iclass & M_CALL_FLAG 144 || get(opCode).iclass & M_RET_FLAG; 145 } 146 bool isArith(MachineOpCode opCode) const { 147 return get(opCode).iclass & M_ARITH_FLAG; 148 } 149 bool isCCInstr(MachineOpCode opCode) const { 150 return get(opCode).iclass & M_CC_FLAG; 151 } 152 bool isLogical(MachineOpCode opCode) const { 153 return get(opCode).iclass & M_LOGICAL_FLAG; 154 } 155 bool isIntInstr(MachineOpCode opCode) const { 156 return get(opCode).iclass & M_INT_FLAG; 157 } 158 bool isFloatInstr(MachineOpCode opCode) const { 159 return get(opCode).iclass & M_FLOAT_FLAG; 160 } 161 bool isConditional(MachineOpCode opCode) const { 162 return get(opCode).iclass & M_CONDL_FLAG; 163 } 164 bool isLoad(MachineOpCode opCode) const { 165 return get(opCode).iclass & M_LOAD_FLAG; 166 } 167 bool isPrefetch(MachineOpCode opCode) const { 168 return get(opCode).iclass & M_PREFETCH_FLAG; 169 } 170 bool isLoadOrPrefetch(MachineOpCode opCode) const { 171 return get(opCode).iclass & M_LOAD_FLAG 172 || get(opCode).iclass & M_PREFETCH_FLAG; 173 } 174 bool isStore(MachineOpCode opCode) const { 175 return get(opCode).iclass & M_STORE_FLAG; 176 } 177 bool isMemoryAccess(MachineOpCode opCode) const { 178 return get(opCode).iclass & M_LOAD_FLAG 179 || get(opCode).iclass & M_PREFETCH_FLAG 180 || get(opCode).iclass & M_STORE_FLAG; 181 } 182 bool isDummyPhiInstr(const MachineOpCode opCode) const { 183 return get(opCode).iclass & M_DUMMY_PHI_FLAG; 184 } 185 bool isPseudoInstr(const MachineOpCode opCode) const { 186 return get(opCode).iclass & M_PSEUDO_FLAG; 187 } 188 189 // Check if an instruction can be issued before its operands are ready, 190 // or if a subsequent instruction that uses its result can be issued 191 // before the results are ready. 192 // Default to true since most instructions on many architectures allow this. 193 // 194 virtual bool hasOperandInterlock(MachineOpCode opCode) const { 195 return true; 196 } 197 198 virtual bool hasResultInterlock(MachineOpCode opCode) const { 199 return true; 200 } 201 202 // 203 // Latencies for individual instructions and instruction pairs 204 // 205 virtual int minLatency(MachineOpCode opCode) const { 206 return get(opCode).latency; 207 } 208 209 virtual int maxLatency(MachineOpCode opCode) const { 210 return get(opCode).latency; 211 } 212 213 // 214 // Which operand holds an immediate constant? Returns -1 if none 215 // 216 virtual int getImmedConstantPos(MachineOpCode opCode) const { 217 return -1; // immediate position is machine specific, so say -1 == "none" 218 } 219 220 // Check if the specified constant fits in the immediate field 221 // of this machine instruction 222 // 223 virtual bool constantFitsInImmedField(MachineOpCode opCode, 224 int64_t intValue) const; 225 226 // Return the largest +ve constant that can be held in the IMMMED field 227 // of this machine instruction. 228 // isSignExtended is set to true if the value is sign-extended before use 229 // (this is true for all immediate fields in SPARC instructions). 230 // Return 0 if the instruction has no IMMED field. 231 // 232 virtual uint64_t maxImmedConstant(MachineOpCode opCode, 233 bool &isSignExtended) const { 234 isSignExtended = get(opCode).immedIsSignExtended; 235 return get(opCode).maxImmedConst; 236 } 237 238 //------------------------------------------------------------------------- 239 // Queries about representation of LLVM quantities (e.g., constants) 240 //------------------------------------------------------------------------- 241 242 /// ConstantTypeMustBeLoaded - Test if this type of constant must be loaded 243 /// from memory into a register, i.e., cannot be set bitwise in register and 244 /// cannot use immediate fields of instructions. Note that this only makes 245 /// sense for primitive types. 246 /// 247 virtual bool ConstantTypeMustBeLoaded(const Constant* CV) const; 248 249 // Test if this constant may not fit in the immediate field of the 250 // machine instructions (probably) generated for this instruction. 251 // 252 virtual bool ConstantMayNotFitInImmedField(const Constant* CV, 253 const Instruction* I) const { 254 return true; // safe but very conservative 255 } 256 257 //------------------------------------------------------------------------- 258 // Code generation support for creating individual machine instructions 259 //------------------------------------------------------------------------- 260 261 // Get certain common op codes for the current target. this and all the 262 // Create* methods below should be moved to a machine code generation class 263 // 264 virtual MachineOpCode getNOPOpCode() const = 0; 265 266 // Create an instruction sequence to put the constant `val' into 267 // the virtual register `dest'. `val' may be a Constant or a 268 // GlobalValue, viz., the constant address of a global variable or function. 269 // The generated instructions are returned in `mvec'. 270 // Any temp. registers (TmpInstruction) created are recorded in mcfi. 271 // Symbolic constants or constants that must be accessed from memory 272 // are added to the constant pool via MachineFunction::get(F). 273 // 274 virtual void CreateCodeToLoadConst(const TargetMachine& target, 275 Function* F, 276 Value* val, 277 Instruction* dest, 278 std::vector<MachineInstr*>& mvec, 279 MachineCodeForInstruction& mcfi) const=0; 280 281 // Create an instruction sequence to copy an integer value `val' 282 // to a floating point value `dest' by copying to memory and back. 283 // val must be an integral type. dest must be a Float or Double. 284 // The generated instructions are returned in `mvec'. 285 // Any temp. registers (TmpInstruction) created are recorded in mcfi. 286 // Any stack space required is allocated via mcff. 287 // 288 virtual void CreateCodeToCopyIntToFloat(const TargetMachine& target, 289 Function* F, 290 Value* val, 291 Instruction* dest, 292 std::vector<MachineInstr*>& mvec, 293 MachineCodeForInstruction& mcfi)const=0; 294 295 // Similarly, create an instruction sequence to copy an FP value 296 // `val' to an integer value `dest' by copying to memory and back. 297 // The generated instructions are returned in `mvec'. 298 // Any temp. registers (TmpInstruction) created are recorded in mcfi. 299 // Any stack space required is allocated via mcff. 300 // 301 virtual void CreateCodeToCopyFloatToInt(const TargetMachine& target, 302 Function* F, 303 Value* val, 304 Instruction* dest, 305 std::vector<MachineInstr*>& mvec, 306 MachineCodeForInstruction& mcfi)const=0; 307 308 // Create instruction(s) to copy src to dest, for arbitrary types 309 // The generated instructions are returned in `mvec'. 310 // Any temp. registers (TmpInstruction) created are recorded in mcfi. 311 // Any stack space required is allocated via mcff. 312 // 313 virtual void CreateCopyInstructionsByType(const TargetMachine& target, 314 Function* F, 315 Value* src, 316 Instruction* dest, 317 std::vector<MachineInstr*>& mvec, 318 MachineCodeForInstruction& mcfi)const=0; 319 320 // Create instruction sequence to produce a sign-extended register value 321 // from an arbitrary sized value (sized in bits, not bytes). 322 // The generated instructions are appended to `mvec'. 323 // Any temp. registers (TmpInstruction) created are recorded in mcfi. 324 // Any stack space required is allocated via mcff. 325 // 326 virtual void CreateSignExtensionInstructions(const TargetMachine& target, 327 Function* F, 328 Value* srcVal, 329 Value* destVal, 330 unsigned numLowBits, 331 std::vector<MachineInstr*>& mvec, 332 MachineCodeForInstruction& mcfi) const=0; 333 334 // Create instruction sequence to produce a zero-extended register value 335 // from an arbitrary sized value (sized in bits, not bytes). 336 // The generated instructions are appended to `mvec'. 337 // Any temp. registers (TmpInstruction) created are recorded in mcfi. 338 // Any stack space required is allocated via mcff. 339 // 340 virtual void CreateZeroExtensionInstructions(const TargetMachine& target, 341 Function* F, 342 Value* srcVal, 343 Value* destVal, 344 unsigned srcSizeInBits, 345 std::vector<MachineInstr*>& mvec, 346 MachineCodeForInstruction& mcfi) const=0; 347}; 348 349#endif 350