TargetInstrInfo.h revision ed80ef6089ef83bd1c79f1477d7a12a949474af5
1//===-- llvm/Target/TargetInstrInfo.h - Instruction Info --------*- C++ -*-===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file was developed by the LLVM research group and is distributed under 6// the University of Illinois Open Source License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This file describes the target machine instructions to the code generator. 11// 12//===----------------------------------------------------------------------===// 13 14#ifndef LLVM_TARGET_TARGETINSTRINFO_H 15#define LLVM_TARGET_TARGETINSTRINFO_H 16 17#include "llvm/CodeGen/MachineBasicBlock.h" 18#include "llvm/CodeGen/MachineFunction.h" 19#include "llvm/Support/DataTypes.h" 20#include <vector> 21#include <cassert> 22 23namespace llvm { 24 25class MachineInstr; 26class TargetMachine; 27class MachineCodeForInstruction; 28class TargetRegisterClass; 29class LiveVariables; 30 31//--------------------------------------------------------------------------- 32// Data types used to define information about a single machine instruction 33//--------------------------------------------------------------------------- 34 35typedef short MachineOpCode; 36typedef unsigned InstrSchedClass; 37 38//--------------------------------------------------------------------------- 39// struct TargetInstrDescriptor: 40// Predefined information about each machine instruction. 41// Designed to initialized statically. 42// 43 44const unsigned M_BRANCH_FLAG = 1 << 0; 45const unsigned M_CALL_FLAG = 1 << 1; 46const unsigned M_RET_FLAG = 1 << 2; 47const unsigned M_BARRIER_FLAG = 1 << 3; 48const unsigned M_DELAY_SLOT_FLAG = 1 << 4; 49const unsigned M_LOAD_FLAG = 1 << 5; 50const unsigned M_STORE_FLAG = 1 << 6; 51 52// M_CONVERTIBLE_TO_3_ADDR - This is a 2-address instruction which can be 53// changed into a 3-address instruction if the first two operands cannot be 54// assigned to the same register. The target must implement the 55// TargetInstrInfo::convertToThreeAddress method for this instruction. 56const unsigned M_CONVERTIBLE_TO_3_ADDR = 1 << 7; 57 58// This M_COMMUTABLE - is a 2- or 3-address instruction (of the form X = op Y, 59// Z), which produces the same result if Y and Z are exchanged. 60const unsigned M_COMMUTABLE = 1 << 8; 61 62// M_TERMINATOR_FLAG - Is this instruction part of the terminator for a basic 63// block? Typically this is things like return and branch instructions. 64// Various passes use this to insert code into the bottom of a basic block, but 65// before control flow occurs. 66const unsigned M_TERMINATOR_FLAG = 1 << 9; 67 68// M_USES_CUSTOM_DAG_SCHED_INSERTION - Set if this instruction requires custom 69// insertion support when the DAG scheduler is inserting it into a machine basic 70// block. 71const unsigned M_USES_CUSTOM_DAG_SCHED_INSERTION = 1 << 10; 72 73// M_VARIABLE_OPS - Set if this instruction can have a variable number of extra 74// operands in addition to the minimum number operands specified. 75const unsigned M_VARIABLE_OPS = 1 << 11; 76 77// M_PREDICABLE - Set if this instruction has a predicate operand that 78// controls execution. It may be set to 'always'. 79const unsigned M_PREDICABLE = 1 << 12; 80 81// M_REMATERIALIZIBLE - Set if this instruction can be trivally re-materialized 82// at any time, e.g. constant generation, load from constant pool. 83const unsigned M_REMATERIALIZIBLE = 1 << 13; 84 85// M_NOT_DUPLICABLE - Set if this instruction cannot be safely duplicated. 86// (e.g. instructions with unique labels attached). 87const unsigned M_NOT_DUPLICABLE = 1 << 14; 88 89// M_HAS_OPTIONAL_DEF - Set if this instruction has an optional definition, e.g. 90// ARM instructions which can set condition code if 's' bit is set. 91const unsigned M_HAS_OPTIONAL_DEF = 1 << 15; 92 93// Machine operand flags 94// M_LOOK_UP_PTR_REG_CLASS - Set if this operand is a pointer value and it 95// requires a callback to look up its register class. 96const unsigned M_LOOK_UP_PTR_REG_CLASS = 1 << 0; 97 98/// M_PREDICATE_OPERAND - Set if this is one of the operands that made up of the 99/// predicate operand that controls an M_PREDICATED instruction. 100const unsigned M_PREDICATE_OPERAND = 1 << 1; 101 102/// M_OPTIONAL_DEF_OPERAND - Set if this operand is a optional def. 103/// 104const unsigned M_OPTIONAL_DEF_OPERAND = 1 << 2; 105 106namespace TOI { 107 // Operand constraints: only "tied_to" for now. 108 enum OperandConstraint { 109 TIED_TO = 0 // Must be allocated the same register as. 110 }; 111} 112 113/// TargetOperandInfo - This holds information about one operand of a machine 114/// instruction, indicating the register class for register operands, etc. 115/// 116class TargetOperandInfo { 117public: 118 /// RegClass - This specifies the register class enumeration of the operand 119 /// if the operand is a register. If not, this contains 0. 120 unsigned short RegClass; 121 unsigned short Flags; 122 /// Lower 16 bits are used to specify which constraints are set. The higher 16 123 /// bits are used to specify the value of constraints (4 bits each). 124 unsigned int Constraints; 125 /// Currently no other information. 126}; 127 128 129class TargetInstrDescriptor { 130public: 131 MachineOpCode Opcode; // The opcode. 132 unsigned short numOperands; // Num of args (may be more if variable_ops). 133 const char * Name; // Assembly language mnemonic for the opcode. 134 InstrSchedClass schedClass; // enum identifying instr sched class 135 unsigned Flags; // flags identifying machine instr class 136 unsigned TSFlags; // Target Specific Flag values 137 const unsigned *ImplicitUses; // Registers implicitly read by this instr 138 const unsigned *ImplicitDefs; // Registers implicitly defined by this instr 139 const TargetOperandInfo *OpInfo; // 'numOperands' entries about operands. 140 141 /// getOperandConstraint - Returns the value of the specific constraint if 142 /// it is set. Returns -1 if it is not set. 143 int getOperandConstraint(unsigned OpNum, 144 TOI::OperandConstraint Constraint) const { 145 assert((OpNum < numOperands || (Flags & M_VARIABLE_OPS)) && 146 "Invalid operand # of TargetInstrInfo"); 147 if (OpNum < numOperands && 148 (OpInfo[OpNum].Constraints & (1 << Constraint))) { 149 unsigned Pos = 16 + Constraint * 4; 150 return (int)(OpInfo[OpNum].Constraints >> Pos) & 0xf; 151 } 152 return -1; 153 } 154 155 /// findTiedToSrcOperand - Returns the operand that is tied to the specified 156 /// dest operand. Returns -1 if there isn't one. 157 int findTiedToSrcOperand(unsigned OpNum) const; 158}; 159 160 161//--------------------------------------------------------------------------- 162/// 163/// TargetInstrInfo - Interface to description of machine instructions 164/// 165class TargetInstrInfo { 166 const TargetInstrDescriptor* desc; // raw array to allow static init'n 167 unsigned NumOpcodes; // number of entries in the desc array 168 unsigned numRealOpCodes; // number of non-dummy op codes 169 170 TargetInstrInfo(const TargetInstrInfo &); // DO NOT IMPLEMENT 171 void operator=(const TargetInstrInfo &); // DO NOT IMPLEMENT 172public: 173 TargetInstrInfo(const TargetInstrDescriptor *desc, unsigned NumOpcodes); 174 virtual ~TargetInstrInfo(); 175 176 // Invariant opcodes: All instruction sets have these as their low opcodes. 177 enum { 178 PHI = 0, 179 INLINEASM = 1, 180 LABEL = 2 181 }; 182 183 unsigned getNumOpcodes() const { return NumOpcodes; } 184 185 /// get - Return the machine instruction descriptor that corresponds to the 186 /// specified instruction opcode. 187 /// 188 const TargetInstrDescriptor& get(MachineOpCode Opcode) const { 189 assert((unsigned)Opcode < NumOpcodes); 190 return desc[Opcode]; 191 } 192 193 const char *getName(MachineOpCode Opcode) const { 194 return get(Opcode).Name; 195 } 196 197 int getNumOperands(MachineOpCode Opcode) const { 198 return get(Opcode).numOperands; 199 } 200 201 InstrSchedClass getSchedClass(MachineOpCode Opcode) const { 202 return get(Opcode).schedClass; 203 } 204 205 const unsigned *getImplicitUses(MachineOpCode Opcode) const { 206 return get(Opcode).ImplicitUses; 207 } 208 209 const unsigned *getImplicitDefs(MachineOpCode Opcode) const { 210 return get(Opcode).ImplicitDefs; 211 } 212 213 214 // 215 // Query instruction class flags according to the machine-independent 216 // flags listed above. 217 // 218 bool isReturn(MachineOpCode Opcode) const { 219 return get(Opcode).Flags & M_RET_FLAG; 220 } 221 222 bool isCommutableInstr(MachineOpCode Opcode) const { 223 return get(Opcode).Flags & M_COMMUTABLE; 224 } 225 bool isTerminatorInstr(MachineOpCode Opcode) const { 226 return get(Opcode).Flags & M_TERMINATOR_FLAG; 227 } 228 229 bool isBranch(MachineOpCode Opcode) const { 230 return get(Opcode).Flags & M_BRANCH_FLAG; 231 } 232 233 /// isBarrier - Returns true if the specified instruction stops control flow 234 /// from executing the instruction immediately following it. Examples include 235 /// unconditional branches and return instructions. 236 bool isBarrier(MachineOpCode Opcode) const { 237 return get(Opcode).Flags & M_BARRIER_FLAG; 238 } 239 240 bool isCall(MachineOpCode Opcode) const { 241 return get(Opcode).Flags & M_CALL_FLAG; 242 } 243 bool isLoad(MachineOpCode Opcode) const { 244 return get(Opcode).Flags & M_LOAD_FLAG; 245 } 246 bool isStore(MachineOpCode Opcode) const { 247 return get(Opcode).Flags & M_STORE_FLAG; 248 } 249 250 /// hasDelaySlot - Returns true if the specified instruction has a delay slot 251 /// which must be filled by the code generator. 252 bool hasDelaySlot(MachineOpCode Opcode) const { 253 return get(Opcode).Flags & M_DELAY_SLOT_FLAG; 254 } 255 256 /// usesCustomDAGSchedInsertionHook - Return true if this instruction requires 257 /// custom insertion support when the DAG scheduler is inserting it into a 258 /// machine basic block. 259 bool usesCustomDAGSchedInsertionHook(MachineOpCode Opcode) const { 260 return get(Opcode).Flags & M_USES_CUSTOM_DAG_SCHED_INSERTION; 261 } 262 263 bool hasVariableOperands(MachineOpCode Opcode) const { 264 return get(Opcode).Flags & M_VARIABLE_OPS; 265 } 266 267 bool isPredicable(MachineOpCode Opcode) const { 268 return get(Opcode).Flags & M_PREDICABLE; 269 } 270 271 bool isNotDuplicable(MachineOpCode Opcode) const { 272 return get(Opcode).Flags & M_NOT_DUPLICABLE; 273 } 274 275 bool hasOptionalDef(MachineOpCode Opcode) const { 276 return get(Opcode).Flags & M_HAS_OPTIONAL_DEF; 277 } 278 279 /// isTriviallyReMaterializable - Return true if the instruction is trivially 280 /// rematerializable, meaning it has no side effects and requires no operands 281 /// that aren't always available. 282 bool isTriviallyReMaterializable(MachineInstr *MI) const { 283 return (MI->getInstrDescriptor()->Flags & M_REMATERIALIZIBLE) && 284 isReallyTriviallyReMaterializable(MI); 285 } 286 287protected: 288 /// isReallyTriviallyReMaterializable - For instructions with opcodes for 289 /// which the M_REMATERIALIZABLE flag is set, this function tests whether the 290 /// instruction itself is actually trivially rematerializable, considering 291 /// its operands. This is used for targets that have instructions that are 292 /// only trivially rematerializable for specific uses. This predicate must 293 /// return false if the instruction has any side effects other than 294 /// producing a value, or if it requres any address registers that are not 295 /// always available. 296 virtual bool isReallyTriviallyReMaterializable(MachineInstr *MI) const { 297 return true; 298 } 299 300public: 301 /// getOperandConstraint - Returns the value of the specific constraint if 302 /// it is set. Returns -1 if it is not set. 303 int getOperandConstraint(MachineOpCode Opcode, unsigned OpNum, 304 TOI::OperandConstraint Constraint) const { 305 return get(Opcode).getOperandConstraint(OpNum, Constraint); 306 } 307 308 /// Return true if the instruction is a register to register move 309 /// and leave the source and dest operands in the passed parameters. 310 virtual bool isMoveInstr(const MachineInstr& MI, 311 unsigned& sourceReg, 312 unsigned& destReg) const { 313 return false; 314 } 315 316 /// isLoadFromStackSlot - If the specified machine instruction is a direct 317 /// load from a stack slot, return the virtual or physical register number of 318 /// the destination along with the FrameIndex of the loaded stack slot. If 319 /// not, return 0. This predicate must return 0 if the instruction has 320 /// any side effects other than loading from the stack slot. 321 virtual unsigned isLoadFromStackSlot(MachineInstr *MI, int &FrameIndex) const{ 322 return 0; 323 } 324 325 /// isStoreToStackSlot - If the specified machine instruction is a direct 326 /// store to a stack slot, return the virtual or physical register number of 327 /// the source reg along with the FrameIndex of the loaded stack slot. If 328 /// not, return 0. This predicate must return 0 if the instruction has 329 /// any side effects other than storing to the stack slot. 330 virtual unsigned isStoreToStackSlot(MachineInstr *MI, int &FrameIndex) const { 331 return 0; 332 } 333 334 /// convertToThreeAddress - This method must be implemented by targets that 335 /// set the M_CONVERTIBLE_TO_3_ADDR flag. When this flag is set, the target 336 /// may be able to convert a two-address instruction into one or more true 337 /// three-address instructions on demand. This allows the X86 target (for 338 /// example) to convert ADD and SHL instructions into LEA instructions if they 339 /// would require register copies due to two-addressness. 340 /// 341 /// This method returns a null pointer if the transformation cannot be 342 /// performed, otherwise it returns the last new instruction. 343 /// 344 virtual MachineInstr * 345 convertToThreeAddress(MachineFunction::iterator &MFI, 346 MachineBasicBlock::iterator &MBBI, LiveVariables &LV) const { 347 return 0; 348 } 349 350 /// commuteInstruction - If a target has any instructions that are commutable, 351 /// but require converting to a different instruction or making non-trivial 352 /// changes to commute them, this method can overloaded to do this. The 353 /// default implementation of this method simply swaps the first two operands 354 /// of MI and returns it. 355 /// 356 /// If a target wants to make more aggressive changes, they can construct and 357 /// return a new machine instruction. If an instruction cannot commute, it 358 /// can also return null. 359 /// 360 virtual MachineInstr *commuteInstruction(MachineInstr *MI) const; 361 362 /// AnalyzeBranch - Analyze the branching code at the end of MBB, returning 363 /// true if it cannot be understood (e.g. it's a switch dispatch or isn't 364 /// implemented for a target). Upon success, this returns false and returns 365 /// with the following information in various cases: 366 /// 367 /// 1. If this block ends with no branches (it just falls through to its succ) 368 /// just return false, leaving TBB/FBB null. 369 /// 2. If this block ends with only an unconditional branch, it sets TBB to be 370 /// the destination block. 371 /// 3. If this block ends with an conditional branch and it falls through to 372 /// an successor block, it sets TBB to be the branch destination block and a 373 /// list of operands that evaluate the condition. These 374 /// operands can be passed to other TargetInstrInfo methods to create new 375 /// branches. 376 /// 4. If this block ends with an conditional branch and an unconditional 377 /// block, it returns the 'true' destination in TBB, the 'false' destination 378 /// in FBB, and a list of operands that evaluate the condition. These 379 /// operands can be passed to other TargetInstrInfo methods to create new 380 /// branches. 381 /// 382 /// Note that RemoveBranch and InsertBranch must be implemented to support 383 /// cases where this method returns success. 384 /// 385 virtual bool AnalyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB, 386 MachineBasicBlock *&FBB, 387 std::vector<MachineOperand> &Cond) const { 388 return true; 389 } 390 391 /// RemoveBranch - Remove the branching code at the end of the specific MBB. 392 /// this is only invoked in cases where AnalyzeBranch returns success. It 393 /// returns the number of instructions that were removed. 394 virtual unsigned RemoveBranch(MachineBasicBlock &MBB) const { 395 assert(0 && "Target didn't implement TargetInstrInfo::RemoveBranch!"); 396 return 0; 397 } 398 399 /// InsertBranch - Insert a branch into the end of the specified 400 /// MachineBasicBlock. This operands to this method are the same as those 401 /// returned by AnalyzeBranch. This is invoked in cases where AnalyzeBranch 402 /// returns success and when an unconditional branch (TBB is non-null, FBB is 403 /// null, Cond is empty) needs to be inserted. It returns the number of 404 /// instructions inserted. 405 virtual unsigned InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB, 406 MachineBasicBlock *FBB, 407 const std::vector<MachineOperand> &Cond) const { 408 assert(0 && "Target didn't implement TargetInstrInfo::InsertBranch!"); 409 return 0; 410 } 411 412 /// BlockHasNoFallThrough - Return true if the specified block does not 413 /// fall-through into its successor block. This is primarily used when a 414 /// branch is unanalyzable. It is useful for things like unconditional 415 /// indirect branches (jump tables). 416 virtual bool BlockHasNoFallThrough(MachineBasicBlock &MBB) const { 417 return false; 418 } 419 420 /// ReverseBranchCondition - Reverses the branch condition of the specified 421 /// condition list, returning false on success and true if it cannot be 422 /// reversed. 423 virtual bool ReverseBranchCondition(std::vector<MachineOperand> &Cond) const { 424 return true; 425 } 426 427 /// insertNoop - Insert a noop into the instruction stream at the specified 428 /// point. 429 virtual void insertNoop(MachineBasicBlock &MBB, 430 MachineBasicBlock::iterator MI) const { 431 assert(0 && "Target didn't implement insertNoop!"); 432 abort(); 433 } 434 435 /// isPredicated - Returns true if the instruction is already predicated. 436 /// 437 virtual bool isPredicated(const MachineInstr *MI) const { 438 return false; 439 } 440 441 /// isUnpredicatedTerminator - Returns true if the instruction is a 442 /// terminator instruction that has not been predicated. 443 virtual bool isUnpredicatedTerminator(const MachineInstr *MI) const; 444 445 /// PredicateInstruction - Convert the instruction into a predicated 446 /// instruction. It returns true if the operation was successful. 447 virtual 448 bool PredicateInstruction(MachineInstr *MI, 449 const std::vector<MachineOperand> &Pred) const; 450 451 /// SubsumesPredicate - Returns true if the first specified predicate 452 /// subsumes the second, e.g. GE subsumes GT. 453 virtual 454 bool SubsumesPredicate(const std::vector<MachineOperand> &Pred1, 455 const std::vector<MachineOperand> &Pred2) const { 456 return false; 457 } 458 459 /// DefinesPredicate - If the specified instruction defines any predicate 460 /// or condition code register(s) used for predication, returns true as well 461 /// as the definition predicate(s) by reference. 462 virtual bool DefinesPredicate(MachineInstr *MI, 463 std::vector<MachineOperand> &Pred) const { 464 return false; 465 } 466 467 /// getPointerRegClass - Returns a TargetRegisterClass used for pointer 468 /// values. 469 virtual const TargetRegisterClass *getPointerRegClass() const { 470 assert(0 && "Target didn't implement getPointerRegClass!"); 471 abort(); 472 return 0; // Must return a value in order to compile with VS 2005 473 } 474}; 475 476} // End llvm namespace 477 478#endif 479